Semiconductor device, manufacturing method thereof and storage system

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and a storage system. The device comprises a plurality of semiconductor columns extending in a third direction, a plurality of gate structures extending in a first direction and a shielding structure, the gate structures and the shielding structures are distributed in a staggered mode in the second direction, and the semiconductor columns are located between the adjacent shielding structures and gate structures; wherein the size of the gate structure in the first direction is smaller than that of the shielding structure in the first direction, and the orthographic projection of the gate structure in the second direction is located in the range of the orthographic projection of the shielding structure.

Description

Semiconductor device, manufacturing method thereof, and storage system Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and a storage system. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing technologies become challenging and costly, which causes the storage density of 2D structured memories to approach an upper limit.

[0003] To overcome the limitations of 2D structured memories, the industry has developed memories with three-dimensional structures to increase storage density.

[0004] However, as the integration density of memories increases, how to properly arrange the layout of various gate lines to reduce mutual interference between the gate lines remains a problem to be overcome.

[0005] Summary of the Invention

[0006] The present application provides a semiconductor device and a manufacturing method thereof, and a storage system, which can improve the yield and reliability of the memory.

[0007] a first region, the first region including a semiconductor pillar array, the semiconductor pillar array including a plurality of semiconductor pillars arranged in an array along a first direction and a second direction and extending in a third direction; the first direction, the second direction, and the third direction intersect each other; and

[0008] A gate structure extending along the first direction is provided on a sidewall of each of the semiconductor pillars;

[0009] A shielding structure extending along the first direction is provided between adjacent semiconductor pillars; the gate structures on the sidewalls of adjacent semiconductor pillars are located on different sides, and the gate structure and the shielding structure are located on different sides of the same semiconductor pillar;

[0010] The size of the gate structure along the first direction is smaller than the size of the shielding structure along the first direction, and the orthographic projection of the gate structure along the second direction is within the range of the orthographic projection of the shielding structure.

[0011] In a second aspect, the present application further provides a method for manufacturing a semiconductor device, comprising:

[0012] providing a substrate;

[0013] forming first grooves in the substrate extending along a second direction and arranged at intervals along the first direction; the first direction intersects the second direction;

[0014] depositing a dielectric material in the first groove;

[0015] forming a second groove and a third groove extending along the first direction in the substrate, wherein the second groove and the third groove are alternately arranged along the second direction, a dimension of the second groove along the first direction is smaller than a dimension of the third groove along the first direction, and an orthographic projection of the second groove along the second direction is within the range of an orthographic projection of the third groove;

[0016] forming a gate line structure in the second groove;

[0017] A shielding structure is formed in the third groove.

[0018] In a third aspect, the present application also provides a storage system, including: a memory controller and a three-dimensional memory, the memory controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes one or more semiconductor devices described in the first aspect.

[0019] Beneficial effects of the present application: The extension dimension of the shielding structure of the present application in the first direction is greater than the extension dimension of the gate structure in the first direction. With such a design, the shielding structure can be led out through the end extending beyond the gate structure along the first direction, which facilitates the lead-out while reducing interference between different signals and improving the stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0021] FIG1 is a cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0022] FIG2 is a top view of a substrate of a semiconductor device provided in an embodiment of the present application;

[0023] FIG3 is a top view of a first groove formed according to an embodiment of the present application;

[0024] FIG4 is a cross-sectional view of a first groove formed along the EE' cutting line in FIG3 according to an embodiment of the present application;

[0025] FIG5 is a top view of a dielectric material deposited in a first groove according to an embodiment of the present application;

[0026] FIG6 is a cross-sectional view of depositing a dielectric material in a first groove according to an embodiment of the present application;

[0027] FIG7 is a top view of the second groove and the third groove provided in an embodiment of the present application;

[0028] FIG8 is a cross-sectional view of the second groove and the third groove formed along the AA′ cutting line in FIG7 according to an embodiment of the present application;

[0029] FIG9 is a top view of a shielding structure and a gate structure provided in an embodiment of the present application;

[0030] FIG10 is a cross-sectional view of a shielding structure and a gate structure provided in an embodiment of the present application;

[0031] FIG11 is a cross-sectional structural diagram of a shielding structure and a gate structure provided in an embodiment of the present application;

[0032] FIG12 is a top view of a semiconductor device provided in an embodiment of the present application;

[0033] FIG13 is a cross-sectional view of the semiconductor device provided in an embodiment of the present application taken along the BB′ cutting line in FIG12 ;

[0034] FIG14 is another top view of the semiconductor device provided in an embodiment of the present application;

[0035] 15 and 16 are cross-sectional views of the semiconductor device provided by an embodiment of the present application taken along the CC' cutting line in FIG. 14 ;

[0036] 17 and 18 are cross-sectional views of the semiconductor device provided by an embodiment of the present application taken along the DD′ cutting line in FIG. 14 ;

[0037] FIG19 is another top view of the semiconductor device provided in an embodiment of the present application;

[0038] 20 and 21 are cross-sectional views of the semiconductor device provided by an embodiment of the present application taken along the DD′ cutting line in FIG. 19 ;

[0039] FIG22 is a structural diagram of a semiconductor device provided in an embodiment of the present application;

[0040] FIG23 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0041] Figure 24 is a structural diagram of the storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0043] As the density of semiconductor memory devices continues to increase, the physical size of memory cells shrinks. This brings the word lines within a memory cell closer together, increasing the capacitive coupling between adjacent word lines. When the number of accesses to a row of memory cells exceeds a threshold, data anomalies in nearby rows can occur. This phenomenon is commonly known as the row hammer effect. Row hammer refers to the phenomenon where repeated accesses to a word line over a period of time cause the adjacent word line sharing the same bit line to open, leading to loss of information stored in the capacitor.

[0044] Among them, Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It is composed of many repeated memory cells, and different memory cells need to be selected through word lines and bit lines. DRAM includes a memory cell region composed of multiple memory cells and a peripheral component region composed of control circuits. Each memory cell includes a transistor electrically connected to a capacitor, and the transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit uses word lines (WL) and bit lines (BL) that span the memory region and are electrically connected to each memory cell to locate each memory cell to control the access of its data.

[0045] As the manufacturing processes for semiconductor devices like dynamic random access memory (DRAM) become more sophisticated, the row hammer effect often occurs as device dimensions shrink. Because DRAM contains numerous word lines arranged adjacent to each other, when a row hammer effect occurs on a word line, data errors may occur in memory cells on adjacent word lines.

[0046] In some related technologies, DRAM periodically performs refresh operations to preserve the charge stored in memory cells and prevent data loss. Increasing the frequency of periodic refreshes can mitigate the harm caused by the row hammer effect to a certain extent, ensuring that each row is refreshed before the effect can cause sufficient damage to the cell charge to cause errors. However, this approach consumes unnecessary time or power to refresh other rows that have not experienced the row hammer effect. This prevents memory devices receiving refresh commands from limiting their refresh range to rows affected by the row hammer effect. This increases system power and reduces system performance because the additional refresh cycles reduce storage system bandwidth.

[0047] As shown in Figure 1, a partial cross-sectional view of a semiconductor device 1000 having a transistor array (not shown in the figure), the transistor array includes a columnar channel 103, and the transistor array includes transistors arranged in an array. The columnar channels 103 of the transistor array are distributed in an array along a first direction and a second direction, and the extension direction of the columnar channels 103 is perpendicular to the plane formed by the first direction and the second direction. A gate oxide layer 104 and a gate structure 102 are provided on one side wall of each columnar channel 103 of the transistor array, wherein the gate structure 102 extends along the first direction, and the two ends of the extension direction of each columnar channel 103 of the transistor array respectively have a source region 101 and a drain region 105 of the transistor. In some embodiments, the positions of the source region 101 and the drain region 105 can be interchanged. Here, the X direction is the first direction, and the Y direction is the second direction. However, as shown in FIG1 , the columnar trench 103 coupled to the unselected word line adjacent to the selected word line is easily affected, mainly in that the activity on the adjacent word line can cause the charge in the cell of the unselected word line to change, which poses a risk to the information stored therein. For example, when the selected word line connected to the columnar trench 103a is active, it will interfere with the adjacent columnar trench 103b, affecting the performance of the device, and therefore further improvement is needed. In other related technologies, an air gap structure is formed between adjacent columnar trenches 103, but this approach has high requirements for process consistency. Alternatively, in other related technologies, a metal layer (not shown in the figure) is formed between adjacent columnar trenches 103 to electrically isolate adjacent columnar trenches 103. However, since the extraction of structures such as bit lines, word lines, and metal layers is also required in subsequent processes, the circuit wiring in the storage array area of ​​the memory is more complicated, the manufacturing process is more difficult, and the cost is increased.

[0048] To improve the above-mentioned problems, with reference to Figures 2 to 24, embodiments of the present application provide a semiconductor device 100, a method for manufacturing the same, and a storage system. The shield structure 30 of the present application has a larger extension dimension in the first direction than the gate structure 10. This allows the shield structure 30 to be led out through the end extending beyond the gate structure 10 in the first direction. This separate leading-out of the shield structure 30 not only facilitates the leading-out but also eliminates the hammer effect. The semiconductor device 100 of the present application has a low manufacturing cost and improves the yield loss caused by the hammer effect, reducing the requirements for process consistency, simplifying the manufacturing process, and reducing manufacturing costs.

[0049] FIG. 23 is a flow chart of a method for manufacturing a semiconductor device 100 according to an embodiment of the present application. The specific flow chart, referring to the structural diagrams of FIG. 2 to FIG. 22 , may include the following steps:

[0050] Step S100, as shown in FIG2, provides a substrate 1;

[0051] Step S200 , as shown in FIG3 , forms first grooves K1 in the substrate 1 extending along the second direction Y and arranged at intervals along the first direction X; the first direction X intersects the second direction Y.

[0052] In some embodiments, the first direction X and the second direction Y form an angle therebetween, and the third direction Z forms an angle therebetween with the plane containing the first direction X and the second direction Y, wherein the angle is less than or equal to 90 degrees. For example, in some embodiments of the present application, the first direction X is defined as the X direction, the second direction Y is defined as the Y direction, and the third direction Z is defined as the Z direction.

[0053] In some embodiments of the present application, the substrate 1 may include a first region R1 as shown in Figures 12 and 14. The first region R1 may include a core device region for forming a transistor array, a memory cell, and / or other required components. The transistor array includes a plurality of transistors, each of which includes a semiconductor pillar 20. In addition, as shown in Figure 22, the opposite ends of the semiconductor pillar 20 extending along the third direction Z respectively form a source 145 and a drain 141 of the transistor, and the sidewalls of the semiconductor pillar 20 are provided with a gate structure 10 of the transistor.

[0054] In some embodiments, substrate 1 is a material used to fabricate semiconductor device 100. The material of substrate 1 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. Substrate 1 may include a wafer formed from cylindrical single crystal silicon through steps such as grinding, polishing, and slicing.

[0055] 2-22 are process diagrams of a method for manufacturing a semiconductor device 100 according to an embodiment of the present application. It should be noted that in the embodiments of the present application, the gate structures 10 on the sidewalls of adjacent semiconductor pillars 20 are located on different sides as an example.

[0056] In some embodiments, step S200 of forming first grooves K1 in the substrate 1 extending along the second direction Y and arranged at intervals along the first direction X includes: etching from the surface of the substrate 1 as shown in FIG. 2 to form the first grooves K1 extending along the second direction Y and arranged at intervals along the first direction X, and the first grooves K1 may extend to the substrate 1 along the third direction Z. That is, as shown in FIG. 1 , FIG. 2 , the substrate 1 is etched from the surface of the substrate 1 along the third direction Z to form a plurality of first grooves K1 extending along the second direction Y and arranged at intervals along the first direction X.

[0057] In some embodiments, the substrate 1 may be etched using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching, or reactive ion etching, which are not limited in some embodiments of the present application.

[0058] As shown in Figures 2, 3, and 4, during the etching process of substrate 1, a mask (not shown) can be used to cover portions of the surface of substrate 1, i.e., the regions where first grooves K1 are to be formed. The surface of substrate 1 is then etched along the thickness direction of substrate 1 (i.e., the third direction Z). Outside the regions covered by the mask, a portion of the semiconductor material of substrate 1 is etched away, forming a groove of a certain depth, i.e., the aforementioned first groove K1.

[0059] In some embodiments, the etching depth for forming the first groove K1 is less than the initial thickness of the substrate 1 , that is, the etching process does not penetrate the substrate 1 . Thus, part of the semiconductor material of a portion of the substrate 1 is removed to form the first groove K1 .

[0060] In some embodiments of the present application, by etching the entire surface of the substrate 1 to synchronously form a plurality of first grooves K1 having the same depth, the manufacturing process can be simplified and the efficiency can be improved.

[0061] Step S300 : depositing a dielectric material 401 in the first groove K1 .

[0062] In some embodiments of the present application, FIG5 is a top view of a dielectric material 401 deposited in a first groove K1, and FIG6 is a cross-sectional view of a dielectric material 401 deposited in a first groove K1, according to some embodiments of the present application. After forming the first groove K1 as shown in FIG3 and FIG4 , as shown in FIG5 and FIG6 , a dielectric material 401 is deposited in the first groove K1 using a deposition process.

[0063] In some embodiments, dielectric material 401 includes but is not limited to any one of polysilicon, silicon nitride, silicon oxide, and aluminum oxide, or any combination thereof. Silicon oxide herein refers to silicon oxide compounds, such as SixOy, and silicon nitride refers to silicon nitrogen compounds, such as SixNy.

[0064] Since the first grooves K1 are formed as shown in Figures 3 and 4, and multiple first grooves K1 are arranged at intervals along the first direction X, there will be a protruding structure 211 between the first grooves K1 formed by removing a portion of the semiconductor material in the substrate 1 to separate the two adjacent first grooves K1. It should be noted that during the actual deposition of the dielectric material 401, the dielectric material 401 will cover the surface of the protruding structure 211. As shown in Figure 5, the dielectric material 401 is filled around each protruding structure 211. In addition, after the deposition is completed, a chemical mechanical polishing (CMP) process can be used to polish away the excess dielectric material 401.

[0065] In some embodiments of the present application, the deposition method of the dielectric material 401 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0066] Step S400: forming a second groove K2 and a third groove K3 extending along the first direction X in the substrate 1, wherein the second groove K2 and the third groove K3 are arranged alternately along the second direction Y, and a size of the second groove K2 along the first direction X is smaller than a size of the third groove K3 along the first direction X, and an orthographic projection of the second groove K2 along the second direction Y is within the range of an orthographic projection of the third groove K3.

[0067] In some embodiments of the present application, after the dielectric material 401 is filled into the first groove K1, a second groove K2 and a third groove K3 extending along the first direction X are formed in the substrate 1. Multiple second grooves K2 and multiple third grooves K3 are staggered along the second direction Y, and the semiconductor pillars 20 are located between adjacent second grooves K2 and third grooves K3. That is, as shown in Figures 7 and 8, the second grooves K2 and third grooves K3 are staggered along the second direction Y. Simultaneously forming the second grooves K2 and the third grooves K3 extending along the first direction X can simplify the manufacturing process and improve efficiency. Of course, in the embodiments of the present application, the second grooves K2 and the third grooves K3 can also be formed in steps.

[0068] As shown in Figure 7, the first etching length of the second groove K2 (i.e., the extension dimension L1 of the second groove K2 along the first direction X) is smaller than the second etching length of the third groove K3 (i.e., the extension dimension L2 of the second groove K2 along the first direction X). The etching length can be controlled by etching process parameters (e.g., etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, when the etching rate is constant, the longer the etching time, the wider the groove formed in the first direction X. In one embodiment of the present application, the etching process parameters can be adjusted so that the second etching length of the third groove K3 is greater than the first etching length of the second groove K2. The etching method can be dry etching, and the dry etching can be, for example, plasma etching.

[0069] In some embodiments of the present application, the manufacturing method of the semiconductor device 100 may further include the steps of: making the size of the second groove K2 along the third direction Z larger than the size of the third groove K3 along the third direction Z, and the orthographic projection of the second groove K2 along the second direction Y is located within the range of the orthographic projection of the third groove K3, and the first direction X, the second direction Y and the third direction Z intersect with each other.

[0070] In some embodiments, etching the substrate 1 can be performed, for example, using a dry etching process or a wet etching process. If the substrate 1 is etched using a dry etching process, the extension dimensions of the second groove K2 and the third groove K3 along the third direction Z can be controlled by controlling the dry etching time. As shown in FIG8 , the first etching depth of the second groove K2 (i.e., the extension dimension H1 along the third direction Z) is greater than the second etching depth of the third groove K3 (i.e., the extension dimension H2 along the third direction Z).

[0071] In some embodiments, the etching depth can be controlled by etching process parameters (e.g., etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, under a constant etching rate, the longer the etching time, the deeper the groove formed in the third direction Z. In one embodiment of the present application, the etching process parameters can be adjusted so that the first etching depth of the second groove K2 is greater than the second etching depth of the third groove K3. The etching method can be dry etching, which can be, for example, plasma etching.

[0072] Figure 7 is a top view of etching to form the second and third recesses K2 and K3, as provided in some embodiments of the present application. Figure 8 is a cross-sectional view of etching to form the second and third recesses K2 and K3, as provided in some embodiments of the present application. As shown in Figures 7 and 8, portions of the dielectric material filling between the protruding structures 211 in the substrate 1 are removed to form the second and third recesses K2 and K3. A plurality of second and third recesses K2 and K3 spaced apart along the second direction Y expose adjacent protruding structures, thereby forming an array of semiconductor pillars 20 distributed along the second direction Y between the second and third recesses K2 and K3, as shown in Figure 7.

[0073] The semiconductor pillars 20 are used to transfer or stop charge transfer under the influence of an applied electric field, turning the transistor on or off. Each semiconductor pillar 20 extends perpendicular to the substrate 1. The direction of extension of the semiconductor pillars 20 corresponds to the direction of current flow when the transistor is on. The semiconductor pillars 20 are arranged in an array along a first direction X and a second direction Y.

[0074] In some embodiments, as shown in FIG7 and FIG8 , the second groove K2 exposes the semiconductor pillars 20 in the same column among the semiconductor pillars 20 distributed in the array; the gate structures 10 of the semiconductor pillars 20 in the same column are interconnected, and the interconnected gate structures 10 serve as word lines for the semiconductor pillars 20 in the same column. The word lines can provide a word line voltage, and the word line voltage is used to control the conduction or cutoff of each transistor.

[0075] Step S500: forming a gate line structure in the second groove K2;

[0076] Step S600: forming a shielding structure 30 in the third groove K3.

[0077] In some embodiments, as shown in FIG7 and FIG8 , after forming the second groove K2 and the third groove K3, a sacrificial material may be deposited in the second groove K2, a mask may be used to remove a portion of the sacrificial material in the third groove K3, and then a metal material may be deposited to form the shielding structure 30, as shown in FIG9 . After depositing the sacrificial material in the third groove K3, a mask may be used to remove a portion of the sacrificial material in the second groove K2, and then a gate dielectric layer 510 may be formed along the inner wall of the second groove K2, and a metal material may be deposited on the sidewalls of the gate dielectric layer 510 to form the gate structure 10.

[0078] In some embodiments, the gate line structure can be formed in the second groove K2 first and then the shielding structure 30 can be formed in the third groove K3, or the shielding structure 30 can be formed in the third groove K3 first and then the gate line structure can be formed in the second groove K2, or the gate line structure can be formed in the second groove K2 and the shielding structure 30 can be formed in the third groove K3 simultaneously.

[0079] In some embodiments, the deposition method of the metal material may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0080] In some embodiments of the present application, the shielding structure 30 is formed simultaneously with the formation process of the gate structure 10, so that the shielding structure 30 can be formed without adding additional process steps. This can shield the interference of the gate structure 10 on the adjacent semiconductor pillars 20, thereby improving the coupling effect between the gate structure 10 and the adjacent semiconductor pillars 20.

[0081] In some embodiments, forming the semiconductor device 100 as shown in FIG. 12 through the above steps S100 to S600 includes:

[0082] a first region R1, the first region R1 including a semiconductor pillar array, the semiconductor pillar array including a plurality of semiconductor pillars 20 arranged in an array along a first direction X and a second direction Y and extending in a third direction Z; the first direction X, the second direction Y and the third direction Z intersect each other; and

[0083] A plurality of gate structures 10 and shielding structures 30 extending along a first direction X; the gate structures 10 and the shielding structures 30 are staggered along a second direction Y, and the semiconductor pillars 20 are located between adjacent shielding structures 30 and gate structures 10;

[0084] The size of the gate structure 10 along the first direction X is smaller than the size of the shielding structure 30 along the first direction X, and the orthographic projection of the gate structure 10 along the second direction Y is within the range of the orthographic projection of the shielding structure 30 .

[0085] Specifically, the shield structure 30 overlaps with the orthographic projection of the gate structure 10 in the first direction X, the extension of the shield structure 30 in the first direction X is greater than the extension of the gate structure 10 in the first direction X, and the orthographic projection of the end of the gate structure 10 in the first direction X in the second direction Y overlaps within the orthographic projection of the end of the shield structure 30 in the first direction X in the second direction Y. In one embodiment of the present application, the etching process parameters can be adjusted so that the second etching length (extension L2 in the first direction X) of the third groove K3 as shown in FIG7 is greater than the first etching length (extension L1 in the first direction X) of the second groove K2. In this way, as shown in FIG9, FIG12 and FIG14, the extension L2 of the shield structure 30 in the first direction X formed in the third groove K3 can be greater than the extension L1 of the gate structure 10 in the first direction X formed in the second groove K2, and the end of the gate structure 10 in the first direction X is located within the range of the end of the shield structure 30 in the first direction X.

[0086] In some embodiments, the size of the gate structure 10 along the third direction Z is larger than the size of the shielding structure 30 along the third direction Z, and the orthographic projection of the gate structure 10 along the second direction Y is within the range of the orthographic projection of the shielding structure 30 .

[0087] Specifically, the shield structure 30 overlaps with the orthographic projection of the gate structure 10 in the third direction Z, the extension dimension of the shield structure 30 in the third direction Z is smaller than the extension dimension of the gate structure 10 in the third direction Z, and the orthographic projection of the shield structure 30 in the second direction Y above the third direction Z overlaps within the orthographic projection of the end portion of the gate structure 10 in the third direction Z in the second direction Y. In one embodiment of the present application, the etching process parameters can be adjusted so that the first etching depth of the second groove K2 (the extension dimension H1 in the third direction Z) is greater than the second etching depth of the third groove K3 (the extension dimension H2 in the third direction Z). In this way, as shown in Figures 10, 11, and 13, the extension dimension h1 of the gate structure 10 formed in the second groove K2 in the third direction Z can be greater than the extension dimension h2 of the shield structure 30 formed in the third groove K3 in the third direction Z, and the end portion of the shield structure 30 in the third direction Z is located within the range of the end portion of the gate structure 10 in the third direction Z.

[0088] In some embodiments, the first surface of the shielding structure 30 away from the substrate 1 is not higher than the first surface of the gate structure 10 away from the substrate 1, and the second surface of the shielding structure 30 close to the substrate 1 is not lower than the second surface of the gate structure 10 close to the substrate 1.

[0089] For example, as shown in Figure 10, the top surface of the first surface of the shielding structure 30 along the third direction Z away from the substrate 1 (hereinafter referred to as the top surface for the convenience of description) is flush with the top surface of the gate structure 10 along the third direction Z, and the second surface of the shielding structure 30 along the third direction Z close to the substrate 1 (hereinafter referred to as the bottom surface for the convenience of description) is higher than the bottom surface of the gate structure 10 along the third direction Z.

[0090] For example, as shown in Figures 11, 13 and 15, the top surface of the shielding structure 30 along the third direction Z is lower than the top surface of the gate structure 10 along the third direction Z, and the bottom surface of the shielding structure 30 along the third direction Z is higher than the bottom surface of the gate structure 10 along the third direction Z.

[0091] In some embodiments of the present application, the gate structure 10 includes a first gate 111 and a second gate 112 adjacent to each other in the second direction Y. The first gate 111 and the second gate 112 are respectively located on one side of the semiconductor pillar 20 adjacent thereto.

[0092] In some embodiments, as shown in FIG13 , the gate structure 10 includes a first gate 111 and a second gate 112 extending along a first direction X. The first gate 111 and the second gate 112 in the same gate structure 10 are adjacent to each other in the second direction Y. Furthermore, the first gate 111 and the second gate 112 are each located on one side of the adjacent semiconductor pillar 20. For example, as shown in FIG13 , semiconductor pillar 20 a and semiconductor pillar 20 b are adjacent to each other in the second direction Y. A gate structure 10 is located between semiconductor pillars 20 a and 20 b. In the gate structure 10, the first gate 111 is located on a side closer to semiconductor pillar 20 a along the second direction Y, and the second gate 112 is located on a side closer to semiconductor pillar 20 b along the second direction Y.

[0093] In some embodiments of the present application, as shown in Figures 7, 8, 9 and 10, the exposed sidewalls of the semiconductor pillar 20 are oxidized through the second groove K2 to form a gate dielectric layer 510 on the sidewalls of the semiconductor pillar 20. The process of oxidizing the sidewalls of the semiconductor pillar 20 exposed in the second groove K2 includes but is not limited to: direct oxidation, alkaline oxidation or acidic oxidation. In some embodiments of the present application, direct oxidation is performed by heating, so that the silicon on the sidewalls of the semiconductor pillar 20 reacts chemically with a gas containing an oxidizing substance at a high temperature, thereby producing a dense silicon dioxide film on the silicon surface, forming a gate dielectric layer 510 located on the sidewalls of the semiconductor pillar 20. The gate dielectric layer 510 includes an insulating material, such as silicon oxide or silicon oxynitride. Among them, the gate dielectric layer 510 is located between the semiconductor pillar 20 and the first gate 111 or the second gate 112 of the gate structure 10 formed in Figures 9, 10, 11 and 22. The gate dielectric layer 510 is used to isolate the gate structure 10 from the semiconductor pillar 20 to prevent direct contact between the gate structure 10 and the semiconductor pillar 20 to cause charge leakage.

[0094] As shown in FIG9 , FIG10 and FIG11 , the detailed description of forming the gate structure 10 and the shielding structure 30 in the second groove K2 and the third groove K3 respectively refers to the above corresponding embodiments S500 to S600 , which will not be repeated here.

[0095] In some embodiments, as shown in Figures 7, 12, 14, and 19, an extension dimension l2 of the shield structure 30 along the first direction X is greater than an extension dimension l1 of the gate structure 10 along the first direction X, i.e., l2>l1. As shown in Figures 10, 11, 12, 13, 15, and 22, an extension dimension h1 of the shield structure 30 along the extension direction of the semiconductor pillar 20 (i.e., the third direction Z) is less than an extension dimension h2 of the gate structure 10 along the extension direction of the semiconductor pillar 20 (i.e., the third direction Z), i.e., h1<h2. The extension dimensions along the first direction X and the extension dimensions along the third direction Z can be controlled by adjusting the etching length and etching depth of the third groove K3 and the second groove K2 as shown in Figures 7 and 8. The etching process parameters include, but are not limited to, etching time, etching gas flow rate, ratio, pressure, temperature, etc.

[0096] In some embodiments, the semiconductor device 100 further includes a second region R2, which is arranged along the first direction X with the first region R1; the second region R2 includes a first conductive portion 210, and the first conductive portion 210 includes a first lead-out structure 40 extending along the third direction Z and a first connecting member 60 extending along the first direction X; the two ends of the first lead-out structure 40 along the third direction Z are respectively in contact with the first connecting member 60 and the gate structure 10; the first conductive portion 210 is located on one side of the shielding structure 30 along the third direction Z.

[0097] Specifically, the second region R2 may include a transition region for connecting to the first region R1, but is not limited thereto. As shown in Figures 14 and 19, the first region R1 and the second region R2 are arranged in the first direction X. The second region R2 includes a first conductive portion 210, and the gate structure 10 in the first region R1 can be connected to the first conductive portion 210 in the second region R2. Referring to Figures 15, 16 and 22, the first conductive portion 210 includes a first lead-out structure 40 and a first connector 60. As shown in Figures 15 and 16, the first connector 60 extends along the first direction X, and as shown in Figure 22, the first lead-out structure 40 extends along the third direction Z. As shown in Figures 15 and 16, the two ends of the first lead-out structure 40 along the third direction Z are respectively in contact with the first connector 60 and the gate structure 10. The first conductive portion 210 can be located on either side of the shielding structure 30 along the third direction Z.

[0098] In some examples, the first conductive portion 210 can be located on a first side of the shielding structure 30 along the third direction Z. As shown in FIG15 , the bottom surface of the gate structure 10 along the third direction Z is connected to the top surface of the first lead-out structure 40 along the third direction Z, and the bottom surface of the first lead-out structure 40 along the third direction Z is connected to the top surface of the first connector 60 along the third direction Z. The bottom surface of the first connector 60 along the third direction Z can be connected to a peripheral circuit. In this way, the first conductive portion 210 can be led out from the front surface of the substrate 1.

[0099] In some examples, the first conductive portion 210 can be located on the second side of the shielding structure 30 along the third direction Z. As shown in FIG16 , the top surface of the gate structure 10 along the third direction Z is connected to the bottom surface of the first lead-out structure 40 along the third direction Z, and the top surface of the first lead-out structure 40 along the third direction Z is connected to the bottom surface of the first connector 60 along the third direction Z. The top surface of the first connector 60 along the third direction Z can be connected to a peripheral circuit. In this way, the first conductive portion 210 can be led out from the back surface of the substrate 1.

[0100] In some embodiments, the semiconductor device 100 includes multiple first regions R1 and multiple second regions R2 , two adjacent first regions R1 along the first direction X are connected through a second region R2 , and the gate structures 10 in two adjacent first regions R1 are connected through the first conductive portion 210 .

[0101] Specifically, Figures 14 and 19 only exemplarily illustrate two alternately connected first regions R1 and one second region R2, where the first region R1a is connected to the first region R1b via the second region R2. In other embodiments, the semiconductor device 100 may also include three alternately connected first regions R1 and two first regions R1. Of course, semiconductor devices 100 including other numbers and arrangements of first regions R1 and second regions R2 are all within the scope of protection of this application and are not limited here.

[0102] For the convenience of description, the present application takes two first regions R1 and one second region R2 alternately arranged in the first direction X as an example. As shown in Figures 14 and 19, the two first regions R1 and the second region R2 are alternately arranged in the first direction X, and the second region R2 is located between the two adjacent first regions R1. The second region R2 includes a first conductive portion 210. The gate structures 10 in the two adjacent first regions R1 are connected through the first lead-out structure 40 of the first conductive portion 210, and then the first lead-out structure 40 is connected to the first connecting member 60 of the first conductive portion 210, so that the multiple gate structures 10 in the two adjacent first regions R1 are connected through the first conductive portion 210 in the second region R2.

[0103] In some embodiments, the materials of the first connector 60 and the first lead-out structure 40 of the first conductive portion 210 may include conductive materials, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.

[0104] In some embodiments, the second region R2 further includes a second conductive portion 220 extending along the second direction Y, and the plurality of shielding structures 30 in the first region R1 are connected via the second conductive portion 220 .

[0105] Specifically, the present application takes two first regions R1 and one second region R2 alternately arranged in the first direction X as an example. As shown in Figures 14 and 19, the two first regions R1 and the second region R2 are alternately arranged in the first direction X, and the second region R2 is located between the two adjacent first regions R1. The second region R2 includes a second conductive portion 220, and the shielding structures 30 in the two adjacent first regions R1 are connected through the second conductive portion 220, so that multiple shielding structures 30 in the two adjacent first regions R1 are connected through the second conductive portion 220 in the second region R2.

[0106] As shown in Figures 14 and 17 to 21, the second region R2 further includes a second conductive portion 220, and the plurality of shielding structures 30 in the first region R1 are connected via the second conductive portion 220, that is, one end of the plurality of shielding structures 30 is connected to the second conductive portion 220. The second conductive portion 220 can be located on any side of the shielding structure 30 along the third direction Z.

[0107] In some embodiments, the first region R1 further includes:

[0108] a bit line 120 located at one side of the semiconductor pillar 20 along the third direction Z and connected to the drain of the semiconductor pillar 20 , the bit line 120 extending along the second direction Y;

[0109] Along the third direction Z, the second conductive portion 220 is located on a side of the shielding structure 30 relatively close to the bit line 120 .

[0110] Specifically, as shown in Figures 13, 14, 19, and 22, the first region also includes a bit line 120, and the semiconductor pillar 20 includes a source 145 and a drain 141 located on opposite sides along the third direction Z. The source 145 and drain 141 of the transistor are located on opposite sides of the semiconductor pillar 20 along the third direction Z. It should be understood that the source 145 and drain 141 of the transistor are relative terms, and the source 145 and drain 141 can be either end of the semiconductor pillar 20 along the third direction Z. The bit line 120 extending along the first direction X is located on one side of the semiconductor pillar 20 along the third direction Z. The bit line 120 is connected to the drain 141 of the semiconductor pillar 20. The second conductive portion 220 is located on a side of the shielding structure 30 that is relatively close to the bit line 120 along the third direction Z.

[0111] In some embodiments, the bit line 120 located at one side of the semiconductor pillar 20 along the third direction Z and connected to the drain of the semiconductor pillar 20 extends along the second direction Y;

[0112] Along the third direction Z, the second conductive portion 220 is located on a side of the shielding structure 30 relatively far away from the bit line 120 .

[0113] As shown in Figures 13, 14, 19, and 22, the first region also includes a bit line 120, and the semiconductor pillar 20 includes a source 145 and a drain 141 located on opposite sides along the third direction Z. The source 145 and drain 141 of the transistor are located on opposite sides of the semiconductor pillar 20 along the third direction Z. It should be understood that the source 145 and drain 141 of the transistor are relative terms, and the source 145 and drain 141 can be either end of the semiconductor pillar 20 along the third direction Z. The bit line 120 extending along the first direction X is located on one side of the semiconductor pillar 20 along the third direction Z. The bit line 120 is connected to the drain 141 of the semiconductor pillar 20. The second conductive portion 220 is located on a side of the shielding structure 30 relatively far from the bit line 120 along the third direction Z. The following description will focus on the specific components of the second conductive portion 220.

[0114] In some embodiments, the second conductive portion 220 includes a second connecting member 80 extending along the second direction Y, the second connecting member 80 is connected to the plurality of shielding structures 30, and a side of the gate structure 10 close to the second connecting member 80 has a distance L3 from the second connecting member 80 in the first direction X.

[0115] Specifically, as shown in Figures 14, 17, 18, and 19, the second conductive portion 220 includes a second connector 80 extending along the second direction Y. The plurality of shielding structures 30 are connected to the second connector 80. A side of the gate structure 10 near the second connector 80 is spaced apart from the second connector 80 in the first direction X by a spacing L3. The value of spacing L3 can be set arbitrarily. As shown in Figures 14 and 19, a side of the gate structure 10 near the second connector 80, i.e., a side near the first lead-out structure 40 of the first conductive portion 210 in the figures, is spaced apart from the second connector 80 extending along the second direction Y by a spacing L3 in the first direction X. This facilitates the extraction of the gate structure 10.

[0116] In some embodiments, the second conductive portion 220 may include a second connector 80 located on a first side of the shielding structure 30 along the third direction Z. Furthermore, the second conductive portion 220 may further include a second connector 80 located on a second side of the shielding structure 30 along the third direction Z. The second conductive portion 220 may further include a second connector 80 located on a first side of the shielding structure 30 along the third direction Z, and another second connector 80 located on a second side of the shielding structure 30 along the third direction Z. The material of the second connector 80 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

[0117] In some embodiments, the second conductive portion 220 further includes: at least one second lead-out structure 70 extending along the third direction Z, the second lead-out structure 70 is connected to the second connecting member 80, and the second lead-out structure 70 is located at one end of the second connecting member 80 in the second direction Y away from the plurality of shielding structures 30.

[0118] Specifically, as shown in Figures 14, 17, 18, and 19, the second conductive portion 220 further includes at least one second lead-out structure 70 extending along the third direction Z. As shown in Figures 17 and 18, the second lead-out structure 70 is connected to the second connector 80, and the second lead-out structure 70 is located at an end of the second connector 80 that is away from the plurality of shielding structures 30 in the second direction Y. In other words, the end of the second connector 80 in the second direction Y is spaced a certain distance from the outermost shielding structures 30 spaced apart in the second direction Y. For example, as shown in Figure 17, the second lead-out structure 70 is located at an end of the second connector 80 in the second direction Y that is away from the outermost shielding structure 30a among the plurality of shielding structures 30, or the second lead-out structure 70 is located at an end of the second connector 80 in the second direction Y that is away from the outermost shielding structure 30b among the plurality of shielding structures 30. In this way, a second lead-out structure 70 is moved away from the outermost shielding structure 30a (or 30b) along the second direction Y, so that there is a gap between the second lead-out structure 70 and the outermost shielding structure 30a (or 30b), which is beneficial for reducing the crosstalk / coupling effect (Coupling Effect) between the shielding structure 30 including conductive material and the second lead-out structure 70, thereby improving device performance.

[0119] The material of the second lead-out structure 70 includes a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The second lead-out structure 70 is connected to the second connector 80, and the second lead-out structure 70 is located at one end away from the plurality of shielding structures 30 arranged side by side in the second direction Y. For example, as shown in Figures 14, 17, 18, and 19, one second lead-out structure 70a is connected to a first end of the second connector 80 away from an outermost shielding structure 30a in the second direction Y, and another second lead-out structure 70b is connected to a second end of the second connector 80 away from an outermost shielding structure 30b in the second direction Y. The first end of the second connector 80 and the second end of the second connector 80 can be the ends of the second connector 80 along the second direction Y, respectively.

[0120] In some embodiments, along the third direction Z, the shielding structure 30 and the second lead-out structure 70 are located on opposite sides of the second connecting member 80 .

[0121] 17 and 20 , the shielding structure 30 and the second lead structure 70 are located on opposite sides of the second connector 80 along the third direction Z. Disposing the shielding structure 30 and the second lead structure 70 of the second conductive portion 220 on opposite sides of the second connector 80 along the third direction Z can reduce device area, thereby reducing the size of the semiconductor device 100.

[0122] In some examples, as shown in FIG. 17 , the second lead-out structure 70 may be located on a side of the shielding structure 30 away from the bit line 120 along the third direction Z, so that the second conductive portion 220 may be led out from the front surface of the substrate 1 .

[0123] In some examples, as shown in FIG18 , the second lead-out structure 70 may also be located on a side of the shielding structure 30 away from the bit line 120 along the third direction Z. In this way, the second conductive portion 220 may be led out from the back surface of the substrate 1 .

[0124] In some embodiments, the shielding structure 30 is in contact with and connected to the second connector 80. Specifically, as shown in Figures 17 and 18, each shielding structure 30 is in direct contact with and connected to the second connector 80.

[0125] In some embodiments, the second conductive portion 220 further includes: at least one third lead-out structure 71 extending along the third direction Z, each of the shielding structures 30 is connected to the second connecting member 80 through one of the third lead-out structures 71, and the third lead-out structure 71 and the second lead-out structure 70 are located on different sides of the second connecting member 80 along the third direction Z.

[0126] Specifically, as shown in Figures 14, 19, 20, and 21, the second conductive portion 220 further includes at least one third lead-out structure 71 extending along the third direction Z. The number of third lead-out structures 71 can be the same as or different from the number of shielding structures 30. The plurality of shielding structures 30 arranged in parallel and spaced relation along the second direction Y are each connected to a second connector 80 extending along the second direction Y via a third lead-out structure 71. That is, in the third direction Z, the third lead-out structure 71 is located between the second connector 80 and the shielding structure 30. That is, both ends of the third lead-out structure 71 along the third direction Z are in contact and connected to the second connector 80 and the shielding structure 30, respectively. This allows each shielding structure 30 to be indirectly connected to the second connector 80. It should be noted that the third lead-out structure 71 and the second lead-out structure 70 are located on different sides of the second connector 80 along the third direction Z. That is, in the third direction Z, the second connector 80 is located between the third lead-out structure 71 and the second lead-out structure 70.

[0127] The material of the third lead-out structure 71 includes a conductive material, and the conductive material includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.

[0128] In some embodiments, the second conductive portion 220 further includes a third connecting member 50 extending along the first direction X, and the third connecting member 50 is connected to the second connecting member 80 through the second lead-out structure 70 .

[0129] Specifically, as shown in Figures 14, 17, 18, 19, 20, and 21, the second conductive portion 220 further includes a third connector 50 extending along the first direction X. The third connector 50 is connected to the second connector 80 via a second lead-out structure 70. That is, the second lead-out structure 70 is located on different sides of the second connector 80 and the third connector 50 in the third direction Z. That is, the second lead-out structure 70 is located between the third connector 50 and the second connector 80 in the third direction Z.

[0130] The material of the third connecting member 50 includes a conductive material, and the conductive material includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.

[0131] In some embodiments, the second lead-out structure 70 and the third lead-out structure 71 may be made of the same material, and their shapes may be a regular trapezoid, a rectangle, or any other shape along the third direction Z. For example, the dimension of the top surface of the third lead-out structure 71 along the first direction X is smaller than the dimension of the bottom surface of the third lead-out structure 71 along the first direction X, and the dimension of the top surface of the second lead-out structure 70 along the first direction X is smaller than the dimension of the bottom surface of the second lead-out structure 70 along the first direction X.

[0132] In some embodiments, along the third direction Z, the shielding structure 30 is located on a side of the second connecting member 80 relatively far away from the bit line 120 .

[0133] Specifically, as shown in Figures 17, 18, 20, and 21, the third connector 50, the second lead structure 70, the second connector 80, and the third lead structure 71 are connected to the shield structure 30 as a whole as a second conductive portion 220 along the third direction Z. If the shield structure 30 is located on a side of the second connector 80 that is relatively far from the bit line 120 in the third direction Z, then this is equivalent to the second conductive portion 220-230 being located on a side of the shield structure 30 that is relatively close to the bit line 120 along the third direction Z. In other words, the shield structure 30 is located above the second connector 80 along the third direction Z, which also means that the shield structure 30 is relatively far from the bit line 120 along the third direction Z, and the second connector 80 is relatively close to the bit line 120 along the third direction Z compared to the shield structure 30.

[0134] In some embodiments, along the third direction Z, the shielding structure 30 is located on a side of the second connecting member 80 relatively close to the bit line 120 .

[0135] Specifically, continuing with the above description, since the third connector 50, the second lead structure 70, the second connector 80, and the third lead structure 71 are connected to the shielding structure 30 as a whole as a second conductive portion 220 along the third direction Z, if the shielding structure 30 is located on the side of the second connector 80 that is relatively close to the bit line 120 along the third direction Z, then this is equivalent to the second conductive portions 220-230 being located on the side of the shielding structure 30 that is relatively far away from the bit line 120 along the third direction Z. In other words, the shielding structure 30 is located below the second connector 80 along the third direction Z, which also means that the shielding structure 30 is relatively close to the bit line 120 along the third direction Z, and the second connector 80 is relatively far away from the bit line 120 along the third direction Z compared to the shielding structure 30.

[0136] In specific applications, according to different needs, the first conductive portion 210 and the second conductive portion 220 can be disposed on the same side or different sides of the shielding structure 30 along the third direction Z.

[0137] The gate structure 10 is led out through the first conductive portion 210, and the shield structure 30 is led out through the second conductive portion 220. As shown in FIG22, the bit line 120 is connected to the drain of the semiconductor pillar 20. As shown in FIG12, FIG14, and FIG19, the lead pads 130 of the bit line 120 are staggered along the second direction Y. When the distance between the gate structure 10 and the shield structure 30 is small, the second conductive portion 220 leading out of the shield structure 30 and the first conductive portion 210 leading out of the gate structure 10 need to be staggered (arranged on different sides along the third direction Z). This can prevent short circuits between the gate structure 10 and the shield structure 30, while reducing device size and improving space utilization.

[0138] Of course, in other embodiments, when the distance between the gate structure 10 and the shielding structure 30 allows, the second conductive portion 220 extending from the shielding structure 30 and the first conductive portion 210 extending from the gate structure 10 can be arranged on the same side along the third direction Z to facilitate actual control.

[0139] The shielding structure 30 , the gate structure 10 , the semiconductor pillar 20 , the first conductive portion 210 , and the second conductive portion 220 in the above embodiments may be integrated into a first semiconductor structure 601 as shown in FIG. 22 .

[0140] In some embodiments, the first region further includes:

[0141] a capacitor structure located on a side of the semiconductor pillar 20 relatively away from the bit line 120 along the third direction Z and extending along the third direction Z;

[0142] The capacitor structure includes a first end connected to the source of the semiconductor pillar 20 and a second end connected to the common end.

[0143] The bit line 120 is connected to the drain of the semiconductor pillar 20, one electrode of the capacitor structure 90 is connected to the source of the semiconductor pillar 20, and the other electrode of the capacitor structure 90 is connected to a common terminal (not shown). Specifically, the capacitor structure 90 is used to store data written to the semiconductor device 100. In some embodiments, the common terminal may include a low voltage terminal or a ground terminal, wherein the low voltage may include -0.5V, -1V, etc.

[0144] In some embodiments, the shielding structure 30 is connected to a common terminal. In practical applications, the shielding structure 30 can be configured to be powered independently and not connected to the common terminal as required. In some embodiments of the present application, a low voltage is applied to the shielding structure 30 or the shielding structure 30 is grounded so that the shielding structure 30 can shield the word line from interfering with the adjacent semiconductor pillars 20.

[0145] Specifically, the semiconductor pillar 20 includes a source 145 and a drain 141 located on opposite sides along the third direction Z. The source 145 and drain 141 of the transistor are located on opposite sides of the semiconductor pillar 20 along the third direction Z. It is understood that the source 145 and drain 141 of the transistor are relative concepts, and the source 145 and drain 141 can be any surface of the semiconductor pillar 20 along the third direction Z. A capacitor structure 90 extending along the third direction Z is located on a first side of the semiconductor pillar 20 along the third direction Z, and a bit line 120 extending along the first direction X is located on a second side of the semiconductor pillar 20 along the third direction Z. The bit line 120 is connected to the drain 141 of the semiconductor pillar 20. The capacitor structure 90 includes a first end connected to the source of the semiconductor pillar 20 and a second end connected to a common end.

[0146] In addition, the capacitor array 604 composed of the above-mentioned capacitor structure 90 can be integrated with the transistor array (including the shielding structure 30, the gate structure 10, the semiconductor pillar 20, the first conductive portion 210 and the second conductive portion 220 in the above embodiment) and other device structures in the substrate 1 of the above-mentioned first semiconductor structure 601. In some applications of the present application, referring to Figure 22, the above-mentioned capacitor structure 90 and the transistor array are integrated in the same semiconductor substrate 1, that is, the substrate 1 of the first semiconductor structure 601 shown in Figure 22, and the driving circuit of the memory device can be integrated in another semiconductor substrate 1, that is, the substrate 1 of the second semiconductor structure 602 shown in Figure 22. In this way, in the substrate 1 integrated with the memory device, there will be some blank areas that are not devices. These blank areas can be used to form the above-mentioned capacitor array 604, without adding additional areas to form capacitors, thereby further improving the integration of the semiconductor device 100.

[0147] As shown in Figure 22, in the first semiconductor structure 601, the capacitor array 604 and the transistor array are stacked in the Z direction, and one electrode in the capacitor structure 90 in the capacitor array 604 is coupled to the drain 141 of the transistor in the transistor array. A capacitor structure 90 and a transistor (including a semiconductor column 20, a gate structure 10, and the drain 141 and the source 145 on opposite sides of the semiconductor column 20 along the third direction Z) constitute a DRAM memory cell. By turning on and off the transistor, the connected capacitor structure 90 is selected and unselected, and the selected memory cell can be read, written, or erased. The embodiment of the present application does not limit the number of capacitor structures 90 and transistors. The capacitor array 604 can be coupled to the transistor array to form a DRAM memory array.

[0148] It is understood that the source 145 and drain 141 of a transistor are relative concepts that are related to the way the transistor is actually connected to the circuit, and have nothing to do with the physical location of the source 145 and drain 141 in the transistor. In some examples, after the transistor is connected to the circuit, the input end of the transistor connected to the circuit can be used as the source 145, and the output end can be used as the drain 141, and carriers flow from the source 145 to the drain 141. To better explain the coupling relationship between the capacitor structure 90 and the transistor in the embodiment of the present application, the end of the transistor coupled to the capacitor structure 90 is used as the drain 141, and the source 145 of the transistor can be coupled to the bit line 120 to which the operating voltage is applied.

[0149] 22 , the first semiconductor structure 601 further includes a first conductive plug 114a coupled to the bit line 120. An insulating first filling layer 142a is disposed between adjacent transistors to support the transistors and provide electrical isolation.

[0150] In some embodiments, as shown in FIG. 22 , an insulating second filling layer 142 b is disposed between the gate structure 10 and the gate dielectric layer.

[0151] In some examples, the constituent materials of the first filling layer 142 a and the second filling layer may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane, or polysilazane.

[0152] In some embodiments, as shown in FIG22 , the second semiconductor structure 602 includes various devices including a CMOS structure. In the Z direction, the first semiconductor structure 601 and the second semiconductor structure 602 are stacked and interconnected by electrical signals through bonding technology. The bonding may include hybrid bonding.

[0153] As shown in FIG22 , before bonding is completed, the planes to be bonded of the first semiconductor structure 601 and the second semiconductor structure 602 are each provided with bonding contacts 132. The bonding contacts 132 lead the electrical signals of the semiconductor structures to the bonding planes. The bonding contacts 132 may include conductive structures such as pads, conductive wires, and conductive plugs. The pads shown in FIG22 are only examples. The planes to be bonded of the first semiconductor structure 601 and the second semiconductor structure 602 are bonded, and the interface where the planes to be bonded of the two semiconductor structures contact is the bonding interface 131. The bonding contacts 132 of the first semiconductor structure 601 and the second semiconductor structure 602 are in contact at the bonding interface 131, thereby realizing electrical signal interconnection between the first semiconductor structure 601 and the second semiconductor structure 602.

[0154] The bonding contact 132 may be made of a conductive material such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. The bonding interface 131 may be made of silicon oxide, silicon nitride, or a metal silicide. In the disclosed embodiment, the bonding interface 131 includes a metal silicide, which can increase the adhesion to the bonding contact 132, reduce stress at the bonding interface 131, minimize bending deformation at the bonding interface 131, and improve manufacturing yield.

[0155] A first conductive plug 114a can be provided to lead the electrical signals of the transistors and couple them to pads on the surface to be bonded of the first semiconductor structure 601. A second conductive plug 114b can be provided to lead the electrical signals of the first CMOS structure 121 and the second CMOS structure 122 in the second semiconductor structure 602, respectively, and couple them to pads on the surface to be bonded of the second semiconductor structure 602. In the z-direction, the pads of the first semiconductor structure 601 and the pads on the second semiconductor structure 602 serve as bonding contacts 132, interconnecting the electrical signals of the two semiconductor structures after bonding is completed.

[0156] In some embodiments, as shown in FIG. 22 , the first semiconductor structure 601 further includes:

[0157] The interconnect layer 118 is located at an end of the capacitor structure 90 away from the transistor along the third direction Z; the interconnect layer 118 is coupled to the capacitor structure 90. The interconnect layer 118 may be composed of a conductive material such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. Electrical signals from the interconnect layer 118 can be routed to the bonding interface 131 via the third conductive plug 114c, thereby achieving electrical signal interconnection with the second semiconductor structure 602.

[0158] 22 , an interconnect structure 133 is further provided on a side of the first semiconductor structure 601 away from the bonding interface 131. The interconnect structure 133 can be coupled to the interconnect layer 118 to supply power to the interconnect layer 118. In other embodiments, the interconnect structure 133 can also be coupled to other interconnect layers for power supply.

[0159] Some embodiments of the present application provide a semiconductor device 100 and a method for manufacturing the same. The transistor array formed by this method has a source 145 and a drain 141 located at either end of a semiconductor pillar 20 extending in a direction perpendicular to the substrate 1. Furthermore, the gate structure 10 is located on a sidewall of the semiconductor pillar 20. This significantly reduces the area of ​​the transistor array and improves the device's storage density. Furthermore, a shielding structure 30 is formed between adjacent semiconductor pillars 20 to shield word lines from interference with adjacent semiconductor pillars 20.

[0160] Based on the above-mentioned semiconductor device 100 and its manufacturing method, as shown in Figure 24, an embodiment of the present invention also provides a storage system 300, including a memory controller 310 and a three-dimensional memory 320. The memory controller 310 is coupled to the three-dimensional memory 320 and is used to control the three-dimensional memory 320 to store data. The three-dimensional memory 320 includes any one of the above-mentioned semiconductor devices 100.

[0161] Specifically, as shown in FIG24 , a storage system 300 includes a memory controller 310 and one or more three-dimensional memories 320. The three-dimensional memories 320 (3D NAND Flash) include an array storage structure 321 and a peripheral circuit 322. The array storage structure 321 includes any of the aforementioned semiconductor devices 100. The storage system 300 can communicate with a host 400 via the memory controller 310. The memory controller 310 can connect to the one or more three-dimensional memories 320 via channels within the one or more three-dimensional memories 320. Each three-dimensional memory 320 can be managed by the memory controller 310 via the channels within the three-dimensional memories 320.

[0162] Specifically, the array storage structure 321 is used to store information, and the peripheral circuit 322 can be located above or below the array storage structure 321, or can be located around the array storage structure 321. The peripheral circuit 322 is used to control the corresponding array storage structure 321. In addition, the semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation. In addition, the semiconductor device 100 of the embodiment of the present invention can be a three-dimensional memory 320, or can be part of a peripheral memory, without special limitation.

[0163] The above is a detailed introduction to a semiconductor device 100, a manufacturing method thereof, and a storage system 300 provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor device, wherein: include: a first region, the first region comprising a semiconductor column array, the semiconductor column array comprising a plurality of semiconductor columns arranged in an array along a first direction and a second direction and extending in a third direction; the first direction, the second direction and the third direction intersect each other; as well as, A plurality of gate structures and shielding structures extending along a first direction; the gate structures and the shielding structures are staggered along a second direction, and the semiconductor pillars are located between adjacent shielding structures and gate structures; The size of the gate structure along the first direction is smaller than the size of the shielding structure along the first direction, and the orthographic projection of the gate structure along the second direction is within the range of the orthographic projection of the shielding structure.

2. The semiconductor device according to claim 1, wherein A dimension of the gate structure along the third direction is greater than a dimension of the shielding structure along the third direction, and an orthographic projection of the gate structure along the second direction is within a range of an orthographic projection of the shielding structure.

3. The semiconductor device according to claim 1, wherein Also includes a second area, wherein the second area and the first area are arranged along the first direction; The second region includes a first conductive portion, the first conductive portion includes a first lead-out structure extending along the third direction and a first connecting member extending along the first direction; Two ends of the first lead-out structure along the third direction are respectively in contact and connected with the first connecting member and the gate structure; The first conductive portion is located at one side of the shielding structure along the third direction.

4. The semiconductor device according to claim 3, wherein: It comprises a plurality of first regions and a plurality of second regions, two adjacent first regions along the first direction are connected via a second region, and the gate structures in two adjacent first regions are connected via the first conductive portion.

5. The semiconductor device according to claim 4, wherein: The second region further includes a second conductive portion, and the plurality of shielding structures in the first region are connected via the second conductive portion.

6. The semiconductor device according to claim 5, wherein: The first area also includes: a bit line located at one side of the semiconductor column along the third direction and connected to the drain of the semiconductor column, the bit line extending along the second direction; The second conductive portion is located at a side of the shielding structure relatively close to the bit line along the third direction.

7. The semiconductor device according to claim 5, wherein: The first area also includes: a bit line located at one side of the semiconductor column along the third direction and connected to the drain of the semiconductor column, the bit line extending along the second direction; The second conductive portion is located at a side of the shielding structure relatively far away from the bit line along the third direction.

8. The semiconductor device according to claim 6 or 7, wherein: The second conductive portion includes a second connecting member extending along the second direction, the second connecting member is connected to the plurality of shielding structures, and a side of the gate structure close to the second connecting member is spaced apart from the second connecting member in the first direction.

9. The semiconductor device according to claim 8, wherein: The second conductive portion further includes: at least one second lead-out structure extending along the third direction, the second lead-out structure being connected to the second connecting member, and the second lead-out structure being located at an end of the second connecting member away from the plurality of shielding structures in the second direction.

10. The semiconductor device according to claim 9, wherein: The shielding structure and the second lead-out structure are located at two opposite sides of the second connecting member along the third direction.

11. The semiconductor device according to claim 10, wherein: The shielding structure is in contact with and connected to the second connecting member.

12. The semiconductor device according to claim 10, wherein: The second conductive portion also includes: at least one third lead-out structure extending along the third direction, each of the shielding structures is connected to the second connecting member via at least one third lead-out structure, and the third lead-out structure and the second lead-out structure are located on different sides of the second connecting member along the third direction.

13. The semiconductor device according to claim 10, wherein: The second conductive portion further includes: a third connecting member extending along the first direction, and the third connecting member is connected to the second connecting member through the second lead-out structure.

14. The semiconductor device according to claim 11, wherein The shielding structure is located at a side of the second connecting member relatively far away from the bit line along the third direction.

15. The semiconductor device according to claim 11, wherein The shielding structure is located at a side of the second connecting member relatively close to the bit line along the third direction.

16. The semiconductor device according to claim 6 or 7, wherein: The first area also includes: a capacitor structure located at a side of the semiconductor column relatively far from the bit line along the third direction and extending along the third direction; The capacitor structure includes a first end connected to the source of the semiconductor column and a second end connected to the common end.

17. The semiconductor device according to claim 1, wherein The gate structure includes a first gate and a second gate adjacent to each other in the second direction, and the first gate and the second gate are respectively located on one side of the semiconductor column adjacent thereto.

18. A method for manufacturing a semiconductor device, wherein: include: providing a substrate; forming first grooves extending along the second direction and arranged at intervals along the first direction in the substrate; The first direction intersects the second direction; depositing a dielectric material in the first groove; A second groove and a third groove extending along the first direction are formed in the substrate, the second groove and the third groove are arranged alternately along the second direction, the size of the second groove along the first direction is smaller than the size of the third groove along the first direction, and the orthographic projection of the second groove along the second direction is located within the range of the orthographic projection of the third groove; forming a gate line structure in the second groove; A shielding structure is formed in the third groove.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: Also includes: The dimension of the second groove along the third direction is greater than the dimension of the third groove along the third direction, and the orthographic projection of the second groove along the second direction is within the range of the orthographic projection of the third groove, and the first direction, the second direction and the third direction intersect with each other.

20. A storage system, wherein: include: A memory controller and a three-dimensional memory, wherein the memory controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes one or more semiconductor devices according to any one of claims 1 to 17.

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