A method for manufacturing a standard wafer with sparse scattering defects

Abstract

A method for manufacturing a standard wafer with sparse scattering defects includes the following steps: Step 1, determining preset defect parameters; Step 2, generating a defect pattern consisting of protrusions or pits randomly arranged in the defect region according to the preset defect parameters, designing the defect pattern as a standard template structure layout, and fabricating a target mask according to the standard template structure layout; obtaining the target wafer through a thermal oxidation process; Step 3, transferring the pattern on the target mask onto the target wafer using a photolithography process; etching the target wafer to obtain the standard wafer. This invention provides a method for manufacturing a standard wafer with sparse scattering defects. The prepared standard wafer has a controllable number and diameter of defects, and the wafer can be cleaned, resulting in a longer lifespan. The distribution area, size, and number of defects are all controllably generated, meeting the needs of different types of inspection equipment.

Description

Technical Field

[0001] This invention relates to the field of measurement technology, and more specifically, to a method for manufacturing a standard wafer with sparse scattering defects. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, the size of nanostructures on chips is gradually shrinking, and the integration density is increasing exponentially. During chip manufacturing, particle contamination on the surface of semiconductor wafers can cause defects, affecting subsequent processes, resulting in defects such as short lines or bridging, causing device failure, and reducing the yield of integrated circuit manufacturing.

[0003] The ever-shrinking device size places increasingly higher demands on the precision of defect detection. Nanoscale defects or particles on the wafer surface require more sensitive and accurate defect detection technologies to ensure the yield rate of integrated circuit manufacturing.

[0004] Integrated circuit manufacturing begins with blank wafers, and the detection of the size and number of particulate defects on these wafers is mostly based on surface scanning technology. Measuring the increase in particle number before and after inspection can characterize contamination sources present during manufacturing and can also be used to monitor the effectiveness of wafer surface cleaning. Semiconductor wafer surface particle size inspection equipment uses optical methods. When optical imaging technology detects defects at the hundred-nanometer scale, the image is affected by light diffraction, and due to the optical diffraction limit, it is impossible to obtain images of defects with clearly cleaned boundaries. Light scattering detection technology is based on the relationship between scattered light intensity and defect diameter. By measuring the intensity of the scattered light, the size of the particulate defects causing the scattering can be inferred. This technology requires calibration wafers with particles of standard diameter as a standard to calibrate the equipment and ensure accurate detection results.

[0005] To calibrate the relationship between the scattering signal detected by the equipment and the particle diameter, particles of different diameters are needed. Currently, internationally, it is common practice to deposit dispersed particles of different diameters, such as polystyrene and silica particles, on the wafer surface as standard wafers for such equipment. For example, VLSI's contaminant standard wafers are widely used in industry. However, particles are prone to aggregation during the deposition stage, and they are easily detached due to external environmental influences or cannot be cleaned after being exposed to other contaminants, resulting in a short lifespan. Furthermore, existing particulate-deposited standard wafers can only simulate protruding defects and cannot solve the dimensional calibration problem in pit defect detection.

[0006] Therefore, the existing technology has problems and needs further improvement and development. Summary of the Invention

[0007] (I) Purpose of the invention: In order to solve the problems existing in the prior art, the purpose of the present invention is to provide a method for manufacturing a standard wafer with sparse scattering defects. The standard wafer manufactured by the method has the characteristics of long service life and cleanability, and the spatially randomly distributed defects eliminate the interference effect between the scattered light of the particles.

[0008] (II) Technical Solution: In order to solve the above-mentioned technical problems, this technical solution provides a method for manufacturing a standard wafer with sparse scattering defects, including the following steps;

[0009] Step 1: Preset defect pattern parameters, which include region parameters and defect parameters. The region parameters include the number of defect regions and the distribution location of each defect region. The defect parameters include the size of each defect in the defect region and the number of defect particles in each defect region. That is, the defect parameters include the defect size and the number of defects. The number of defect regions refers to the number of defect regions divided on a single wafer.

[0010] Step 2: Based on the preset defect pattern parameters, generate a defect pattern consisting of protrusions or pits randomly arranged at the coordinates of the dot matrix positions within the defect area. Design the defect pattern as a standard template structure layout and fabricate a target mask according to the standard template structure layout. Use a thermal oxidation process to grow a silicon dioxide thin film on the surface of a silicon wafer to obtain the target wafer, or use a chemical vapor deposition (CVD) process to grow a silicon oxide thin film on the surface of a silicon carbide wafer to obtain the target wafer.

[0011] Step 3: Use photolithography to fabricate defect patterns on the target wafer, transferring the defect patterns from the target photomask onto the target wafer; use etching to etch the target wafer to obtain a standard wafer; use scanning electron microscopy to measure the defect diameter, and measure the defect size and number of the manufactured standard wafer.

[0012] Furthermore, the number of defective regions is a positive integer greater than or equal to 1, and each defective region includes a defect pattern.

[0013] Furthermore, in the standard template structure layout, the defect size parameters in each defect pattern are different; the defect size in the defect pattern is a single size, or the defect size is distributed in intervals.

[0014] Furthermore, the single size refers to the defect particles within the region having a single, identical diameter; the defect size range distribution is within a single defect region, where the average diameter of the defect particles is a single value, and the size of the defect is a random distribution varying within a diameter range.

[0015] Furthermore, the defect pattern is a dot matrix arrangement of defect particles in the defect region, and the dot matrix arrangement of all defect particles in each defect region is a defect array.

[0016] Furthermore, by dividing each independent defect region into grids of equal size using a uniform grid method, defect particles are generated at each grid point with a probability of 50% to 80%, thereby achieving a random distribution of defect particle positions within the defect region and forming a sparse random defect array with a lattice arrangement.

[0017] Furthermore, within a single defect region, the distance between randomly occurring defect particles is greater than the spot diameter of the inspection device to be calibrated.

[0018] Furthermore, the defective region is rectangular or other shapes; the shape and size of the defective region are determined based on the size of the standard wafer and the number of defective regions.

[0019] All the defective regions do not intersect each other, and all the defective regions are evenly distributed on the standard wafer around the center point of the standard wafer.

[0020] Furthermore, a silicon dioxide thin film is grown on top of a highly polished wafer using a thermal oxidation process;

[0021] A target mask is fabricated according to the standard template structure layout, and the pattern on the target mask is transferred to the photoresist using an exposure process; then the pattern on the target mask is transferred to the target wafer using a development process.

[0022] Furthermore, information areas are obtained by laser marking on the standard wafer. The information areas are circular dot arrays in the form of QR codes with a diameter greater than 1 micrometer. The information areas do not intersect with any of the defect areas and are set near the edge of the standard wafer.

[0023] The QR code contains the region parameter information, the defect parameter information, and the defect pattern information corresponding to each defect region set on the standard wafer.

[0024] (III) Beneficial Effects: This invention provides a method for manufacturing a standard wafer with sparse scattering defects. This method can prepare standard wafers with multiple defect regions and various defect sizes, meeting the testing needs of the equipment to be calibrated. During calibration, it reduces the frequency of replacing the standard wafer, exhibiting high compatibility and practicality. Furthermore, in subsequent use, this standard wafer can be purged and cleaned, exhibiting longer stability compared to wafers manufactured from particles in the prior art, thus increasing the sample's lifespan. The random, sparse defect distribution avoids optical interference caused by scattered light between multiple defect points within the illumination area, thus preventing interference with detection accuracy. Simultaneously, this standard wafer has a controllable number and size of defects, and the standard value of the defect size is determined by scanning electron microscopy for traceability, used for calibrating surface scanning equipment, greatly improving calibration efficiency. Moreover, the defect region parameters and defect parameters are controllably generated, better meeting the needs of different types of testing equipment. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the steps in a method for manufacturing a standard wafer with sparse scattering defects according to the present invention.

[0026] Figure 2 This is a standard template structure layout with four defect areas provided by the present invention;

[0027] Figure 3 This invention provides a standard template structure layout with defects of different diameters within three defect areas.

[0028] Figure 4 This is a schematic diagram of the distribution of the defect array in the fifth defect region provided by the present invention;

[0029] Figure 5 This is a schematic diagram of a standard wafer with information regions provided by the present invention;

[0030] Icon labels:

[0031] 1-First defect area, 2-Second defect area, 3-Third defect area, 4-Fourth defect area, 5-Fifth defect area, 6-Sixth defect area, 7-Seventh defect area, 8-Eighth defect area, 9-Ninth defect area, 10-Tenth defect area, 11-Information area. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to preferred embodiments. More details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention can obviously be implemented in many other ways different from those described herein. Those skilled in the art can make similar extensions and derivations based on actual application situations without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention should not be limited by the content of this specific embodiment.

[0033] The accompanying drawings are schematic diagrams of embodiments of the present invention. It should be noted that these drawings are for illustrative purposes only and are not drawn to scale, and should not be construed as limiting the actual scope of protection of the present invention.

[0034] This invention discloses a method for manufacturing a standard wafer with sparse scattering defects, such as... Figure 1 As shown, it includes the following steps:

[0035] Step 1: Preset the defect pattern parameters for the testing equipment to be calibrated as needed. The defect pattern parameters include region parameters and defect parameters. The region parameters include the number of defect regions and the distribution location of each defect region. The defect parameters include the size of each defect in the defect region and the number of defects in each defect region. That is, the defect parameters include the defect size and the number of defects. The number of defect regions refers to the number of defect regions divided on a single wafer.

[0036] Step 2: Based on the preset defect pattern parameters, generate a defect pattern consisting of protrusions or pits randomly arranged at the lattice position coordinates within the defect area. Design the defect pattern as a standard template structure layout and fabricate a target mask according to the standard template structure layout. Use a thermal oxidation process to grow a silicon dioxide thin film on the surface of a silicon wafer to obtain the target wafer, or use a chemical vapor deposition (CVD) process to grow a silicon oxide thin film on the surface of a silicon carbide wafer to obtain the target wafer.

[0037] Step 3: Use photolithography to fabricate defect patterns on the target wafer, transferring the defect patterns from the target photomask onto the target wafer; use etching to etch the target wafer to obtain a standard wafer; use scanning electron microscopy to measure the defect diameter, and measure the defect size and number of the manufactured standard wafer.

[0038] Preferably, in this invention, the number of defective regions in the region parameters can be determined according to the needs of the testing equipment requiring calibration. The number of defective regions is a positive integer, and each defective region includes a defect pattern. Based on the determined number of defective regions, all the defective regions are uniformly distributed around the center point of the standard wafer on the standard wafer to obtain the defective region distribution position.

[0039] The uniform distribution setting specifically ensures that the distance from the center of each defect region to the center of the wafer is equal. It is important to note that the distance between different defect regions should be greater than 1 cm to prevent multiple defect regions from being scanned simultaneously by the testing equipment to be calibrated, which could affect the calibration results.

[0040] Preferably, the defective regions of this invention can be rectangular or other shapes, and different defective regions can have the same or different shapes. The shape and size of the defective regions are determined according to the size of the wafer and the number of defective regions, and all defective regions set on the wafer do not intersect each other.

[0041] In one specific embodiment of the present invention, such as Figure 2 As shown, four defect regions are uniformly distributed on a standard wafer: namely, first defect region 1, second defect region 2, third defect region 3, and fourth defect region 4. The first defect region 1 is square, the second defect region 2 is circular, the third defect region 3 is circular, and the fourth defect region 4 is rectangular. The second defect region 2 and the third defect region 3 have the same shape and area. The first defect region 1, the second defect region 2, and the fourth defect region 4 have different shapes and areas, and the first defect region 1, the second defect region 2, the third defect region 3, and the fourth defect region 4 do not intersect on the standard wafer.

[0042] Preferably, in this invention, defect parameters are set within the obtained defect region. The defect parameters include the size of each defect particle in the defect region and the number of defect particles in each defect region. That is, the defect parameters include defect size and defect quantity.

[0043] Specifically, the defect size within a single defect region is either a single size or the defect size is distributed within a range. A single size means that the defect particles within that region have a single, identical diameter, such as 100 nm, 200 nm, or 500 nm. A range-distribution of defect sizes means that within a single defect region, the average diameter of the defect particles is a single value, such as 200 nm, and the defect size is randomly distributed within a diameter range. The diameter of the defect particles within different defect regions can be determined based on the size detection capability range of the inspection equipment used for calibration. The diameter of the defects on the wafer is measured by a calibrated scanning electron microscope after fabrication.

[0044] In a wafer fabricated using the method for manufacturing a standard wafer with sparse scattering defects according to the present invention, the average diameter of the defects within the defect region is 200 nm, and the number of defects is 1000. The diameters of the 1000 defects within this defect region follow a Gaussian random distribution, and the statistical variance of the diameter distribution is 20 nm.

[0045] Specifically, the size of the defect particles differs within different defect regions; that is, the defect particles have different defect sizes within different defect regions.

[0046] The number of defects refers to the number of each defect size, which can be 1000, 5000, or 10000. The specific number of defects can be set as needed and is not required in this invention. Different defect areas can be set with the same number of defects or different numbers of defects, depending on the testing equipment to be calibrated.

[0047] In a specific embodiment of the present invention, in step two, when generating a defect pattern composed of protrusions or pits randomly arranged in the lattice position coordinates within the defect area according to preset defect pattern parameters, the defect pattern can be generated using the Niagara particle system.

[0048] The Niagara particle system includes a control unit, an emission unit, a particle generation unit, and a material unit. The control unit, a system component, is responsible for the overall management and control of the particle system, including its creation, initialization, updating, and interaction with other components or systems, allowing users to control and adjust particle effects holistically. The emission unit includes multiple emitters, each corresponding to a defect area. Each emitter can independently control one or more particle effects, such as particle position, quantity, and frequency. The particle generation unit includes modules and parameters. Modules are the foundational layer of the Niagara particle system, encapsulating particle generation and updating behaviors. By combining different modules, particle generation methods, size, and other attributes can be defined. Parameters control specific values ​​within these modules, such as initial particle size, velocity, and lifespan. The particle generation process is achieved through the combined action of these modules and parameters.

[0049] The control unit creates and initializes the particle system according to the preset defect graphic parameters. The particle generation unit defines the particle generation method and generates particles. The emission unit emits the particles generated by the particle generation unit to the material unit for rendering and coloring, generating a defect pattern composed of protrusions or pits with random grid position coordinates in the defect area.

[0050] In another specific embodiment of the present invention, in step two, when generating a defect pattern composed of protrusions or pits randomly arranged in the matrix position coordinates within the defect area according to preset defect graphic parameters, the defect pattern is randomly arranged in the defect area according to a certain matrix, and each defect area generates a defect pattern with a defect coverage rate of 50%, and the defect size is different in different defect areas.

[0051] The lattice arrangement of all defect particles within each defect region constitutes a defect array. Optionally, each independent defect region can be divided into grids of equal area using a uniform grid method. At each grid point, there is a 50% to 80% probability of a defect particle appearing. A random number P between 0 and 1 is generated. If P is greater than 0.5, a defect is generated at that grid point; otherwise, no defect is generated at that point. This process is repeated for other grid points. This method achieves the random distribution of defect particle positions within the defect region, forming a sparse random defect array with a certain lattice arrangement.

[0052] like Figure 3 As shown, three defect regions are distributed on a standard wafer: a fifth defect region 5, a sixth defect region 6, and a seventh defect region 7. Defect arrays are designed in each of these regions. The defects in each region have a different average defect diameter. For example, the average defect diameter in the fifth defect region 5 is 200 nm, in the sixth defect region 6 it is 500 nm, and in the seventh defect region 7 it is 100 nm.

[0053] It is important to note that, within a single defect region, the distance between randomly occurring defect particles needs to be greater than the diameter of the scanning detection device's spot, i.e., greater than the image resolution of the inspection device to be calibrated. This ensures that only one defect, or a few defects, are scanned on the wafer at a time, avoiding the phenomenon of multiple defects being unrecognizable by the detection device. In existing technologies, the calibration wafers used for calibration in existing inspection equipment are characterized by dense defect distribution, and the detection parameter is the wafer roughness, not the size of each defect. This invention optimizes the present invention because the defects have a defined diameter within a single defect region, are sparsely located, and exhibit long-term structural stability.

[0054] Specifically, such as Figure 4 As shown, it displays Figure 5 A partial schematic diagram of the defect array distribution within the fifth defect region 5. A detailed description is provided using the fifth defect region 5 as an example. The shape of the fifth defect region 5 is designed as follows: The fifth defect region 5 is divided into a rectangular grid of equal area, totaling 100×100 grid points. A protrusion with a defect diameter of 200 nm is placed within the fifth defect region 5. The position coordinates of the defect size within the fifth defect region 5 are distributed across grid points spaced 100 micrometers apart. Defects at each of the 100×100 grid points are randomly generated, and the probability of a random defect occurring at each grid point is N / 10000. The diameters of the N defects within each defect region follow a Gaussian random statistical distribution with a statistical variance of 20 nm. Therefore, the distance between defect particles within a single defect region on the standard wafer designed using this invention is relatively large. Consequently, the detection equipment to be calibrated can only scan one or a few defects on the standard wafer. Unlike other methods that scan only a portion of the defect area, the standard wafer designed using this invention achieves a more accurate calibration effect.

[0055] A standard template structure layout is designed based on the defect's regional parameters, defect parameters, and defect pattern. This standard template structure layout includes at least one defect region, and each defect region includes one defect pattern. The defect size in each defect pattern is different, and the number of defects corresponding to any two different defect regions may be the same or different. For example... Figure 2 The diagram shows a standard template structure layout including four defect regions. A target mask is then fabricated according to this standard template structure layout. A silicon dioxide thin film is grown on the wafer surface using a thermal oxidation process to obtain the target wafer.

[0056] In step three, photoresist is uniformly coated onto the obtained target wafer. Using photolithography, the pattern on the target mask is transferred to the photoresist through exposure. Then, a development process is used to transfer the pattern from the target mask onto the target wafer. In other words, the standard template structure pattern is transferred to the target wafer. Finally, an etching process is used to etch the target wafer to obtain the standard wafer. It is conceivable that the method for manufacturing a standard wafer with sparse scattering defects according to this invention can also create pit structures on the target wafer, or create a standard wafer with both bumps and pits. Unlike the polystyrene particle standard wafers used in the prior art, defects formed by silicon dioxide etching are not easily removed, can be cleaned, and can be reused.

[0057] Specifically, information areas are also provided on the standard wafer. For example... Figure 5As shown, an eighth defect region 8, a ninth defect region 9, a tenth defect region 10, and an information region 11 are distributed on a standard wafer. The information region 11 does not intersect with the eighth, ninth, and tenth defect regions 8 and 9, and is located near the edge of the standard wafer. The information region 11 is a circular dot matrix in the form of a QR code, with a diameter greater than 1 micrometer, and can be obtained by laser marking on the standard wafer. The QR code contains the parameter information of the regions on the standard wafer, the defect parameter information, and the defect pattern information corresponding to each defect region. The image of the information region 11 can be obtained by taking a QR code image with a microscope. The diameter information of the defects on the wafer is measured by a calibrated scanning electron microscope after fabrication. More specifically, the QR code may also contain manufacturer information for easy later maintenance.

[0058] The method for manufacturing a standard wafer with sparse scattering defects according to this invention can produce standard wafers with multiple defect regions and various defect sizes, meeting the testing needs of the inspection equipment to be calibrated. During calibration, the frequency of replacing the standard wafer is reduced, exhibiting extremely high compatibility and practicality. Furthermore, in subsequent use, this standard wafer can be purged and cleaned, exhibiting longer stability compared to wafers manufactured from particles in the prior art, thus increasing the sample's lifespan. Simultaneously, this standard wafer has a controllable number and diameter of defects, greatly improving calibration efficiency when used to calibrate surface scanning equipment. Moreover, the regional parameters and defect parameters of the defect pattern are controllably generated, further meeting the needs of different types of inspection equipment.

[0059] The above description illustrates preferred embodiments of the present invention and helps those skilled in the art to more fully understand the technical solution of the present invention. However, these embodiments are merely illustrative and should not be construed as limiting the specific implementation of the present invention to these embodiments. For those skilled in the art, several simple deductions and modifications can be made without departing from the inventive concept, and all such modifications should be considered within the protection scope of the present invention.

Claims

1. A method of manufacturing a standard wafer with sparse scattering defects, characterized by, The method comprises the following steps; Step one, presetting defect pattern parameters, wherein the defect pattern parameters comprise area parameters and defect parameters; the area parameters comprise the number of defect areas and the distribution position of each defect area; the defect parameters comprise the size of each defect in the defect area and the number of defect particles in each defect area, i.e., the defect parameters comprise defect size and defect number; the number of defect areas refers to the number of defect areas divided on a single wafer; Step two, generating a defect pattern composed of randomly arranged convex or concave dots in the dot matrix position in the defect area according to the preset defect pattern parameters, designing the defect pattern as a standard template structure layout, and manufacturing a target mask plate according to the standard template structure layout; growing a silicon dioxide film on the wafer surface by a thermal oxidation process to obtain a target wafer, or growing a silicon oxide film on the surface of a silicon carbide wafer by a chemical vapor deposition process to obtain a target wafer; Step three, manufacturing and processing the defect pattern on the target wafer by a photolithography process, transferring the defect pattern on the target mask plate to the target wafer; etching the target wafer by an etching process to obtain a standard wafer; and measuring the defect diameter by a scanning electron microscope to measure the defect size and number of the manufactured standard wafer; The defect pattern is the random arrangement of defect particles in the dot matrix of the defect area, and the dot matrix arrangement of all defect particles in each defect area is a defect array; The defect area is divided into grid areas of equal size by uniformly dividing each independent defect area, and a defect particle is generated at each grid point with a probability of 50% to 80% to realize the random distribution of defect particle positions in the defect area and form a sparse random defect array with dot matrix arrangement.

2. The method of claim 1, wherein the standard wafer is a silicon wafer. The number of defect areas is a positive integer, and each defect area comprises a defect pattern.

3. The method of claim 1, wherein the standard wafer is a silicon wafer. In the standard template structure layout, the defect size parameters in each defect pattern are different; the defect size in the defect pattern is a single size, or the defect size is an interval distribution.

4. The method of claim 3, wherein the standard wafer is a silicon wafer. The single size refers to the defect particles in the area having a single same diameter; and the defect size interval distribution refers to that, within a single defect area, the average diameter of the defect particles is a numerical value, and the defect size is a random distribution within a diameter range.

5. The method of claim 3, wherein the standard wafer is a silicon wafer. In a single defect area, the distance between randomly occurring defect particles is greater than the spot diameter of the to-be-calibrated inspection equipment.

6. The method of claim 1, wherein the standard wafer is a silicon wafer. The shape of the defect area is a rectangle or other shapes; the shape and size of the defect area are determined according to the size of the standard wafer and the number of defect areas; All the defect areas are not intersected with each other, and all the defect areas are uniformly distributed around the center point of the standard wafer on the standard wafer.

7. The method of claim 1, wherein the standard wafer is a silicon wafer. A silicon dioxide film is grown on the highly polished wafer by a thermal oxidation process; A target mask plate is manufactured according to the standard template structure layout, and an exposure process is used to transfer the pattern on the target mask plate to the photoresist; A reutilization developing process is used to transfer the pattern on the target mask to a target wafer.

8. The method of claim 1, wherein the standard wafer is a silicon wafer. An information area is marked on the standard wafer by a laser marking machine, the information area is a circular dot matrix in the form of a two-dimensional code, the diameter is greater than 1 microns, the information area does not intersect with all the defect areas, and is arranged near the edge of the standard wafer; The two-dimensional code contains the area parameter information, the defect parameter information and the defect pattern information corresponding to each defect area arranged on the standard wafer.

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