Fault detection circuit and method

Abstract

The invention provides a fault detection circuit and method. The fault detection circuit comprises a signal generation circuit, a circuit to be detected and a signal acquisition circuit. The signal generation circuit is connected with the circuit to be tested and is used for sending a test signal to the circuit to be tested; the signal acquisition circuit is connected with the to-be-tested circuit and is used for performing signal conversion on the test signal passing through the to-be-tested circuit to obtain a forward waveform. According to the embodiment of the invention, by utilizing the fault detection circuit, specific fault identification can be carried out aiming at fault states of different internal components, and the fault states of the internal components of the device can be represented more accurately and conveniently.

Description

Technical Field

[0001] The present application relates to the technical field of circuit fault detection, and in particular to a fault detection circuit and method. Background Art

[0002] With the development of integrated circuit technology, switching power supplies based on (DC-DC Converter, DC-DC) DC-DC converters have gradually replaced traditional linear power supplies with advantages such as high conversion rate, light weight and small size. The development of DC-DC power modules is in line with the development trend of light, small, intelligent and long-life equipment. It is a key part of the power system, and its reliability will directly determine the reliable application of the power system.

[0003] In actual application environments, there will be various environmental stresses such as temperature stress, mechanical stress, and electrical stress. The test screening test carried out before the power module is installed and applied is not enough to solve the degradation problem in use, especially for some more extreme application environments. Environmental stress poses a threat to the normal operation of the DC-DC power module, causing its performance to gradually degrade with the increase of working time. For example, under the action of vibration stress, the substrate is unevenly stressed, and surface-mounted devices such as (Metal-Oxide-Semiconductor Field-Effect Transistor, MOS) metal oxide semiconductor field effect transistors and diodes will crack, resulting in failure; electrical stress may also cause instantaneous breakdown of the device and other failures. For capacitors, the rise in external temperature will cause the capacitance to decrease and the equivalent series resistance ESR to increase, resulting in weakened filtering performance, which has a great impact on the output voltage ripple of the DC-DC power module. In addition, optocouplers, (Pulse Width Modulation, PWM) pulse width modulation chips, energy storage inductors and surface mount resistors are also prone to failure. These fault conditions have a great impact on the normal working state of the equipment, so it is of great significance to carry out fault research on power modules. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a fault detection circuit and method.

[0005] Based on the above purpose, the present application provides a fault detection circuit, including:

[0006] Signal generating circuit, circuit to be tested, signal acquisition circuit;

[0007] The signal generating circuit is connected to the circuit to be tested, and is used to send a test signal to the circuit to be tested;

[0008] The signal acquisition circuit is connected to the circuit to be tested and is used to perform signal conversion on the test signal passing through the circuit to be tested to obtain a positive waveform.

[0009] In a possible implementation, the signal generating circuit includes a pulse voltage generating circuit; the pulse voltage generating circuit includes a first square wave signal generating circuit and a pulse voltage signal output circuit;

[0010] The first square wave signal generating circuit is connected to the pulse voltage signal output circuit and controls the pulse voltage signal output circuit to emit a first square wave signal;

[0011] The pulse voltage signal output circuit is used to generate a pulse voltage test signal and send the pulse voltage test signal to the circuit to be tested.

[0012] In a possible implementation manner, the first square wave signal generating circuit is a first timer circuit.

[0013] In a possible implementation, the pulse voltage signal output circuit includes a first resistor and a first MOS tube;

[0014] The output end of the first timer circuit is connected to the gate of the first MOS tube;

[0015] The first resistor is connected to the source of the first MOS tube.

[0016] In a possible implementation, the signal generating circuit includes a pulse current generating circuit; the pulse current generating circuit includes a second square wave signal generating circuit and a pulse current signal output circuit;

[0017] The second square wave signal generating circuit is connected to the pulse current signal output circuit and controls the pulse current signal output circuit to generate a second square wave signal;

[0018] The pulse current signal output circuit is used to generate a pulse current test signal and send the pulse current test signal to the circuit to be tested.

[0019] In a possible implementation manner, the second square wave signal generating circuit is a second timer circuit.

[0020] In a possible implementation, the pulse current signal output circuit includes a second resistor, a third resistor and a second MOS tube;

[0021] The second resistor at the output end of the second timer circuit is connected to the gate of the second MOS tube;

[0022] The third resistor is connected to the drain of the second MOS tube.

[0023] In a possible implementation, the signal acquisition circuit includes a filtering circuit, a square wave conversion circuit and an inverting circuit;

[0024] The filter circuit is connected to the circuit to be tested, and is used to filter the test signal passing through the circuit to be tested and retain the oscillation signal;

[0025] The square wave conversion circuit is connected to the filter circuit and is used to amplify the oscillation signal and convert it into a square wave signal;

[0026] The reverse circuit is connected to the square wave conversion circuit and is used to convert the waveform of the square wave signal into a forward waveform.

[0027] In a possible implementation, the square wave conversion circuit includes an inverting amplifier and a voltage comparator;

[0028] The filter circuit is connected to the in-phase terminal of the reverse amplifier;

[0029] The output end of the inverting amplifier is connected to the inverting end of the voltage comparator;

[0030] The output terminal of the voltage comparator is connected to the inverting circuit.

[0031] Based on the same inventive concept, the embodiment of the present application further provides a fault detection method, which is applied to a fault detection circuit, comprising:

[0032] Using a signal generating circuit to send a test signal to the circuit to be tested;

[0033] Utilizing a signal acquisition circuit to receive the test signal, and performing signal conversion on the test signal to obtain a positive waveform;

[0034] Fault detection is performed based on the forward-going waveform.

[0035] From the above, it can be seen that the fault detection circuit and method provided by the present application include a signal generating circuit, a circuit to be tested, and a signal acquisition circuit; the signal generating circuit is connected to the circuit to be tested, and is used to send a test signal to the circuit to be tested; the signal acquisition circuit is connected to the circuit to be tested, and is used to perform signal conversion on the test signal passing through the circuit to be tested to obtain a positive waveform. By constructing a complete set of fault detection circuits, the present application can obtain the waveform information of the circuit to be tested through the above-mentioned fault detection circuit, and then use the waveform information to obtain the corresponding fault condition, which can more accurately and conveniently characterize the fault state of the components inside the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of a signal acquisition circuit in a fault detection circuit according to an embodiment of the present application;

[0038] Figure 2 A schematic diagram of a pulse voltage generating circuit in a fault detection circuit according to an embodiment of the present application;

[0039] Figure 3 A schematic diagram of a pulse current generating circuit in a fault detection circuit according to an embodiment of the present application;

[0040] Figure 4 Schematic diagram of a fault detection method flow chart of an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0042] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] It is understandable that before using the technical solutions of each embodiment of the present disclosure, the type, scope of use, usage scenarios, etc. of the personal information involved will be informed to the user in an appropriate manner, and the user's authorization will be obtained.

[0044] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly remind the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can independently choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.

[0045] As an optional but non-limiting implementation, in response to receiving the user's active request, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0046] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0047] As mentioned in the background technology section, with the development of integrated circuit technology, switching power supplies based on DC-DC converters have gradually replaced traditional linear power supplies with advantages such as high conversion rate, light weight, and small size. The development of DC-DC power modules is in line with the development trend of light, small, intelligent, and long-life equipment. It is a key part of the power system, and its reliability will directly determine the reliable application of the power system.

[0048] In actual application environments, there will be various environmental stresses such as temperature stress, mechanical stress, and electrical stress. The test screening test carried out before the power module is installed and applied is not enough to solve the degradation problem in use, especially for some more extreme application environments. Environmental stress poses a threat to the normal operation of the DC-DC power module, causing its performance to gradually degrade with the increase of working time. For example, under the action of vibration stress, the substrate is unevenly stressed, and surface-mounted devices such as (Metal-Oxide-Semiconductor Field-Effect Transistor, MOS) metal oxide semiconductor field effect transistors and diodes will crack, resulting in failure; electrical stress may also cause instantaneous breakdown of the device and other failures. For capacitors, the rise in external temperature will cause the capacitance to decrease and the equivalent series resistance ESR to increase, resulting in weakened filtering performance, which has a great impact on the output voltage ripple of the DC-DC power module. In addition, optocouplers, (Pulse Width Modulation, PWM) pulse width modulation chips, energy storage inductors and surface mount resistors are also prone to failure. These fault conditions have a great impact on the normal working state of the equipment, so it is of great significance to carry out fault research on power modules.

[0049] Based on the above considerations, an embodiment of the present application proposes a fault detection circuit, which includes a signal generating circuit, a circuit to be tested, and a signal acquisition circuit; the signal generating circuit is connected to the circuit to be tested, and is used to send a test signal to the circuit to be tested; the signal acquisition circuit is connected to the circuit to be tested, and is used to perform signal conversion on the test signal passing through the circuit to be tested to obtain a positive waveform. By constructing a complete set of fault detection circuits, the present application can obtain the waveform information of the circuit to be tested through the above fault detection circuit, and then use the waveform information to obtain the corresponding fault condition, which can more accurately and conveniently characterize the fault status of the internal components of the device.

[0050] The technical solutions of the embodiments of the present application are described in detail below through specific examples.

[0051] refer to Figure 1 , which is a schematic diagram of a signal acquisition circuit in a fault detection circuit of an embodiment of the present application.

[0052] refer to Figure 2 , is a schematic diagram of a pulse voltage generating circuit in a fault detection circuit in an embodiment of the present application.

[0053] refer to Figure 3 , is a schematic diagram of a pulse current generating circuit in a fault detection circuit in an embodiment of the present application.

[0054] The following combination Figure 1 , Figure 2 and Figure 3 The fault detection circuit of the present application will be described.

[0055] In the figure,

[0056] In some embodiments, the fault detection circuit includes a signal generating circuit, a circuit to be tested, and a signal acquisition circuit; the signal generating circuit is connected to the circuit to be tested, and is used to send a test signal to the circuit to be tested; the signal acquisition circuit is connected to the circuit to be tested, and is used to perform signal conversion on the test signal passing through the circuit to be tested to obtain a positive waveform.

[0057] In some embodiments, the signal generating circuit includes a pulse voltage generating circuit; the pulse voltage generating circuit includes a first square wave signal generating circuit and a pulse voltage signal output circuit; the first square wave signal generating circuit is connected to the pulse voltage signal output circuit and controls the pulse voltage signal output circuit to emit a first square wave signal; the pulse voltage signal output circuit is used to generate a pulse voltage test signal and send the pulse voltage test signal to the circuit to be tested.

[0058] In some embodiments, the first square wave signal generating circuit is a first timer circuit.

[0059] In some embodiments, the pulse voltage signal output circuit includes a first resistor and a first MOS tube; the output end of the first timer circuit is connected to the gate of the first MOS tube; the first resistor is connected to the source of the first MOS tube.

[0060] In some embodiments, the signal generating circuit includes a pulse current generating circuit; the pulse current generating circuit includes a second square wave signal generating circuit and a pulse current signal output circuit; the second square wave signal generating circuit is connected to the pulse current signal output circuit and controls the pulse current signal output circuit to emit a second square wave signal; the pulse current signal output circuit is used to generate a pulse current test signal and send the pulse current test signal to the circuit to be tested.

[0061] In some embodiments, the second square wave signal generating circuit is a second timer circuit.

[0062] In some embodiments, the pulse current signal output circuit includes a second resistor, a third resistor and a second MOS tube; the second resistor at the output end of the second timer circuit is connected to the gate of the second MOS tube; the third resistor is connected to the drain of the second MOS tube.

[0063] In some embodiments, the signal acquisition circuit includes a filtering circuit, a square wave conversion circuit and a reverse circuit; the filtering circuit is connected to the circuit to be tested, and is used to filter the test signal passing through the circuit to be tested and retain the oscillation signal; the square wave conversion circuit is connected to the filtering circuit, and is used to amplify the oscillation signal and convert it into a square wave signal; the reverse circuit is connected to the square wave conversion circuit, and is used to convert the waveform of the square wave signal into a forward waveform.

[0064] In some embodiments, the square wave conversion circuit includes a reverse amplifier and a voltage comparator; the filter circuit is connected to the in-phase end of the reverse amplifier; the output end of the reverse amplifier is connected to the reverse end of the voltage comparator; and the output end of the voltage comparator is connected to the reverse circuit.

[0065] In this embodiment, reference Figure 1 ,The signal acquisition circuit is composed of multiple functional modules, covering filter circuit, square wave conversion circuit and ,inverting circuit.

[0066] The filter circuit filters out the DC signal component in the output signal of the previous stage, and is composed of a first capacitor C3, a second capacitor C4, a third capacitor C6 and a third resistor R4. The third resistor R4 and the third capacitor C6 are first connected in series and then connected in parallel with the first capacitor C3 and the second capacitor C4, and the voltage of the third resistor R4 is taken as the output voltage; the first reverse amplifier U1 is composed of an operational amplifier LF411, and is connected to form an inverting proportional operation circuit in the form of negative feedback. The fourth resistor R2 and the first resistor R3 are proportional operation resistors to control the proportional operation coefficient. The fourth capacitor C5 and the fifth capacitor C7 are output filter capacitors. The first voltage regulator D3 connected in parallel with the fourth capacitor C5 and the fifth capacitor C7 is a voltage regulator to make the output voltage a rectangular wave; the second reverse Amplifier U2 is composed of operational amplifier LM339 and connected in the form of an open-loop comparator. Its in-phase input terminal is connected to a 2V DC level, and the DC level is obtained by series voltage division of the 5V DC power supply by the eighth resistor R8 and the ninth resistor R9. The inverting input terminal is connected to the rectangular wave voltage output by the previous operational amplifier. The output of the comparator is still a rectangular wave signal, but it is shifted in level; the third reverse amplifier U3 is composed of operational amplifier LF411 and is connected in the form of an inverting proportional operational circuit in the form of negative feedback. The fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are proportional operational resistors. The fifth resistor R5 and the seventh resistor R7 have a series voltage division effect to control the inverting proportional operational coefficient and realize the inversion of the input signal.

[0067] The operation process is as follows:

[0068] Input signal processing (filter circuit): The input signal first passes through the filter module (first capacitor C3, second capacitor C4, third capacitor C6 and third resistor R4) to effectively filter out high-frequency noise and DC components and retain key effective signals. The filtered signal is converted into a relatively smooth AC signal.

[0069] Square wave conversion (square wave conversion circuit): The filtered signal is sent to the non-inverting input terminal (Pin 3) of the first reverse amplifier (U1, LF411). The reference voltage is set by adjusting the first voltage divider resistor R3, and then the difference between the input signal and the reference voltage is compared. When the input signal exceeds the reference voltage, the operational amplifier outputs a high level; otherwise, it outputs a low level. This module converts the input signal into a square wave signal corresponding to the original signal characteristics.

[0070] Shaping and protection circuit: The shaping circuit is composed of the fourth capacitor C5, the fifth capacitor C7 and the second voltage regulator diode D3, which is used to further stabilize the signal and limit the amplitude to protect the subsequent circuit. The second voltage regulator diode D3 ensures that the output level is maintained within a specific range to prevent the signal from overloading and damaging the subsequent circuit.

[0071] Reverse circuit: The square wave signal is input through the inverting terminal of the third reverse amplifier (U3, LF411) to achieve signal polarity reversal. The amplification factor is set through the feedback resistor sixth resistor R6 to adjust the amplitude of the output signal. This module is responsible for adjusting the polarity and amplitude of the output signal to meet the needs of subsequent circuits.

[0072] Output signal: The final output is a shaped square wave signal for use by subsequent circuits. The number of peaks in the output signal corresponds to the number of peaks in the input signal, which is used to determine the characteristics of the input signal.

[0073] Functions of each module and component: The filtering circuit includes: a first capacitor C3, a second capacitor C4, and a third capacitor C6 (capacitors): filter out noise and smooth signals.

[0074] The third resistor R4 (resistance): cooperates with the capacitor to form an RC filter circuit to control the filter cutoff frequency. Function: remove high-frequency interference and DC components in the input signal and retain the effective low-frequency signal.

[0075] The square wave conversion circuit includes: the first reverse amplifier U1 (LF411 reverse amplifier): compares the input signal with the reference voltage, outputs high and low levels, and realizes the square wave of the signal. The first resistor R3 (resistance): sets the reference voltage and controls the threshold of the comparator. The fourth capacitor C5 and the fifth capacitor C7 (capacitor): are used for signal shaping and smoothing. The second voltage regulator diode D3 (voltage regulator diode): limits the signal amplitude and protects the subsequent circuit. Function: Convert the filtered analog signal into a square wave signal.

[0076] Reverse circuit: The third reverse amplifier U3 (LF411 reverse amplifier): performs inverse amplification on the square wave signal and outputs a signal with opposite polarity.

[0077] The fifth resistor R5 and the sixth resistor R6 (feedback resistor): control the gain of the operational amplifier and adjust the output signal amplitude. Function: adjust the amplitude and reverse the polarity of the square wave signal.

[0078] Power module: V4, V6, V7 (power supply): provide the required positive and negative voltages for the circuit. Function: provide a stable power supply for the entire circuit.

[0079] In the above circuit, the input signal is filtered, square-wave converted and reversely processed, and finally a stable square-wave signal is output. It is used to collect the peak information of the input signal. The subsequent module counts the number of pulses of the square-wave signal to evaluate the working status of the corresponding device.

[0080] In this embodiment, the signal generating circuit may be a pulse current generating circuit, a pulse voltage generating circuit, and a DC signal circuit.

[0081] Specifically, Figure 2 As shown, the pulse voltage generating circuit in the embodiment uses a 555 timer chip as the core to generate a stable square wave signal, thereby controlling the conduction and cutoff of the MOS tube to ensure the output of a constant pulse signal. It should be noted that the 555 timer chip can be any timer or other square wave signal generating circuit. The reason why the 555 timer is used in this application is that the structure is simple and easy to build.

[0082] In this embodiment, the circuit parameter setting is described as follows: in normal operation, the output voltage reaches a stable state at 4ms after startup. The input power source adopts a voltage signal source, the initial voltage is 100V, it rises to 120V at 0.5ns at 6ms, maintains for 5ms and then drops to 100V at 50ns. The duty cycle of the circuit is 0.5.

[0083] The main part of the circuit is a 555 timer, in which the VCC and GND of the 555 timer chip are connected to a 5V DC voltage and a ground wire respectively; Pin 5 is connected to the ground and a filter capacitor, the sixth capacitor C2; Pin 4 is the reset control terminal of the 555 timer, connected to a 5V DC level; Pin 2 is the trigger terminal, and Pin 7 is the voltage comparison terminal. First, the 5V DC power supply charges the seventh capacitor C1 through the eighth resistor R1 and the ninth resistor R2, and Pin 7 is connected to the seventh capacitor C1. When the voltage on the seventh capacitor C1 is charged to exceed the set higher threshold voltage, Pin 2 (trigger terminal) triggers the 555 timer, and the output terminal Pin 3 outputs a high-level signal. If the voltage on the seventh capacitor C1 continues to increase, Pin 7 (charge release terminal) is turned on. , the DC power supply is directly grounded through the eighth resistor R1, and the seventh capacitor C1 is also discharged to the ground through the ninth resistor R2. When the voltage of the seventh capacitor C1 drops below the set lower threshold voltage, pin 7 is turned off, and the 5V DC power supply continues to charge the seventh capacitor C1 through the eighth resistor R1 and the ninth resistor R2. This cycle can generate a pulse voltage signal; pin 3 is connected to the gate of the first MOS tube M1 through a tenth resistor R4'. The first MOS tube M1 adopts a source follower connection method. The signal is output from the source of the first MOS tube M1. The output pulse voltage of pin 3 is used to control the conduction and cutoff of the first MOS tube M1. When it is turned on, current flows through the eleventh resistor R3' to generate a voltage drop. This voltage is the output voltage signal.

[0084] The operating principle is as follows:

[0085] The 555 timer is set as an astable oscillator, and the frequency and duty cycle of its output pulse signal are determined by the combination of external resistors and capacitors. After power is turned on, the seventh capacitor C1 is charged through the eighth resistor R1 and the ninth resistor R2, and the voltage gradually rises. When the capacitor voltage rises to the threshold voltage (2 / 3Vcc) of the 555 timer, the internal discharge pin (Pin 7) is activated, and the capacitor is discharged through the ninth resistor R2. As the capacitor voltage drops to the trigger voltage (1 / 3Vcc), the discharge pin is closed and the capacitor starts charging again. This process repeats itself, and the 555 timer outputs a square wave signal at the output end (Pin 3).

[0086] Square wave signal controls MOS tube: The output signal of the 555 timer is transmitted to the gate of the first MOS tube M1 through the tenth resistor R4'. When the output signal is high, the first MOS tube is turned on and the current passes through the load; when the output signal is low, the first MOS tube is turned off and the current is disconnected. Thus, the square wave signal is amplified by the first MOS tube, drives the load, and forms a stable voltage pulse signal.

[0087] Circuit Components: 555 timer (X1): The core component for generating square wave signals. The operating frequency and duty cycle are determined by external resistors and capacitors.

[0088] The eighth resistor R1 and the ninth resistor R2 (timing resistor) together with the seventh capacitor C1 determine the oscillation frequency and signal duty cycle of the 555 timer.

[0089] The seventh capacitor C1 (timing capacitor) controls the oscillation period of the 555 timer and cooperates with the eighth resistor R1 and the ninth resistor R2 to adjust the frequency of the output signal.

[0090] The sixth capacitor C2 (decoupling capacitor) filters out high-frequency noise from the power supply to ensure stable operation of the 555 timer.

[0091] The tenth resistor R4' (gate current limiting resistor): limits the current from the output end of the 555 timer to the gate of the first MOS tube to protect the circuit.

[0092] The first MOS tube M1 (IRF540, N-channel MOS tube): controlled by the output signal of the 555 timer, amplifies the signal and drives the load. When the gate voltage reaches the threshold, the first MOS tube is turned on and the current passes through the load.

[0093] The first voltage V1 (power supply): provides operating voltage for the circuit.

[0094] The main function of this circuit is to generate a stable pulse signal, and control the switch of the first MOS tube through the square wave signal generated by the 555 timer, thereby driving the load. By adjusting the parameters of the eighth resistor R1, the ninth resistor R2 and the seventh capacitor C1, the frequency and duty cycle of the output pulse signal can be changed to meet different application requirements.

[0095] like Figure 3 As shown, the pulse current generating circuit in the embodiment of the present application.

[0096] The 555 timer is used to generate a pulse voltage signal, which is then converted into a corresponding pulse current signal through the second MOS tube. The main principle of the circuit is consistent with the pulse voltage generation circuit, but the output end controls the generation and termination of the output end current by controlling the on and off of the second MOS tube M2.

[0097] In this embodiment, the circuit parameter settings are described as follows: Under normal output conditions, the output voltage reaches a stable state at 4ms. The test signal uses a current pulse source to provide a current that rises to 4A in 1us 6ms after the circuit is started, maintains for 6ms, and then drops to 0A in 1us.

[0098] The following is a detailed interpretation of the circuit operation process and an analysis of the functions of each electronic component:

[0099] The operation process is as follows:

[0100] 555 timer operation (square wave signal generation circuit): The 555 timer (X1) works in the astable mode, and outputs a periodic square wave signal at the output end (Pin 3) through the charging and discharging of the external twelfth resistor R1', the thirteenth resistor R2' and the capacitor C1. The eighth capacitor C1' is charged in the initial stage, and the voltage gradually rises until it reaches the threshold voltage (2 / 3Vcc), activating the discharge pin (Pin 7) inside the 555 timer, and then the capacitor is discharged through the thirteenth resistor R2'. When the capacitor voltage drops to the trigger voltage (1 / 3Vcc), the discharge pin is closed and the capacitor starts to charge again. In this way, the 555 timer output end can output a stable square wave signal.

[0101] Square wave signal controls MOS tube: The square wave signal output by the 555 timer is transmitted to the gate of the second MOS tube M2 (IRF540) through the current limiting resistor 14th resistor R5'. When the square wave signal is in a high level state, the second MOS tube M2 is turned on, and the current flows from V1 (12V power supply) through the load resistor 15th resistor R6' to form a pulse current. When the square wave signal is in a low level state, the second MOS tube is turned off and the current is interrupted.

[0102] Pulse current output: The current passes through the fifteenth resistor R6', converting the conduction and cutoff of the second MOS tube into the on-off of the current, thereby generating a periodic pulse current signal. The load resistor converts the current signal into a voltage signal for use in subsequent circuits.

[0103] The functions of the components are as follows:

[0104] 555 Timer Module:

[0105] X1 (555 timer): core component, responsible for generating periodic square wave signals and controlling the switching of MOS tubes to generate pulse current.

[0106] The twelfth resistor R1' (1500Ω) and the thirteenth resistor R2' (700Ω): cooperate with the eighth capacitor C1' to set the oscillation frequency and square wave duty cycle of the 555 timer.

[0107] The eighth capacitor C1' (1 μF) is a timing capacitor for controlling the oscillation period.

[0108] The ninth capacitor C3' (0.01μF): a decoupling capacitor used to filter high-frequency noise in the power supply to ensure the stable operation of the 555 timer.

[0109] MOS tube control module:

[0110] The second MOS tube M2 (IRF540, N-channel MOS tube): acts as a switch and is controlled by the square wave signal output by the 555 timer to achieve conduction and cutoff.

[0111] The fourteenth resistor R5' (1 kΩ): a gate current limiting resistor, which limits the output current of the 555 timer and protects the second MOS tube and the 555 timer.

[0112] Load Module:

[0113] The fifteenth resistor R6' (10Ω): a load resistor, converting the current signal into a voltage signal and limiting the circuit current at the same time.

[0114] V1 (12V power supply): provides working power for the entire circuit.

[0115] The embodiment of the present application utilizes the pulse square wave signal generated by the 555 timer to control the switch of the second MOS tube, thereby realizing the conversion of the voltage signal into a periodic pulse current signal.

[0116] In some embodiments, a DC test signal may also be input, and the fault status of the MOS tube generally includes short circuit, open circuit and increased drain-source resistance. The working status of the MOS tube can be obtained by detecting the DC status signal.

[0117] It can be seen from the above embodiments that the fault detection circuit described in the embodiments of the present application includes a signal generating circuit, a circuit to be tested, and a signal acquisition circuit; the signal generating circuit is connected to the circuit to be tested, and is used to send a test signal to the circuit to be tested; the signal acquisition circuit is connected to the circuit to be tested, and is used to perform signal conversion on the test signal passing through the circuit to be tested to obtain a positive waveform. The present application constructs a complete set of fault detection circuits, and can obtain the waveform information of the circuit to be tested through the above fault detection circuit. The corresponding fault condition can then be obtained using the waveform information, and the fault state of the internal components of the device can be more accurately and conveniently characterized.

[0118] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a fault detection method.

[0119] refer to Figure 4 , the fault detection method comprises:

[0120] Step S401, using a signal generating circuit to send a test signal to the circuit under test;

[0121] Step S402, using a signal acquisition circuit to receive the test signal, and performing signal conversion on the test signal to obtain a forward waveform;

[0122] Step S403: completing fault detection based on the forward waveform.

[0123] The method of the above embodiment is used to implement the corresponding fault detection circuit in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0124] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0125] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0126] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0127] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0128] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0129] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A fault detection circuit, characterized in that: include: Signal generating circuit, circuit to be tested, signal acquisition circuit; The signal generating circuit is connected to the circuit to be tested, and is used to send a test signal to the circuit to be tested; The signal acquisition circuit is connected to the circuit to be tested and is used to perform signal conversion on the test signal passing through the circuit to be tested to obtain a positive waveform.

2. The circuit according to claim 1, characterized in that The signal generating circuit includes a pulse voltage generating circuit; the pulse voltage generating circuit includes a first square wave signal generating circuit and a pulse voltage signal output circuit; The first square wave signal generating circuit is connected to the pulse voltage signal output circuit and controls the pulse voltage signal output circuit to emit a first square wave signal; The pulse voltage signal output circuit is used to generate a pulse voltage test signal and send the pulse voltage test signal to the circuit to be tested.

3. The circuit according to claim 2, characterized in that The first square wave signal generating circuit is a first timer circuit.

4. The circuit according to claim 3, characterized in that The pulse voltage signal output circuit includes a first resistor and a first MOS tube; The output end of the first timer circuit is connected to the gate of the first MOS tube; The first resistor is connected to the source of the first MOS tube.

5. The circuit according to claim 1, characterized in that The signal generating circuit includes a pulse current generating circuit; the pulse current generating circuit includes a second square wave signal generating circuit and a pulse current signal output circuit; The second square wave signal generating circuit is connected to the pulse current signal output circuit and controls the pulse current signal output circuit to generate a second square wave signal; The pulse current signal output circuit is used to generate a pulse current test signal and send the pulse current test signal to the circuit to be tested.

6. The circuit according to claim 5, characterized in that The second square wave signal generating circuit is a second timer circuit.

7. The circuit according to claim 6, characterized in that The pulse current signal output circuit includes a second resistor, a third resistor and a second MOS tube; The second resistor at the output end of the second timer circuit is connected to the gate of the second MOS tube; The third resistor is connected to the drain of the second MOS tube.

8. The circuit according to claim 1, characterized in that The signal acquisition circuit includes a filtering circuit, a square wave conversion circuit and a reverse circuit; The filter circuit is connected to the circuit to be tested, and is used to filter the test signal passing through the circuit to be tested and retain the oscillation signal; The square wave conversion circuit is connected to the filter circuit and is used to amplify the oscillation signal and convert it into a square wave signal; The reverse circuit is connected to the square wave conversion circuit and is used to convert the waveform of the square wave signal into a forward waveform.

9. The circuit according to claim 8, characterized in that The square wave conversion circuit includes an inverting amplifier and a voltage comparator; The filter circuit is connected to the in-phase terminal of the reverse amplifier; The output end of the inverting amplifier is connected to the inverting end of the voltage comparator; The output terminal of the voltage comparator is connected to the inverting circuit.

10. A fault detection method, characterized in that: Applied to the fault detection circuit according to any one of claims 1 to 9, the method comprises: Using a signal generating circuit to send a test signal to the circuit to be tested; Utilizing a signal acquisition circuit to receive the test signal, and performing signal conversion on the test signal to obtain a positive waveform; Fault detection is performed based on the forward-going waveform.

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