Chip test system and test method

Abstract

The invention relates to the technical field of chip testing, and discloses a chip testing system and a testing method, which can accurately adjust the downward pressing formation of chip testing and prevent a chip from being crushed. A chip testing system comprises a rack, a chip storage mechanism, a testing mechanism and a feeding mechanism. And the chip storage mechanism is arranged on the rack. The feeding mechanism comprises a translation mechanism, a lifting mechanism, a plurality of chip grabbing mechanisms and a limiting mechanism. And the plurality of chip grabbing mechanisms are arranged on the lifting mechanism. And the lifting mechanism is arranged on the translation mechanism. The translation mechanism can drive the chip grabbing mechanism to move in the horizontal plane. The lifting mechanism can drive the chip grabbing mechanism to ascend or descend. The chip grabbing mechanism can move to any corner above the testing mechanism on the horizontal plane through cooperation of the translation mechanism and the lifting mechanism, and chips are grabbed flexibly. The limiting mechanism can limit the maximum descending stroke of the lifting mechanism, and the chip grabbing mechanism is prevented from being driven to crush the chip.

Description

Technical Field

[0001] The present invention relates to, and in particular to, a chip testing system and a testing method. Background Art

[0002] With the rapid development of electronic technology, the types and functions of chips are constantly increasing, especially in the fields of high-performance computing, Internet of Things, smart hardware, etc., the requirements for chip functionality, stability and reliability are getting higher and higher. As the core component of electronic products, chips must undergo rigorous testing before they can be put into production and use. Chip testing is not only to detect whether the chip can work properly, but also to ensure its stability and reliability under various environmental conditions.

[0003] Traditional chip testing systems usually include test racks, test boards, loading devices, etc. In these systems, the testing process mainly relies on manual operation or simple robotic arm control. Although basic functional tests can be completed, there are certain problems in actual applications: Low efficiency of manual operation: Traditional test systems often require manual placement of chips at test locations for testing, resulting in low test efficiency and prone to operational errors or misplacement, which affects test accuracy and production efficiency.

[0004] Lack of Automation: The existing chip testing equipment has a low degree of automation, especially in the process of chip grabbing, transferring and sorting, which often relies on manual operation or simple mechanical control. For high-throughput production requirements, manual operation cannot meet the needs of large-scale and efficient testing.

[0005] Chip damage is prone to occur: In the traditional testing process, the chip grabbing and placement operations often lack precise control measures, causing unnecessary pressure or damage to the chip, increasing the risk of chip damage, and affecting product quality and the reliability of test results.

[0006] Limited test compatibility and extensibility: Traditional system designs are often configured for chips of specific sizes or types and cannot flexibly adapt to chips of different types or sizes. This results in the need to redesign or replace equipment when faced with new types of chips, increasing the maintenance cost and difficulty of the test system.

[0007] Lack of effective chip positioning and placement accuracy control: Insufficient control over the positioning of the test position and the chip placement accuracy may result in the chip being unable to be correctly placed at the test position during testing, affecting the accuracy of the test results. Especially in the testing of tiny chips, test errors may affect the final test results. Summary of the invention

[0008] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a chip testing system that can accurately adjust the pressure formation of chip testing to avoid damaging the chip.

[0009] The present invention also provides a testing method having the above chip testing system.

[0010] A chip testing system according to an embodiment of the first aspect of the present invention comprises: a rack; a chip storage mechanism, the chip storage mechanism being arranged on the rack, the chip storage mechanism being used to accommodate chips; a testing mechanism, the testing mechanism being arranged on the rack, the testing mechanism comprising a plurality of testing components, the testing components comprising a testing table, a testing board bracket and a plurality of testing boards, the testing table being arranged on the rack, the testing board bracket being arranged on the testing table, a plurality of the testing boards being evenly arranged on the testing board bracket, and the testing board being provided with a testing position for accommodating a chip to be tested; a loading mechanism, the loading mechanism being movably arranged on the rack The loading mechanism is arranged on the rack, and is configured to grab the material in the chip storage mechanism and place it in the test assembly; the loading mechanism includes a translation mechanism, a lifting mechanism, a plurality of chip grabbing mechanisms and a limiting mechanism, and the plurality of chip grabbing mechanisms are arranged on the lifting mechanism, and the lifting mechanism is arranged on the translation mechanism, and the translation mechanism can drive the chip grabbing mechanism to move in a horizontal plane, and the lifting mechanism can drive the chip grabbing mechanism to rise or fall, and the limiting mechanism is arranged on the lifting mechanism, and the limiting mechanism can limit the maximum displacement of the chip grabbing mechanism to prevent the chip grabbing mechanism from crushing the chip.

[0011] At least the following beneficial effects are achieved: A chip testing system includes a rack, a chip storage mechanism, a testing mechanism and a feeding mechanism. The chip storage mechanism is arranged on the rack. The chip storage mechanism is used to accommodate chips. The testing mechanism is arranged on the rack. The testing mechanism includes several groups of test components. The test components include a test bench, a test board bracket and several test boards. The test bench is arranged on the rack. The test board bracket is arranged on the test bench. Several test boards are evenly arranged on the test board bracket. The test board is provided with a test position for accommodating the chip to be tested. The feeding mechanism is movably arranged on the rack. The feeding mechanism is configured to grab the material in the chip storage mechanism and place it in the test component. The feeding mechanism includes a translation mechanism, a lifting mechanism, several chip grabbing mechanisms and a limiting mechanism. Several chip grabbing mechanisms are arranged on the lifting mechanism. The lifting mechanism is arranged on the translation mechanism. The translation mechanism can drive the chip grabbing mechanism to move in a horizontal plane. The lifting mechanism can drive the chip grabbing mechanism to rise or fall. The limiting mechanism is arranged on the lifting mechanism. The limit mechanism can limit the maximum displacement of the chip grabbing mechanism to prevent the chip grabbing mechanism from crushing the chip. The chip grabbing mechanism can move to any corner above the test mechanism on the horizontal plane through the cooperation of the translation mechanism and the lifting mechanism to flexibly grab the chip. The limit mechanism can limit the maximum descending stroke of the lifting mechanism to avoid driving the chip grabbing mechanism to crush the chip.

[0012] According to some embodiments of the present invention, the lifting mechanism includes a translation slide, a lifting rail and a lifting cylinder, the translation slide is slidably set on the translation mechanism, the lifting rail is set on the translation slide, the lifting cylinder is set at one end of the lifting rail, and the chip grabbing mechanism is slidably set on the lifting rail and connected to the output end of the lifting cylinder.

[0013] According to some embodiments of the present invention, the chip grabbing mechanism includes a mounting block, a mounting plate and a plurality of negative pressure grabbers. The mounting block is slidably disposed on the lifting rail and is connected to the output end of the lifting cylinder. The mounting plate is disposed on the mounting block, and a plurality of negative pressure grabbers are disposed on the mounting plate.

[0014] According to some embodiments of the present invention, the negative pressure grabber includes a mounting part, a negative pressure connecting pipe and a suction nozzle, the mounting part is arranged on the mounting plate, the negative pressure connecting pipe is arranged at one end of the mounting part, the suction nozzle is arranged at the other end of the mounting part, and the other end of the negative pressure connecting pipe is connected to a negative pressure generating device.

[0015] According to some embodiments of the present invention, the limiting mechanism includes a limiting seat, a limiting plate and a limiting block. The limiting seat is arranged on the translation mechanism and is located on one side of the lifting rail. The limiting plate is arranged on the chip grabbing mechanism. The limiting plate moves with the chip grabbing mechanism to approach or move away from the limiting seat. When the lower end of the chip grabbing mechanism abuts against the test assembly, the limiting seat is fitted with the limiting plate. The limiting block is detachably arranged on the limiting seat. The thickness of the limiting block is consistent with the thickness of the chip to be tested. The limiting plate falls and contacts the limiting block.

[0016] According to some embodiments of the present invention, a connecting groove is provided on the limiting seat, and a connecting protrusion is provided on the limiting block, and the connecting protrusion can be inserted into the connecting groove.

[0017] According to some embodiments of the present invention, the translation mechanism includes a first translation rail, a translation truss and a second translation rail, the first translation rail is arranged on both sides of the frame, the translation truss is slidably arranged on the first translation rail and is located above the testing mechanism, the second translation rail is arranged on the translation truss, a plurality of chip grabbing mechanisms are slidably arranged on the second translation rail, the length directions of the first translation rail and the second translation rail are perpendicular to each other, and the translation slide is slidably arranged on the second translation rail.

[0018] According to some embodiments of the present invention, the chip storage mechanism includes a plurality of tray racks, a slide rack, a chip transfer and grasping device, and a chip conveying mechanism, wherein the plurality of tray racks are arranged on the rack, the slide rack is arranged on the rack and is located above the tray rack, the chip transfer and grasping device is slidably arranged on the slide rack, the chip conveying mechanism is arranged on the rack, and the chip conveying mechanism is capable of conveying the chip to one side of the testing mechanism.

[0019] According to some embodiments of the present invention, the testing mechanism further includes a chip in place detection component, the chip in place detection component includes a chip sensor and an alarm light, the chip sensor is arranged on the testing bench, the chip sensor can detect whether the chip is placed on the testing position, the alarm light is arranged on the testing bench, and when the chip sensor detects that there is no chip placed on the testing position, the alarm light flashes.

[0020] A testing method according to an embodiment of the second aspect of the present invention includes a chip testing system according to an embodiment of the first aspect of the present invention, including the following steps: first, the lifting mechanism is debugged, and the maximum stroke of the lifting mechanism is manually adjusted so that the limit plate and the limit seat are in contact with the suction nozzle at the same time; then a limit block with the same thickness as the chip to be tested is placed on the limit seat, and then the equipment is started, the chip transfer and grasping device places the chip to be tested in the chip conveying mechanism, the loading mechanism takes the chip to be tested from the chip conveying mechanism and places it on the test position for testing, and after the test is completed, the loading mechanism puts the tested chip back into the chip conveying mechanism, the chip conveying mechanism conveys the chip back to one side of the chip transfer and grasping device, and the chip transfer and grasping device places the tested chip in the tray rack.

[0021] At least the following beneficial effects are achieved: This testing method has all the beneficial effects brought by the above-mentioned chip testing system, which will not be described repeatedly here.

[0022] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 It is a structural schematic diagram of an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a chip grabbing mechanism according to an embodiment of the present invention; Figure 3 This is a schematic structural diagram of a chip lifting mechanism according to an embodiment of the present invention; Figure 4 for Figure 1 A partial enlarged view of the middle A; Figure 5 for Figure 3 A partial enlarged view of point B in the middle.

[0024] Figure Number: Rack 10; Chip storage mechanism 20, tray rack 21, slide rail rack 22, chip transfer and grabbing device 23, chip conveying mechanism 24; Testing mechanism 30, testing assembly 31, testing table 311, testing board support 312, testing board 313, chip in place detection assembly 32, chip sensor 321, warning light 322; Feeding mechanism 40, translation mechanism 41, first translation rail 411, translation truss 412, second translation rail 413, lifting mechanism 42, translation slide 421, lifting rail 422, lifting cylinder 423, chip grabbing mechanism 43, mounting block 431, mounting plate 432, negative pressure grabber 433, mounting portion 433a, negative pressure connecting pipe 433b, suction nozzle 433c, limiting mechanism 44, limiting seat 441, connecting groove 441a, limiting plate 442, limiting block 443, connecting protrusion 443a. DETAILED DESCRIPTION

[0025] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0026] In the description of the present invention, if there is a description of first and second, it is only for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0027] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0028] Reference Figures 1 to 5 A chip testing system includes a rack 10, a chip storage mechanism 20, a testing mechanism 30 and a loading mechanism 40.

[0029] Through the design of this overall structure, the system can effectively organize and manage various components to ensure the smooth and efficient chip testing process. The rack 10 provides a stable support as the foundation of the system, which is convenient for the installation and debugging of subsequent components. The integration of the overall structure improves the automation and reliability of the production process.

[0030] The chip storage mechanism 20 is disposed on the rack 10. The chip storage mechanism 20 is used to accommodate chips.

[0031] The chip storage mechanism 20 ensures that the chips are stored in an orderly manner before testing, and prevents the chips from being damaged due to collision or improper storage. In addition, a reasonable storage design can improve the efficiency of chip access and reduce accidental damage during chip operation.

[0032] The test mechanism 30 is arranged on the rack 10. The test mechanism includes a plurality of test components 31. The test components 31 include a test table 311, a test board support 312, and a plurality of test boards 313. The test table 311 is arranged on the rack 10. The test board support 312 is arranged on the test table 311. A plurality of test boards 313 are evenly arranged on the test board support 312. The test board 313 is provided with a test position for accommodating the chip to be tested.

[0033] This multi-level, evenly arranged test board 313 design can support multi-chip parallel testing and improve test efficiency. The test position accurately locates the chip to ensure the accuracy and consistency of the test and reduce test errors caused by chip positioning errors.

[0034] The loading mechanism 40 is movably disposed on the frame 10 . The loading mechanism 40 is configured to grab materials in the chip storage mechanism 20 and place them in the test assembly 31 .

[0035] The automated design of the loading mechanism 40 greatly improves the efficiency of the test process and reduces the need for manual intervention. Precise chip grabbing and placement avoids chip damage during the transfer process, especially in the operation of precision chips, ensuring efficient and non-destructive operation.

[0036] The feeding mechanism 40 includes a translation mechanism 41, a lifting mechanism 42, a plurality of chip grabbing mechanisms 43 and a limiting mechanism 44. The plurality of chip grabbing mechanisms 43 are arranged on the lifting mechanism 42. The lifting mechanism 42 is arranged on the translation mechanism 41. The translation mechanism 41 can drive the chip grabbing mechanism 43 to move in a horizontal plane. The lifting mechanism 42 can drive the chip grabbing mechanism 43 to rise or fall. The limiting mechanism 44 is arranged on the lifting mechanism 42. The limiting mechanism 44 can limit the maximum displacement of the chip grabbing mechanism 43 to prevent the chip grabbing mechanism 43 from crushing the chip.

[0037] It is understandable that the chip grabbing mechanism 43 can move to any corner above the testing mechanism 30 on the horizontal plane through the cooperation of the translation mechanism 41 and the lifting mechanism 42 to flexibly grab the chip. The limit mechanism 44 can limit the maximum descending stroke of the lifting mechanism 42 to avoid driving the chip grabbing mechanism 43 to crush the chip.

[0038] Reference Figures 1 to 5 The lifting mechanism 42 includes a translation slide 421, a lifting rail 422 and a lifting cylinder 423. The translation slide 421 is slidably disposed on the translation mechanism 41. The lifting rail 422 is disposed on the translation slide 421. The lifting cylinder 423 is disposed at one end of the lifting rail 422. The chip grabbing mechanism 43 is slidably disposed on the lifting rail 422 and is connected to the output end of the lifting cylinder 423.

[0039] It can be understood that the translation mechanism 41 can drive the translation slide 421 to move in the horizontal plane, and the lifting cylinder 423 can drive the chip grabbing mechanism 43 to move up and down so as to move closer to or away from the chip in the vertical direction. Reference Figures 1 to 5 The chip grabbing mechanism 43 includes a mounting block 431, a mounting plate 432, and a plurality of negative pressure grabbers 433. The mounting block 431 is slidably disposed on the lifting rail 422 and connected to the output end of the lifting cylinder 423. The mounting plate 432 is disposed on the mounting block 431. The plurality of negative pressure grabbers 433 are disposed on the mounting plate 432.

[0040] It is understandable that the mounting block 431 can rise or fall along the lifting rail 422 under the drive of the lifting cylinder 423, driving the mounting plate 432 and a plurality of negative pressure grabbers 433 to rise or fall.

[0041] Reference Figures 1 to 5 The negative pressure grabber 433 includes a mounting portion 433a, a negative pressure connecting pipe 433b and a suction nozzle 433c. The mounting portion 433a is disposed on the mounting plate 432. The negative pressure connecting pipe 433b is disposed at one end of the mounting portion 433a. The suction nozzle 433c is disposed at the other end of the mounting portion 433a. The other end of the negative pressure connecting pipe 433b is connected to a negative pressure generating device.

[0042] Reference Figure 5 The limiting mechanism 44 includes a limiting seat 441, a limiting plate 442 and a limiting block 443. The limiting seat 441 is arranged on the translation mechanism 41 and is located on one side of the lifting rail 422. The limiting plate 442 is arranged on the chip grabbing mechanism 43. The limiting plate 442 moves with the chip grabbing mechanism 43 to approach or move away from the limiting seat 441. When the lower end of the chip grabbing mechanism 43 abuts against the test assembly 31, the limiting seat 441 is fitted with the limiting plate 442. The limiting block 443 is detachably arranged on the limiting seat 441. The thickness of the limiting block 443 is consistent with the thickness of the chip to be tested. The limiting plate 442 falls and contacts the limiting block 443.

[0043] Reference Figures 1 to 5 The limiting seat 441 is provided with a connecting groove 441a. The limiting block 443 is provided with a connecting protrusion 443a. The connecting protrusion 443a can be inserted into the connecting groove 441a.

[0044] It can be understood that the connection groove 441a and the connection protrusion 443a cooperate to achieve a detachable connection between the limiting seat 441 and the limiting block 443, which is convenient to use and disassemble.

[0045] It is worth noting that, in some other embodiments of the present invention, when the thickness of the chip to be tested changes, the limit block 443 of the corresponding thickness can be replaced to achieve the maximum stroke control of the chip grabbing mechanism 43.

[0046] Reference Figures 1 to 5 The translation mechanism 41 includes a first translation rail 411, a translation truss 412 and a second translation rail 413. The first translation rail 411 is arranged on both sides of the frame 10. The translation truss 412 is slidably arranged on the first translation rail 411 and is located above the test mechanism 30. The second translation rail 413 is arranged on the translation truss 412. A plurality of chip grabbing mechanisms 43 are slidably arranged on the second translation rail 413. The length directions of the first translation rail 411 and the second translation rail 413 are perpendicular to each other. The translation slide 421 is slidably arranged on the second translation rail 413.

[0047] Reference Figures 1 to 5 The chip storage mechanism 20 includes a plurality of tray racks 21, a slide rail rack 22, a chip transfer and grabbing device 23, and a chip conveying mechanism 24. The plurality of tray racks 21 are arranged on the rack 10. The slide rail rack 22 is arranged on the rack 10 and is located above the tray rack 21. The chip transfer and grabbing device 23 is slidably arranged on the slide rail rack 22. The chip conveying mechanism 24 is arranged on the rack 10. The chip conveying mechanism 24 can convey the chip to one side of the testing mechanism 30.

[0048] It is worth noting that the tray rack 21 can accommodate several trays, and several chips are placed in the trays. The transfer and grasping device 23 can take out the chips to be tested from the trays and place them in the chip conveying mechanism 24, and can also take out the chips after the test from the chip conveying mechanism 24 and place them in the discharge tray.

[0049] It is worth noting that in the embodiment of the present invention, the chip conveying mechanism 24 conveys each chip individually, and the spacing between the chips can be adjusted when conveying each chip to make it conform to the spacing between the test position and the suction nozzle 433c. The implementation method can be that the conveying mechanism of each chip is connected to a lead screw individually, and the lead screws are driven to rotate separately by different power mechanisms to achieve separate control.

[0050] Reference Figures 1 to 5 The test mechanism 30 further includes a chip in place detection component 32. The chip in place detection component 32 includes a chip sensor 321 and an alarm light 322. The chip sensor 321 is disposed on the test bench 311. The chip sensor 321 can detect whether the chip is placed on the test position. The alarm light 322 is disposed on the test bench 311. When the chip sensor 321 detects that the chip is not placed on the test position, the alarm light 322 flashes.

[0051] It is understandable that when the chip is not placed properly, or the chip is not captured, resulting in no chip at the test position, the chip sensor 321 can detect and send an alarm to the staff.

[0052] A chip testing method uses a chip testing system, including the following steps: first, the lifting mechanism 42 is debugged, and the maximum stroke of the lifting mechanism 42 is manually adjusted so that the limit plate 442 and the limit seat 441 are in contact with each other, and the suction nozzle 433c is just in contact with the test position. Then, a limit block 443 with the same thickness as the chip to be tested is placed on the limit seat 441. Then the equipment is started, the chip transfer and grasping device 23 places the chip to be tested in the chip conveying mechanism 24, and the loading mechanism 40 takes the chip to be tested from the chip conveying mechanism 24 and places it on the test position for testing. After the test is completed, the loading mechanism 40 puts the tested chip back into the chip conveying mechanism 24, the chip conveying mechanism 24 conveys the chip back to one side of the chip transfer and grasping device 23, and the chip transfer and grasping device 23 places the tested chip in the tray rack 21.

[0053] Each wash lamp of the above-mentioned embodiment 4 Technical features can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] Of course, the present invention is not limited to the above-mentioned embodiments, and those skilled in the art may make equivalent modifications or substitutions without violating the spirit of the present invention, and these equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A chip testing system, characterized in that: include: Rack (10); A chip storage mechanism (20), the chip storage mechanism (20) being arranged on the rack (10), and the chip storage mechanism (20) being used to accommodate chips; A testing mechanism (30), the testing mechanism (30) being arranged on the rack (10), the testing mechanism comprising a plurality of testing components (31), the testing components (31) comprising a testing table (311), a testing board support (312), and a plurality of testing boards (313), the testing table (311) being arranged on the rack (10), the testing board support (312) being arranged on the testing table (311), a plurality of the testing boards (313) being evenly arranged on the testing board support (312), and the testing board (313) being provided with a testing position for accommodating a chip to be tested; a loading mechanism (40), the loading mechanism (40) being movably disposed on the frame (10), the loading mechanism (40) being configured to grab materials in the chip storage mechanism (20) and place them in the test assembly (31); The loading mechanism (40) comprises a translation mechanism (41), a lifting mechanism (42), a plurality of chip grabbing mechanisms (43) and a limiting mechanism (44); the plurality of chip grabbing mechanisms (43) are arranged on the lifting mechanism (42); the lifting mechanism (42) is arranged on the translation mechanism (41); the translation mechanism (41) is capable of driving the chip grabbing mechanism (43) to move in a horizontal plane; the lifting mechanism (42) is capable of driving the chip grabbing mechanism (43) to rise or fall; the limiting mechanism (44) is arranged on the lifting mechanism (42); the limiting mechanism (44) is capable of limiting the maximum displacement of the chip grabbing mechanism (43) to prevent the chip grabbing mechanism (43) from crushing the chip.

2. A chip testing system according to claim 1, characterized in that: The lifting mechanism (42) comprises a translation slide (421), a lifting rail (422) and a lifting cylinder (423); the translation slide (421) is slidably arranged on the translation mechanism (41); the lifting rail (422) is arranged on the translation slide (421); the lifting cylinder (423) is arranged at one end of the lifting rail (422); and the chip grabbing mechanism (43) is slidably arranged on the lifting rail (422) and connected to the output end of the lifting cylinder (423).

3. A chip testing system according to claim 2, characterized in that: The chip grabbing mechanism (43) comprises a mounting block (431), a mounting plate (432) and a plurality of negative pressure grabbers (433); the mounting block (431) is slidably arranged on the lifting rail (422) and connected to the output end of the lifting cylinder (423); the mounting plate (432) is arranged on the mounting block (431); and the plurality of negative pressure grabbers (433) are arranged on the mounting plate (432).

4. A chip testing system according to claim 3, characterized in that: The negative pressure grabber (433) comprises a mounting portion (433a), a negative pressure connecting tube (433b) and a suction nozzle (433c), wherein the mounting portion (433a) is arranged on the mounting plate (432), the negative pressure connecting tube (433b) is arranged at one end of the mounting portion (433a), the suction nozzle (433c) is arranged at the other end of the mounting portion (433a), and the other end of the negative pressure connecting tube (433b) is connected to a negative pressure generating device.

5. A chip testing system according to claim 4, characterized in that: The limiting mechanism (44) comprises a limiting seat (441), a limiting plate (442) and a limiting block (443); the limiting seat (441) is arranged on the translation mechanism (41) and is located on one side of the lifting rail (422); the limiting plate (442) is arranged on the chip grabbing mechanism (43); the limiting plate (442) moves with the chip grabbing mechanism (43) to approach or move away from the limiting seat (441); when the lower end of the chip grabbing mechanism (43) abuts against the test assembly (31), the limiting seat (441) and the limiting plate (442) are in contact; the limiting block (443) is detachably arranged on the limiting seat (441); the thickness of the limiting block (443) is consistent with the thickness of the chip to be tested; the limiting plate (442) falls and contacts the limiting block (443).

6. A chip testing system according to claim 5, characterized in that: The limiting seat (441) is provided with a connecting groove (441a), and the limiting block (443) is provided with a connecting protrusion (443a), and the connecting protrusion (443a) can be inserted into the connecting groove (441a).

7. A chip testing system according to claim 5, characterized in that: The translation mechanism (41) comprises a first translation rail (411), a translation truss (412) and a second translation rail (413); the first translation rail (411) is arranged on both sides of the frame (10); the translation truss (412) is slidably arranged on the first translation rail (411) and is located above the testing mechanism (30); the second translation rail (413) is arranged on the translation truss (412); a plurality of chip grabbing mechanisms (43) are slidably arranged on the second translation rail (413); the length directions of the first translation rail (411) and the second translation rail (413) are perpendicular to each other; and the translation slide plate (421) is slidably arranged on the second translation rail (413).

8. A chip testing system according to claim 1, characterized in that: The chip storage mechanism (20) comprises a plurality of tray racks (21), a slide rail rack (22), a chip transfer and grabbing device (23) and a chip conveying mechanism (24); the plurality of tray racks (21) are arranged on the rack (10); the slide rail rack (22) is arranged on the rack (10) and is located above the tray rack (21); the chip transfer and grabbing device (23) is slidably arranged on the slide rail rack (22); the chip conveying mechanism (24) is arranged on the rack (10); and the chip conveying mechanism (24) is capable of conveying chips to one side of the testing mechanism (30).

9. A chip testing system according to claim 1, characterized in that: The testing mechanism (30) further comprises a chip in-place detection component (32), the chip in-place detection component (32) comprising a chip sensor (321) and an alarm light (322), the chip sensor (321) being arranged on the testing table (311), the chip sensor (321) being capable of detecting whether a chip is placed on a testing position, the alarm light (322) being arranged on the testing table (311), and when the chip sensor (321) detects that no chip is placed on the testing position, the alarm light (322) flashes.

10. A chip testing method, using a chip testing system according to any one of claims 1 to 9, characterized in that: The following steps are involved: First, debug the lifting mechanism and manually adjust the maximum stroke of the lifting mechanism so that the limit plate and the limit seat are in contact with the test position at the same time; then place a limit block with the same thickness as the chip to be tested on the limit seat, and then start the equipment. The chip transfer and grasping device places the chip to be tested in the chip conveying mechanism, and the loading mechanism takes the chip to be tested from the chip conveying mechanism and places it on the test position for testing. After the test is completed, the loading mechanism puts the tested chip back into the chip conveying mechanism, and the chip conveying mechanism conveys the chip back to one side of the chip transfer and grasping device, and the chip transfer and grasping device places the tested chip in the tray rack.

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