A multi-channel chip packaging test method and system

Abstract

The present invention discloses a multi-channel chip packaging test method, which includes the following specific steps: establishing a data set; obtaining the operation data of multi-channel chips of the same model in different circuits; data preprocessing; performing data cleaning and normalization processing on the collected original operation data; data statistics and analysis; performing statistical analysis on the preprocessed data; establishing a prediction model; establishing a feature recognition model based on the convolutional neural network CNN; obtaining the optimal model through iterative training; verifying the model; using the model number of the chip and the type of the circuit where it is located as inputs, and using the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value; performing self-testing using the predicted pseudo-random test vector algorithm and the seed value; summarizing the test results to verify the prediction accuracy of the model; using this solution can greatly improve the accuracy and test efficiency of self-testing, and is beneficial to discovering chip flaws and potential defects as early as possible.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-channel chip testing, and particularly to a multi-channel chip packaging and testing method and system. Background Art

[0002] A multichannel chip is an integrated circuit chip with multiple independent channels, used for processing and transmitting multiple signals or data streams; each channel of the multichannel chip can independently process signals and data; common multichannel chips such as A / D conversion chips, multi-channel RFID chips, multi-channel microcontrollers MCU, etc.; the application scope of multichannel chips is also very wide, for example, in the communication field, multi-channel RFID chips in the Internet of Things communication can realize the simultaneous identification and data processing of multiple tags to improve the communication rate and capacity. In the audio and video processing field, a multi-channel voltage gain chip can simultaneously process multiple audio and video signals, improve the voltage level of the audio signal, enhance the anti-interference ability of the signal, and improve the signal-to-noise ratio of the system; realize the synchronization and encoding of audio and video signals; in medical instruments, multi-channel chips are used to collect and process physiological signals such as electrocardiograms and electroencephalograms. These chips can provide high-precision and low-noise signal amplification and conversion, which helps doctors make accurate diagnoses. In the field of industrial automation, multi-channel chips are used to monitor and control multiple sensors and actuators to achieve the stable operation of an automated production line. For example, a multi-channel half-bridge drive chip can drive multiple DC motors, relays and other actuators to achieve precise control of automated equipment.

[0003] After the chip packaging is completed, it needs to be tested, and some chips need to be tested or retested at the system level or circuit board level; some chips need to be tested at any time during their entire life cycle; for example, chips related to autonomous driving and the medical field; for example, a heart pacemaker chip; to meet the needs of the full-cycle testing of the above chips, a LogicBIST module is usually embedded during the research and development and design of the chip for testing;

[0004] LogicBIST is based on the Scan-based structure, inserts BIST logic inside the chip to generate pseudo-random test vectors, and then uses these pseudo-random test vectors for self-testing. The function of its hardware circuit structure is to generate test data, input it into the circuit under test, collect the output response, and verify whether the output result is correct. This workflow is controlled by a built-in self-test controller. Similar to the ATPG (Automatic Test Pattern Generation) process, the fault coverage rate can be used to evaluate the effectiveness of the built-in self-test.

[0005] Another function of LogicBIST is to detect potential defects. For example, a metal wire connecting two vias in a chip has a notch during the etching process. It does not malfunction during early use, and the chip can also pass the ATE test when it leaves the factory. However, as the usage time increases, the metal wire breaks after a period of electromigration. At this time, the chip operation will have a fault, and this defect is a potential defect. In the prior art, LogicBIST is classified according to the test time: on-line BIST and off-line BIST; here, on-line and off-line mean offline and online. Offline test: It means that when the BIST test is performed, the chip does not work, and it is suitable for the case where the entire test process takes a short time. Online test: It means that when the BIST test is performed, the chip is still working; therefore, on-line BIST allows operations to be performed within the circuit under test, and it is necessary to find time gaps to test the chip, which results in a long test cycle; for some non-stop chips such as the aforementioned pacemaker chip, how to ensure the accuracy of the test results while improving the efficiency of the online test is beneficial to detecting potential defects in the chip earlier and consuming less power. Summary of the Invention

[0006] In view of the problems existing in the above background, the present invention proposes a multi-channel chip package testing method and system.

[0007] Therefore, the problem to be solved by the present invention is how to improve the efficiency of online testing and detect potential defects in the chip earlier.

[0008] To solve the above technical problems, the present invention provides the following technical solutions:

[0009] The first aspect of the present invention provides a multi-channel chip package testing method, including the following specific steps:

[0010] S1, establish a data set; obtain the operation data of multi-channel chips of the same model in different circuits;

[0011] In step S1, a data set is established according to the model of the multi-channel chip, and the operation data of chips of the same model are stored in the same data set; according to the application of the chips in different circuits in the data set, the data set is separated into multiple subsets; the multi-channel chips collected include normal chips and faulty chips; while collecting the operation data, the data manual information of the chips is also collected, specifically including the model of the chip, pin interface information, electrical characteristic parameters, timing control diagram, and package information.

[0012] The chip operation data collected in step S1 includes the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip, fault codes corresponding to the faults, production batch information, the pseudo-random test vector algorithm used when detecting the fault, and the seed value.

[0013] S2, data preprocessing; perform data cleaning and normalization on the collected original operation data;

[0014] The collected original operation data first needs to remove outliers and duplicates in the data, and then process the data in the same unit; in addition, it can also be achieved by calculating statistics such as the mean and standard deviation of the data to convert the original data into standard scores or Z-scores.

[0015] S3, data statistics and analysis; perform statistical analysis on the preprocessed data, and establish data subsets for the data that passes the test and the data that fails the test respectively;

[0016] In step S3, classify the preprocessed data;

[0017] Establish data subsets for the data that passes the test and the data that fails the test respectively; reclassify the data in the test-pass subset and the test-fail subset according to normal chips and faulty chips; generate new data subsets;

[0018] S4, data annotation; perform annotation on the data in the test-pass data subset and the test-fail data subset respectively;

[0019] In step S4, use manual annotation to perform feature annotation on the faulty chip subset and the test-fail subset in the test-pass subset.

[0020] S5, establishment of a prediction model; establish a feature recognition model based on the convolutional neural network CNN; set training parameters: set the initial learning rate, and adopt the learning rate decay algorithm; obtain the optimal model through iterative training; in step S5, use the annotated dataset as the model input to train the feature recognition model of the convolutional neural network CNN; the architecture of the CNN model in step S5 includes an input layer, a convolutional layer, a pooling layer, and a fully connected layer; use the predicted pseudo-random test vector algorithm and seed value to perform self-testing using LogicBIST; summarize the test results to verify the prediction accuracy of the model. Among the training parameters, the initial learning rate is set to 0.01; use the exponential decay algorithm to iteratively optimize the model.

[0021] S6. Verification of the model: Using the model number of the chip and the type of the circuit where it is located as inputs, and using the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value. The results output by the model are: the predicted pseudo-random test vector algorithm and the predicted seed value; using the predicted pseudo-random test vector algorithm and the seed value, using a random chip, and performing self-test through the LogicBIST built in the chip; verifying whether the chip failure can be identified through the test results; counting the qualified rate, and repeating steps S5 - S6 until the qualified rate meets the expectation.

[0022] The second invention of the present invention provides a multi-channel chip package test system, which uses the above method to test the chip, including a data acquisition module, a data processing module, a human-computer interaction module, and a chip test platform.

[0023] The data acquisition module is used to acquire the operating data required for chip testing; including the chip model, the circuit platform on which it operates, the input rated current, rated voltage, the frequency of the input signal, the common failure types of this type of chip and the corresponding fault codes, the pseudo-random test vector algorithm used when detecting this fault, and the seed value information.

[0024] The data processing module is used to preprocess, statistically analyze the data collected by the data acquisition module, and calculate the established model.

[0025] The human-computer interaction module includes a data display interface, an artificial annotation module, and a modification module; the data display interface displays the preprocessed data in the form of charts; the artificial annotation module is used to annotate the data; the modification module is used to modify the parameters of the prediction model.

[0026] The chip test platform is used to provide a specified circuit system for the chip to carry out a self-test environment.

[0027] Preferably, the chip test platform is provided with several test stations to test multiple chips simultaneously.

[0028] The third aspect of the present invention provides a computer device, including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the above multi-channel chip package test method are implemented.

[0029] The fourth aspect of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above multi-channel chip package test method are implemented.

[0030] The beneficial effects of the present invention are as follows: By collecting a certain amount of chip operation data, the chips are first systematically classified; the normal chips and faulty chips are determined by manual annotation, and then conventional pseudo-random test vectors are used for self-testing; eigenvalue can be extracted by analyzing the test results; the pseudo-random test vectors with high judgment accuracy and the corresponding seed values are selected as the preferred test content for testing; for chips of the same model and batch, the possibility of having the same defects is relatively high. Therefore, for some common chips that can only be tested online during operation, using this solution can greatly improve the accuracy and efficiency of self-testing, which is conducive to detecting the defects and potential deficiencies of the chips as early as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is a flowchart of a multi-channel chip packaging test method.

[0033] Figure 2 It is a structural diagram of a multi-channel chip packaging test system. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings of the specification.

[0035] In the following description, many specific details are set forth to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0036] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that can be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that excludes other embodiments.

[0037] Embodiment 1

[0038] This embodiment provides a multi-channel chip packaging test method, including the following specific steps:

[0039] S1. Establish a dataset; obtain the operation data of multi-channel chips of the same model in different circuits;

[0040] In step S1, a dataset is established according to the model of the multi-channel chips, and the operation data of chips of the same model are stored in the same dataset; in the dataset, according to the applications of the chips in different circuits, the dataset is separated to form multiple subsets; the collected multi-channel chips include normal chips and faulty chips; while collecting the operation data, the data manual information of the chips is also collected, specifically including the model of the chips, pin interface information, electrical characteristic parameters, timing control diagrams, and packaging information.

[0041] The chip operation data collected in step S1 include the input rated current, rated voltage, frequency of the input signal, common fault types of this model of chips, fault codes corresponding to the faults, production batch information, pseudo-random test vector algorithm used when detecting the fault, and seed values.

[0042] S2. Data preprocessing; perform data cleaning and normalization on the collected original operation data;

[0043] The collected original operation data first need to remove the outliers and duplicates in the data, and then process the data in the same unit; in addition, it can also be achieved by calculating statistics such as the average value and standard deviation of the data to convert the original data into standard scores or Z-scores.

[0044] S3. Data statistics and analysis; perform statistical analysis on the preprocessed data, and establish data subsets for the data that pass the test and the data that fail the test respectively;

[0045] In step S3, the preprocessed data are classified;

[0046] Data subsets are established for the data that pass the test and the data that fail the test respectively; the data in the subset that passes the test and the subset that fails the test are re-divided according to normal chips and faulty chips; new data subsets are generated;

[0047] S4. Data annotation; perform annotation on the data in the data subset that passes the test and the data subset that fails the test respectively;

[0048] In step S4, the feature annotation is performed on the faulty chip subset and the subset that fails the test in the data subset that passes the test by means of manual annotation.

[0049] S5. Establishment of the prediction model: Establish a feature recognition model based on the convolutional neural network (CNN); Set training parameters: Set the initial learning rate and adopt the learning rate decay algorithm; Obtain the optimal model through iterative training; In step S5, use the labeled dataset as the model input to train the feature recognition model of the convolutional neural network (CNN); The architecture of the CNN model in step S5 includes an input layer, a convolutional layer, a pooling layer, and a fully connected layer.

[0050] S6. Verification of the model: Use the model number of the chip and the type of the circuit where it is located as the input, and use the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value; Use the predicted pseudo-random test vector algorithm and seed value to perform self-testing using LogicBIST; Summarize the test results to verify the prediction accuracy of the model. Among the training parameters, the initial learning rate is set to 0.01; Use the exponential decay algorithm to iteratively optimize the model. In step S6, the results output by the model are: the predicted pseudo-random test vector algorithm and the predicted seed value; Use the predicted pseudo-random test vector algorithm and seed value, and use a random chip to perform self-testing through the LogicBIST built in the chip; Verify whether the chip failure can be identified through the test results; Count the pass rate, and repeat steps S5 - S6 until the pass rate meets the expectation.

[0051] The following uses a specific case to introduce the steps of this solution in detail:

[0052] The ADS1113 chip is a high-precision, low-power 16-bit analog-to-digital converter (ADC) chip; Its basic information is as follows:

[0053] Resolution: 16 bits, providing high-precision analog-to-digital conversion.

[0054] Power consumption: In the continuous conversion mode, the power consumption is only 150 μA; In the single-trigger mode, the device automatically powers off after one conversion, thus significantly reducing the power consumption during the idle period.

[0055] Package: Adopt ultra-small leadless QFN-10 package or MSOP-10 package, with a size of 2mm x 1.5mm x 0.4mm, suitable for applications with limited space.

[0056] Operating power supply: Wide power supply voltage range, from 2.0V to 5.5V, adapting to different power supply environments.

[0057] Data rate: Programmable data rate, from 8 SPS (samples per second) to 860 SPS, which can be adjusted according to application requirements.

[0058] On-board reference and oscillator: Built-in low-drift voltage reference and an oscillator, enabling stable analog-to-digital conversion without external components.

[0059] I2C interface: Compatible with the I2C serial interface, supports 4 I2C slave address selections, and is convenient for communicating with master chips such as microcontrollers.

[0060] Single-ended / differential input: Although the specific input configuration of the ADS1113 may vary depending on the model or package, generally such chips support single-ended or differential input methods to adapt to different signal acquisition requirements.

[0061] Application fields: The ADS1113 chip is widely used in portable instruments, consumer goods, battery monitoring, temperature measurement, factory automation, and process control. Especially in medical devices, its high precision and low power consumption make it an ideal choice.

[0062] Advantages and features: Features such as ultra-small package, wide power supply range, low current consumption, programmable data rate, and internal reference and oscillator make the ADS1113 chip perform excellently in sensor measurement applications with power and space constraints.

[0063] Based on the above advantages, the ADS1113 chip can also be applied in common devices such as ventilators and cardiac pacemakers; during the operation of the device, online detection of the chip is required for safety reasons; the traditional solution is to use the pseudo-random test vector generation ability of LogicBIST to generate independent test vectors for each channel. These test vectors should cover various possible inputs and states of the channel to ensure the comprehensiveness of the test; pseudo-random test vectors are generally generated through specific algorithms or circuits, commonly including linear feedback shift registers (LFSRs), pseudo-random number generators (PRGs), and pseudo-random number generators combined with memories;

[0064] Among them, the LFSR is a simple and efficient pseudo-random number generation algorithm, and its principle is to generate a pseudo-random number sequence through a feedback loop composed of a shift register and an exclusive OR gate.

[0065] Specifically: Define a shift register, and its length determines the period of the pseudo-random number sequence.

[0066] According to a specific feedback function, perform an exclusive OR operation on some bits of the shift register, and use the result as the new input bit. In each clock cycle, the value of the shift register is shifted one bit to the left, and the new input bit is added to the least significant bit. With a small hardware overhead, a long pseudo-random number sequence can be generated;

[0067] The PRG is a more complex random number generation algorithm, which uses more logic gates and state variables to implement.

[0068] Specifically:

[0069] Define a state variable to store the current state.

[0070] In each clock cycle, update the value of the state variable according to a specific algorithm.

[0071] Output the value of the state variable as a pseudo-random number.

[0072] This article takes a pseudo-random number generator combined with a memory as an example for introduction; different from the aforementioned PRG, after combining with a memory, the memory can be used to store the seed of the pseudo-random generator; by the control unit, the phase shift or control of the pseudo-random test sequence can be realized, and the generation of the pseudo-random test sequence can be flexibly controlled to make it suitable for application scenarios that require complex test sequences.

[0073] The specific steps are as follows:

[0074] S1. Establish a data set; obtain the operation data of the ADS1113 chip in different circuits; for the different functions of the ADC chip in different circuits, several basic circuit models are preset, and the common ones include a bridge circuit model, an amplification circuit model, an interface circuit model, a current-voltage conversion model, and a filter circuit model; among them, the bridge circuit is used to convert the changes in physical quantities such as resistance, capacitance, and inductance of the sensor into changes in voltage or current, which is convenient for the ADC chip to capture the analog signal; for example, resistive sensors (thermistors, potentiometers), capacitive sensors, and inductive sensors;

[0075] The amplification circuit is used to amplify the output signal of the sensor, thereby improving the measurement accuracy and sensitivity; the amplification circuit is also a relatively common application scenario.

[0076] The interface circuit is used to convert the sensor output with high impedance into low impedance when the sensor output is of high impedance, so that the detection circuit can accurately obtain the sensor signal.

[0077] The current-voltage conversion model is also a relatively common application scenario, mainly used to convert some sensors with current signal output into voltage signal for output.

[0078] The filter circuit model is used to remove the noise and interference components in the sensor output signal to improve the signal purity and measurement accuracy. The foregoing part only gives an exemplary case, and the specific model type can be further refined according to the application scenario. For example, the amplification circuit can be set as a differential amplification circuit or other amplification circuits with high usage frequency.

[0079] Establish a data set X based on the chip model i , where i is the number of chips of the same model; X i {X 1 , X 2 ……X n};

[0080] In the dataset, according to the applications of the chips in different circuits, the dataset is separated to form multiple subsets; X i {X i,1 , X i,2 …… X i,n};

[0081] For example, 10 ADS1113 chips are actually tested. The dataset corresponding to chip No. 1 is denoted as X 1 , and the dataset corresponding to chip No. 10 is named X 10 , and the corresponding subset is denoted as X 10,n ; n is the number of different types of circuit models; then, the bridge circuit model X 10,1 , the amplifier circuit model X 10,2 , the interface circuit model X 10,3 , the current-voltage conversion model X 10,4 , the filter circuit model X 10,5 ;

[0082] The multi-channel chips collected include normal chips and faulty chips; while collecting the operation data, the data manual information of the chips is also collected, specifically including the chip model, pin interface information, electrical characteristic parameters, timing control diagram, and package information. The collected chip operation data includes the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip, the fault codes corresponding to the faults, the pseudo-random test vector algorithm used when detecting the fault, and the seed value; for the collected data manual information and chip operation data, two separate vectors are generated and denoted as A and B respectively; each collected data is written into the vector in a fixed order and finally combined into two high-dimensional vectors:

[0083] A(a 1 , a 2 …… a m )

[0084] B(b 1 , b 2 , …… b k )

[0085] In the above formula, A is the data manual vector, a 1 , a 2 …… a m are the parameters in the data manual, and m is the number of parameters; B is the chip operation vector, b 1 , b 2 , …… b k are the parameters of the chip operation data, and k is the number of parameters.

[0086] S2, Data preprocessing; perform data cleaning and normalization on the collected original operation data;

[0087] The collected original operation data first needs to remove outliers and duplicates in the data, and then process the data in the same unit; in addition, it can also be achieved by converting the original data into standard scores or Z - scores by calculating statistics such as the mean and standard deviation of the data.

[0088] S3, Data statistics and analysis; perform statistical analysis on the pre - processed data, and establish data subsets for the data that passes the test and the data that fails the test respectively;

[0089] In step S3, classify the pre - processed data;

[0090] Establish data subsets for the data that passes the test and the data that fails the test respectively; among them, T t is the data subset of normal chips in the test - passed data subset, and T f is the data subset of failed - test chips; re - divide the data in the test - passed subset and the failed - test subset according to normal chips and faulty chips; generate new data subsets.

[0091] Among the pre - prepared chips, there are some normal chips that have passed ATE testing and some chips with defects that have failed the test; select as many chips with various failure reasons as possible to obtain the operation data of chips under different failure conditions; divide the chips according to their functionality after testing; among them, T t,t represents the data subset of normal chips in the test - passed data subset, and T t,f represents the data subset of faulty chips in the test - passed data subset; T f,t represents the data subset of normal chips in the failed - test data subset, and T f,f represents the data subset of faulty chips in the failed - test data subset.

[0092] S4, Data annotation; annotate the data in the test - passed data subset T t and the failed - test data subset T f respectively; use the manual annotation method to perform feature annotation on the faulty chip subset T t,f in the test - passed subset and the failed - test subset T t ; by analyzing and processing the test data obtained in steps S3 and S4, the influence of different pseudo - random test vector algorithms and seed values on the test results can be obtained;

[0093] a. In the faulty chip subset T t,fIf there is a fault in the middle chip, but no problem is found in the self-test using the algorithm and the seed value, then there are defects in this algorithm and the corresponding seed value, and this kind of error situation should be excluded in the subsequent processing;

[0094] b. For the test failure subset T t When labeling, the normal chip data subset T in the test failure data subset f,t means that the normal chip is determined to be faulty due to problems with the algorithm and the seed value; for such situations, the test weights of this algorithm and the corresponding seed value should be reduced;

[0095] c. For the faulty chip data subset T in the test failure data subset f,f the corresponding algorithm and seed value should be weighted up and stored in the memory; when testing, give priority to using this type of algorithm and seed value for testing to improve the test efficiency and reduce power consumption; the sum of the total weights set in the two cases of b and c is 1.

[0096] S5. Establishment of the prediction model; establish a feature recognition model based on the convolutional neural network CNN; set training parameters: set the initial learning rate and adopt the learning rate decay algorithm; obtain the optimal model through iterative training; in step S5, use the labeled data set as the model input to train the feature recognition model of the convolutional neural network CNN; the architecture of the CNN model in step S5 includes an input layer, a convolutional layer, a pooling layer, and a fully connected layer. Use the predicted pseudo-random test vector algorithm and seed value to perform self-test using LogicBIST; summarize the test results to verify the prediction accuracy of the model. In the training parameters, the initial learning rate is set to 0.01; use the exponential decay algorithm to iteratively optimize the model.

[0097] For the same pseudo-random test vector algorithm, its randomly generated test vectors. In this embodiment, further, it is preferable to use the starting value and the seed value of the pseudo-random test vector algorithm that can preferably detect faults as inputs for testing; without changing the calculation rules of the pseudo-random test vector algorithm, the self-test efficiency and the fault detection rate can be improved for the same type of chip and the same type of fault.

[0098] S6. Verification of the model; use the model number of the chip and the type of the circuit where it is located as inputs, and use the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value;

[0099] The results output by the model are: the predicted pseudo-random test vector algorithm and the predicted seed value; using the predicted pseudo-random test vector algorithm and the seed value, with a random chip, perform self-testing through the LogicBIST built into the chip; verify whether the chip's faults can be identified through the test results; count the pass rate, and repeat steps S5 - S6 until the pass rate meets the expectation.

[0100] In this embodiment, chips of the same batch use the same processing technology and processing steps. When a specific defect exists in one chip, the probability of the same defect occurring in the remaining chips is relatively high; therefore, in practical applications, it can be considered to store in the memory the type of pseudo-random test vector algorithm, the seed value, and the starting value used for self-testing of the faulty chips; give priority to self-testing to reduce the detection volume and improve the detection efficiency. In general multi-channel chips, different channels work independently. When detecting several channels with the same function, when the detection result is qualified, replace with another test vector and seed value to test the remaining channels with the same function; if the detection result is unqualified, give priority to using the same test vector and seed value to test the remaining channels with the same function. For example, D1, D2, D3, and D4 are parallel channels with the same function on the chip; when using the first test vector and the first seed value to detect D1 and the test result is qualified, use the second test vector and the seed value to detect D2, and so on, using more test vectors and seed values for testing to quickly discover possible defects; when using the first test vector and the first seed value to detect D1 and the test result is unqualified, give priority to using the first test vector and the first seed value to test D2, D3, and D4 to quickly discover possible defects.

[0101] Embodiment 2

[0102] This embodiment provides a multi-channel chip packaging test system, which uses the method in Embodiment 1 to test the chip, including a data acquisition module, a data processing module, a human-computer interaction module, and a chip test platform;

[0103] The data acquisition module is used to collect the operation data required for chip testing; including the chip model, the circuit platform it operates on, as well as the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip, the fault codes corresponding to the faults, the pseudo-random test vector algorithm used when detecting the fault, and the seed value information;

[0104] The data processing module is used to preprocess, statistically analyze, and calculate the established model for the data collected by the data acquisition module;

[0105] The human-computer interaction module includes a data display interface, a manual annotation module, and a modification module; the data display interface displays the preprocessed data in the form of charts; the manual annotation module is used to annotate the data; the modification module is used to modify the parameters of the prediction model;

[0106] The chip test platform is used to provide a specified circuit system for the chip to perform a self-test loading environment. The chip test platform sets several test stations to test multiple chips simultaneously. In this embodiment, the chip test platform can be pre-set with common circuit models including a bridge circuit model, an amplifier circuit model, an interface circuit model, a current-voltage conversion model, and a filter circuit model; and provides multiple test stations; so that the chip can quickly perform system-level or circuit board-level tests; as a further solution, the chip test platform meets the ATE test requirements.

[0107] In this embodiment, data is obtained by testing several chips, providing a data set and a validation set for the training of the prediction model; after the prediction model is trained, the predicted pseudo-random test vectors and seed values can be output through the model, and written into the memory of the chip through the communication module. When the chip is running, it preferentially uses the predicted pseudo-random test vectors and seed values for self-testing; correspondingly, when the chip detects defects or faults during self-testing, it can upload to the test system through the communication module for subsequent processing.

[0108] Embodiment 3

[0109] This embodiment also provides a computer device, which is applicable to the steps of the multi-channel chip packaging test method, including a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the steps of the multi-channel chip packaging test method proposed in Embodiment 1.

[0110] The computer device can be a terminal. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner. The wireless manner can be achieved through WIFI, a carrier network, NFC (Near Field Communication), or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad set on the shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0111] Example 4

[0112] This embodiment also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the multi-channel chip package testing method described in Embodiment 1 are implemented.

[0113] The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM for short), electrically erasable programmable read-only memory (EEPROM for short), erasable programmable read-only memory (EPROM for short), programmable read-only memory (PROM for short), read-only memory (ROM for short), magnetic memory, flash memory, magnetic disk or optical disc.

[0114] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A multi-channel chip packaging test method, characterized in that: The specific steps include: S1, establish a data set; obtain the operating data of the same model multi-channel chip in different circuits; S2, data preprocessing: data cleaning and normalization of the collected original operation data; S3, data statistics and analysis; Perform statistical analysis on the preprocessed data and create data subsets for the data that passed the test and the data that failed the test; S4, data labeling: label the data in the test passing data subset and the test failing data subset respectively; S5, establishment of prediction model; establishment of feature recognition model based on convolutional neural network CNN; Set training parameters: set the initial learning rate and use the learning rate decay algorithm; obtain the optimal model through iterative training; S6, verification of the model; using the chip model and the type of circuit in which it is located as input, using the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value; using the predicted pseudo-random test vector algorithm and seed value to input LogicBIST for self-test; summarizing the test results to verify the prediction accuracy of the model; In step S1, a data set is established based on the model of the multi-channel chip, and the operation data of the chips of the same model are stored in the same data set; the data set is separated into multiple subsets according to the application of the chip in different circuits; the multi-channel chips collected include normal chips and faulty chips; The chip operation data collected in step S1 includes the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, the pseudo-random test vector algorithm used when detecting the fault, and the seed value; In step S5, the labeled data set is used as the model input to train the feature recognition model of the convolutional neural network CNN; the architecture of the CNN model in step S5 includes an input layer, a convolution layer, a pooling layer, and a fully connected layer. In the training parameters, the initial learning rate is set to 0.01; the exponential decay algorithm is used to iteratively optimize the model; Among them, in step S6, the results of the model output are: a predicted pseudo-random test vector algorithm and a predicted seed value; using the predicted pseudo-random test vector algorithm and seed value, using a random chip, and performing self-testing through the chip's built-in LogicBIST; verifying whether the chip fault can be identified through the test results; calculating the pass rate, and repeating steps S5-S6 until the pass rate meets expectations.

2. A multi-channel chip packaging test method according to claim 1, characterized in that: In step S3, the preprocessed data is classified; The data of the test passing data and the test failing data are respectively established into data subsets; the data in the test passing subset and the test failing subset are re-divided into normal chips and faulty chips; Generate new subsets of data.

3. A multi-channel chip packaging test method according to claim 1, characterized in that: In step S4, feature annotation is performed on the faulty chip subset in the test-passing subset and the test-failed chip subset by manual annotation.

4. A multi-channel chip packaging test system, using the method according to any one of claims 1 to 3 to test the chip, characterized in that: Including data acquisition module, data processing module, human-computer interaction module and chip testing platform; The data acquisition module is used to collect the operating data required for chip testing; including the chip model, the circuit platform on which it is running, the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, the pseudo-random test vector algorithm used when the fault is detected, and seed value information; The data processing module is used to pre-process, perform statistical analysis and calculate the established model on the data collected by the data acquisition module; The human-computer interaction module includes a data display interface, a manual annotation module, and a modification module; the data display interface displays the pre-processed data in the form of charts; The manual labeling module is used to label the data; the modification module is used to modify the parameters of the prediction model; The chip test platform is used to provide a designated circuit system as a self-testing environment for the chip.

5. A multi-channel chip packaging test system according to claim 4, characterized in that: The chip testing platform is equipped with several testing stations to test multiple chips at the same time.

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