DDIC power supply system and method for reducing DDIC power consumption

Abstract

The invention provides a DDIC power supply system and a method for reducing power consumption of a DDIC. The power supply system comprises an LDO unit, a digital circuit unit, a VDD unit, a VDDI unit and a judgment control unit. According to the invention, the whole machine working state is taken as the basis for opening and closing the LDO unit, compared with the prior art, the problem that the set value is too high or too low is avoided, and the power consumption is reduced. Furthermore, the output value of the LDO unit is dynamically adjusted according to the working state of the whole machine, and lower power consumption is obtained.

Description

Technical Field

[0001] The present application relates to the field of OLED display, and in particular to the technical field of reducing the power consumption of display driver chips. Background Art

[0002] In the current fiercely competitive OLED display field, including display screens for mid-to-high-end consumer products such as mobile phones, wearable devices, and handheld game consoles, low power consumption has become a major selling point that many businesses focus on promoting. The reason for this is quite intuitive. Low power consumption means less power consumption, so various consumer electronic products do not need to be charged frequently, which greatly improves the convenience of user use. In addition, power consumption is often accompanied by heat dissipation. If the power consumption is high, the product is prone to overheating during use. Low power consumption can effectively reduce heat generation, making the overheating phenomenon no longer obvious, thereby creating a more comfortable user experience for users.

[0003] At present, display driver chips (DDIC, display driveric) generally adopt 4powermode power supply method, and the motherboard directly provides all four power supplies required by DDIC, namely VDDI, VCI, AVDD and VDD.

[0004] However, in the actual application of 4powermode, there is a problem that cannot be ignored. When the external VDD power supply provided to the DDIC remains unchanged, if encountering certain special screen usage scenarios, the VDD current will increase sharply. Due to the wiring resistance between the motherboard and the DDIC, according to Ohm's law, when current passes through the resistance, it will inevitably produce a voltage drop. In this way, the VDD voltage that finally enters the DDIC is likely to be lower than the voltage required for the normal operation of its internal digital circuit, which will cause abnormalities in the internal circuit of the DDIC, and finally manifest as abnormal display. This is obviously a situation that neither product designers nor users want to see.

[0005] In order to solve the above technical problems, an internal compensation function is introduced on the basis of 4powermode, that is, the LDO unit is introduced. The specific principle is that when the external voltage is lower than a set value A, a working mode similar to 3powermode will be turned on, and the output value of the LDO unit (generally with 1.8V as input, and the expected output value input at the Vset end) is used to compensate for the insufficient VDD voltage entering the DDIC end due to the voltage drop. However, the set value A and the parameters of the LDO unit are fixed at the factory. Once they are set by the relevant application personnel in the assembly plant, the product cannot be changed after it is shipped to the user, unless the product is returned to the factory for reset. Setting the set value A and the parameters of the LDO unit too high or too low will lead to increased power consumption or abnormal working conditions. Therefore, how to reasonably set the above two parameters has become a key issue that needs to be solved urgently. Summary of the invention

[0006] The present application provides a DDIC power supply system and a method for reducing DDIC power consumption, which turns on / off an LDO unit according to the working state of the whole machine and dynamically adjusts the output value of the LDO unit.

[0007] The present application provides a DDIC power supply system, comprising: an LDO unit, a digital circuit unit, a VDD unit, a VDDI unit and a judgment control unit;

[0008] The LDO unit includes a Vset terminal and an enable terminal; one end of the LDO module is connected to the VDDI unit, and the other end is connected to the digital circuit;

[0009] The digital circuit unit includes a digital module, an SRAM module and a PHY module, one end of which is directly connected to the VDD unit;

[0010] A judgment control unit comprises a first end, a second end and a third end; the first end is connected to the interface unit and is used to judge the working state of the interface unit; the second end is connected to the enable end and is used to turn on or off the LDO unit according to the working state; the third end is connected to the Vset end of the LDO unit and is used to adjust the input value of the Vset end according to the working state;

[0011] A VDD unit is directly connected to the digital module, the SRAM module and the PHY module, and is used to provide a first voltage to the digital module, the SRAM module and the PHY module;

[0012] The VDDI module is used to provide a second voltage to the LDO module.

[0013] Furthermore, the first voltage is 1.2V.

[0014] Furthermore, the second voltage is 1.8V.

[0015] On the other hand, based on the above power supply system, the present application also provides a method for reducing DDIC power consumption, comprising the following steps:

[0016] Step 1: DDIC receives a frame of data transmitted by AP through the interface unit.

[0017] Step 2: Determine the working state of the interface unit and the reading state of the SRAM module according to the transmitted data, and adjust the parameters of the LDO unit.

[0018] Furthermore, step 2 is specifically as follows:

[0019] Step 2.1 determines the working state of the interface unit according to the transmitted data to control whether to turn on the LDO unit; if the interface state is in high-speed mode, turn on the LDO unit, input the first value to the Vset terminal, and jump to step 1; if the interface unit is in low-speed mode, jump to step 2.2;

[0020] Step 2.2, further determine whether it is necessary to read the SRAM module, if necessary, turn on the LDO unit, input the second value to the Vset terminal, and jump to step 1; if not, turn off the LDO unit and jump to step 1;

[0021] The first value is greater than the second value.

[0022] Furthermore, the first value is a higher level value.

[0023] Furthermore, the second value is a lower level value.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] (1) The present application uses the working state of the whole machine as the basis for turning on and off the LDO unit. Compared with the prior art, this avoids the problem of setting the value too high or too low and reduces power consumption.

[0026] (2) The present application further dynamically adjusts the output value of the LDO unit according to the working state of the whole machine, thereby achieving lower power consumption compared to the single output value of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 This is a schematic diagram of the principle of this embodiment;

[0029] Figure 2 A schematic diagram of the structure of the power supply system implemented in this embodiment;

[0030] Figure 3 FIG. 4 is a flow chart of the method for reducing DDIC power consumption according to the present embodiment. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] See also Figure 1 , the horizontal axis is the DDIC working state, which are state A, state B and state C respectively; the vertical axis is VDDD (i.e., the output value of the LDO unit 10). Figure 1 As shown, the lower limit to ensure the normal operation of DDIC is 0.99V. In practice, due to the existence of internal voltage drop, the voltage output to the VDD module of DDIC in each state is different (the voltage drop of state A is the largest, state B is the second, and state C is the smallest, showing a step distribution). Even in some states (such as state A and state B), it cannot meet the minimum 0.99V, that is, the normal operation of DDIC cannot be guaranteed. At this time, in order to ensure the normal operation of DDIC, the value required for internal compensation is also different (the compensation value required for state A is the largest, state B is the second, and state C does not require compensation, showing a step distribution). However, in the prior art, the internal compensation value has been set at the factory (that is, it is fixed after leaving the factory). When the compensation value meets state A, state B (the voltage provided is greater than the voltage provided after compensation in state A) and state C (no compensation is required to ensure the normal operation of DDIC) will generate power consumption waste. This implementation dynamically adjusts the compensation value for different states, so that the final voltage is slightly higher than 0.99V (under the condition of ensuring normal operation). Figure 1 In the figure, after compensation, it becomes a straight line, and the voltage values ​​provided by the three states are equal), thereby achieving the effect of saving power consumption.

[0033] Figure 2 FIG. 4 shows a schematic diagram of the structure of the DDIC power supply system of this embodiment. Figure 2 As shown, the power supply system includes an LDO unit 10 , a digital circuit unit 20 , a determination control unit 30 , a VDDI unit 40 , a VDD unit 50 and an interface unit 60 .

[0034] The LDO unit 10 includes a Vset terminal 101 and an enable terminal 102 ; the enable terminal 102 is used to control the on and off of the LDO unit 10 , and the value of the Vset terminal 101 is used to control the output value of the LDO unit 10 .

[0035] The digital circuit unit 20 includes a digital module, an SRAM module, and a PHY module.

[0036] The first end of the judgment control unit 30 is connected to the Vset end 101 for dynamically adjusting the output value of the LDO unit; the second end is connected to the enable end 102 for controlling the on and off of the LDO unit 10; the third end is connected to the interface unit 60 for obtaining the working status of the interface unit 60 and the reading status of the SRAM module.

[0037] The VDD unit 50 is connected to the digital circuit unit 20 and directly connected to the digital module, the SRAM module and the PHY module;

[0038] The VDDI unit 40 is connected to the LDO unit 10 and is used to provide an input voltage to the LDO unit 10 .

[0039] Optionally, the VDD unit provides a 1.2V voltage.

[0040] Optionally, the VDDI unit provides 1.8V voltage.

[0041] On the other hand, based on the above power supply system, the present application also provides a method for reducing DDIC power consumption, comprising the following steps:

[0042] Step 1: DDIC receives a frame of data transmitted by AP through the interface unit.

[0043] Step 2: Determine the working state of the interface unit and the reading state of the SRAM module according to the transmitted data, and adjust the parameters of the LDO unit.

[0044] Step 2 is as follows:

[0045] Step 2.1 determines the working state of the interface unit according to the transmitted data to control whether to turn on the LDO unit; if the interface state is in high-speed mode, turn on the LDO unit, input the first value to the Vset terminal, and jump to step 1; if the interface unit is in low-speed mode, jump to step 2.2;

[0046] Step 2.2, further determine whether it is necessary to read the SRAM module, if necessary, turn on the LDO unit, input the second value to the Vset terminal, and jump to step 1; if not, turn off the LDO unit and jump to step 1;

[0047] The first value is greater than the second value, the first value is a higher level value, and the second value is a lower level value.

[0048] Figure 3 The interface unit is a MIPI working timing diagram. Figure 3 As shown, in Vedio mode, a judgment mechanism is added at a fixed position after each frame of MIPI_VS to determine whether the MIPI data lane has a high-speed signal. If so, it means that the interface is transmitting data. At this time, VDD needs to consume a higher current, so a higher value needs to be compensated. When it is determined that the lane has entered the low-speed mode, it means that the interface has not moved. At this time, there is no need to consume a lot of electricity, so the compensation value is set small or turned off. When entering the display, the LDO unit 10 is turned off, or Vset is set to a smaller value.

[0049] Preferably, in no-refresh mode, if the source does not update data to the panel, the LDO unit 10 can be turned off. If an update is required, data needs to be read from the SRAM module, which will also consume power, but it is much smaller than the refresh frame, so Vset can be set smaller.

[0050] In summary, for devices with MIPI interface:

[0051] In Video mode, as shown in Table 1:

[0052] A) Screen off state (sleep in): At this time, the power consumption is the lowest and the LDO unit 10 is turned off;

[0053] B) After waking up, refresh frame (normal display): the LDO unit 10 is turned on for compensation, and inputs a first value to the Vset terminal 101, ie, sets a higher potential value.

[0054] C) After waking up, non-refresh frame (normal display): If the AP is not updating data, the panel refresh frame rate is consistent with the whole machine (that is, there is no need to read SRAM, during the skip frame, the AP is not sending data, and the DDIC source does not provide voltage to the panel), and the LDO unit 10 is turned off; if the AP is not updating data, the panel refresh frame rate is inconsistent with the whole machine (that is, the SRAM needs to be read, the AP maintains a lower frame rate, and the panel is still refreshed at a higher frame rate, and the refresh frame data needs to be read from the SRAM), the LDO unit is turned on for compensation, and a second value is input to the Vset terminal 101, that is, a lower level value is set. Optionally, if you do not pursue extreme power consumption reduction, in this case, the internal LDO can be turned on and set to a lower value.

[0055] The three gears of this embodiment can be automatically switched according to the added status detection module

[0056] Table 1 Truth table of MIPI interface Vedio mode

[0057]

[0058] Optional, in Command mode, as shown in Table 2

[0059] A) Screen off state: At this time, the power consumption is the lowest and the internal LDO unit 10 is turned off;

[0060] B) After waking up, refresh the frame: the internal LDO unit is turned on, and the first value is input to the Vset terminal 101, that is, a higher potential value is set.

[0061] C) After wake-up, non-refresh frame: If the AP is not updating data, the panel needs to continuously output image information. At this time, the SRAM module still needs to be read to continuously output the source voltage to the panel. The internal LDO unit 10 is turned on and a second value is input to the Vset terminal 101, that is, a lower potential value is set.

[0062] Table 2 Truth table of MIPI interface command mode

[0063]

[0064]

[0065] Optional, for EDP interface, as shown in Table 3

[0066] A) Screen off state: At this time, the power consumption is the lowest, and the LDO unit 10 is turned off

[0067] B) After waking up, refresh frame: the LDO unit 10 is turned on and inputs a first value to the Vset terminal 101, that is, sets a higher potential value.

[0068] C) After waking up, non-refresh frame, long v stage: AP is not updating data, the panel refresh frame rate is consistent with the whole machine (that is, there is no need to read the SRAM module, during longv, AP is not sending data, and DDIC source does not provide voltage to the panel), and LDO unit 10 is turned off; if AP is not updating data, the panel refresh frame rate is inconsistent with the whole machine (that is, the SRAM module needs to be read, AP maintains a lower frame rate, the panel is still refreshed at a higher frame rate, and the refresh frame data needs to be read from the SRAM module), LDO unit 10 is turned on and the second value is input to Vset terminal 101, that is, a lower level value is set. Optionally, if you do not pursue extreme power consumption reduction, you can turn on the internal LDO in this case and set a lower value.

[0069] Table 3 Truth table of EDP interface

[0070]

[0071]

[0072] In summary, Tables 1-3 can be simplified to Table 4:

[0073] Table 4 Simplified truth table

[0074]

[0075] Among them, A is the first value, a is the second value, and A>a.

[0076] It should be noted that this embodiment uses Vset divided into three gears for illustration. In fact, technicians in the relevant field can further divide it according to needs, that is, divide it into N gears to achieve stepless shifting.

[0077] The "equal" or "same" or "equal" disclosed in the present invention must take into account the distribution of engineering parameters, and the error distribution is within ±30%; the definition of "parallel" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is less than or equal to 45 degrees; the definition of "perpendicular" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is within the range of [60, 120] degrees; the definition of "phase mismatch" also needs to take into account the distribution of engineering parameters, and the error distribution of the degree of mismatch is within ±30%. In addition, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without more constraints, an element defined by the phrase "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0078] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0079] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DDIC power supply system, characterized in that: include: An LDO unit, a digital circuit unit, a VDD unit, a VDDI unit and a judgment control unit; The LDO unit includes a Vset terminal and an enable terminal; one end of the LDO module is connected to the VDDI unit, and the other end is connected to the digital circuit; The digital circuit unit includes a digital module, an SRAM module and a PHY module, one end of which is directly connected to the VDD unit; A judgment control unit comprises a first end, a second end and a third end; the first end is connected to the interface unit and is used to judge the working state of the interface unit; the second end is connected to the enable end and is used to turn on or off the LDO unit according to the working state; the third end is connected to the Vset end of the LDO unit and is used to adjust the input value of the Vset end according to the working state; A VDD unit is directly connected to the digital module, the SRAM module and the PHY module, and is used to provide a first voltage to the digital module, the SRAM module and the PHY module; The VDDI module is used to provide a second voltage to the LDO module.

2. The power supply system according to claim 1, characterized in that: The first voltage is 1.2V.

3. The power supply system according to claim 1, characterized in that: The second voltage is 1.8V.

4. A method for reducing DDIC power consumption based on the power supply system according to any one of claims 1 to 3, characterized in that: The following steps are involved: Step 1, DDIC receives a frame of data transmitted by AP through the interface unit; Step 2: Determine the working state of the interface unit and the reading state of the SRAM module according to the transmitted data, and adjust the parameters of the LDO unit.

5. The method according to claim 4, characterized in that In step 2, the working state of the interface unit and the reading state of the SRAM module are determined according to the transmitted data, and the parameters of the LDO unit are adjusted as follows: Step 2.1 determines the working state of the interface unit according to the transmitted data to control whether to turn on the LDO unit; if the interface state is in high-speed mode, turn on the LDO unit, input the first value to the Vset terminal, and jump to step 1; if the interface unit is in low-speed mode, jump to step 2.2; Step 2.2, further determine whether it is necessary to read the SRAM module, if necessary, turn on the LDO unit, input the second value to the Vset terminal, and jump to step 1; if not, turn off the LDO unit and jump to step 1; The first value is greater than the second value.

6. The method according to claim 5, characterized in that The first value is a higher level value.

7. The method according to claim 5, characterized in that The second value is a lower level value.

Images