Chip minimum component unit version information management method, electronic device and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a method, electronic device and medium for managing version information of a chip minimum component unit, the method comprising: step S1, generating a chip IP and chip IP version information based on the chip minimum component unit; step S2, generating a logic SOC and logic SOC version information; step S3, generating a first physical SOC and a first physical SOC version information based on the logic SOC and the logic SOC version information, the first physical SOC version information including the chip IP version information corresponding to the minimum component unit; step S4, generating a second physical SOC and a second physical SOC version information, the minimum component unit instance name in the version information corresponding to the second physical SOC including a hash code generated by hash transformation of the IP version information corresponding to the minimum component unit. The present invention improves the determination efficiency and accuracy of the version information of the IP corresponding to the minimum component unit.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method for managing version information of a minimum component unit of a chip, an electronic device and a medium. Background Art

[0002] The chip development process needs to go through multiple stages. The smallest components are interconnected to form different IPs (Intellectual Properties). Based on the IP and the smallest components, SOCs (System on Chip) of different stages are subsequently generated. During the chip development process, IP and SOC will iterate different versions. When a problem is found in the smallest component at any stage, it is usually necessary to first determine the version information of the IP corresponding to the smallest component with the problem before proceeding to the next step. However, due to the rapid iteration of versions during chip development, the large number of chip levels and the large scale of components, it is usually impossible to directly obtain the IP version information corresponding to the smallest component. If the version information of the IP corresponding to the smallest component is determined by backtracking stage by stage from large-scale data, the efficiency is extremely low and prone to errors. Therefore, how to improve the efficiency and accuracy of obtaining the version information of the IP corresponding to the smallest component has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The purpose of the present invention is to provide a method, electronic device and medium for managing version information of a chip minimum component unit, thereby improving the efficiency and accuracy of determining version information of an IP corresponding to the minimum component unit.

[0004] According to a first aspect of the present invention, a method for managing version information of a chip minimum component unit is provided, comprising:

[0005] Step S1, generating a chip IP and chip IP version information based on a chip minimum component unit, and establishing a mapping relationship between the minimum component unit and the chip IP version information;

[0006] Step S2, generating a logic SOC and logic SOC version information based on the chip IP and the chip IP version information, wherein the logic SOC version information includes the chip IP version information corresponding to the smallest component unit;

[0007] Step S3, generating a first physical SOC and first physical SOC version information based on the logical SOC and the logical SOC version information, wherein the first physical SOC includes a plurality of physical groups, each physical group includes at least one minimum component unit, the minimum component units included in the first physical SOC and the interconnection relationship between the minimum component units are the same as those in the logical SOC, and the first physical SOC version information includes chip IP version information corresponding to the minimum component unit;

[0008] Step S4: generate a second physical SOC and a second physical SOC version information by performing logic synthesis based on the first physical SOC and the first physical SOC version information, wherein the minimum component unit instance name in the version information corresponding to the second physical SOC includes a hash code generated by hash transformation of the IP version information corresponding to the minimum component unit.

[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the present invention provides a method for managing version information of the minimum component unit of a chip, an electronic device and a medium, which can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0012] The embodiment of the present invention manages the version information of the minimum component unit in the chip development process, so that the version information of each stage carries the mapping relationship between the minimum component unit and the IP version information, so that the version information of the IP corresponding to the minimum component unit in any stage can be queried, thereby improving the efficiency and accuracy of determining the version information of the IP corresponding to the minimum component unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a method for managing version information of a chip minimum component unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a method for managing version information of a chip minimum component unit, such as Figure 1 As shown, including:

[0017] Step S1: Generate chip IP and chip IP version information based on the minimum component unit of the chip, and establish a mapping relationship between the minimum component unit and the chip IP version information.

[0018] Each minimum component unit has a corresponding register transfer level (RTL) code. Chip design includes component modules set at multiple levels. A component module is a module composed of multiple minimum component units interconnected, or a minimum component unit. Chip IP is a component module in chip design. During the chip development process, IP may iterate multiple versions.

[0019] Step S2: Generate a logic SOC and logic SOC version information based on the chip IP and the chip IP version information, wherein the logic SOC version information includes the chip IP version information corresponding to the smallest component unit.

[0020] Among them, the logic SOC is composed of chip IP interconnection, and the chip IP is composed of the smallest component unit of the chip. Therefore, based on the correspondence between the smallest component unit and the chip IP, the IP version information corresponding to each smallest component unit in the logic SOC can be determined.

[0021] Step S3, generating a first physical SOC and first physical SOC version information based on the logical SOC and the logical SOC version information, the first physical SOC including multiple physical groups, each physical group including at least one minimum component unit, the minimum component units included in the first physical SOC and the interconnection relationship between the minimum component units are the same as those in the logical SOC, and the first physical SOC version information includes the chip IP version information corresponding to the minimum component unit.

[0022] Among them, in the physical stage, the smallest components in the logic SOC will be reorganized to generate different physical groups according to information such as physical layout and wiring. At this time, the chip IP no longer exists. During the reorganization, the number of the smallest components will not change, and the interconnection relationship between the smallest components will remain unchanged. Although the chip IP no longer exists, the first physical SOC version information of the present invention contains the chip IP version information corresponding to the smallest component unit, which is convenient for obtaining the chip IP version information corresponding to the smallest component unit.

[0023] Step S4: generate a second physical SOC and a second physical SOC version information by performing logic synthesis based on the first physical SOC and the first physical SOC version information, wherein the minimum component unit instance name in the version information corresponding to the second physical SOC includes a hash code generated by hash transformation of the IP version information corresponding to the minimum component unit.

[0024] It should be noted that in practical applications, in most cases, during the processing stage of the second physical SOC, there will be a situation where the minimum component unit needs to be backtracked. In the prior art, it is impossible to directly determine the IP version information of the minimum component unit that needs to be backtracked. It is often necessary to backtrack from the second physical SOC to the first physical SOC, then backtrack to the logical SOC, and then backtrack to the IP stage. Each stage does not contain complete version information. Therefore, each stage needs to be backtracked forward, but due to the fast version iteration speed and many iteration versions, the backtracking process takes a lot of time and cannot guarantee accuracy. Based on this, in step S4 of the embodiment of the present invention, the IP version information corresponding to the minimum component unit is directly set in the minimum component unit instance name in the version information corresponding to the second physical SOC. The hash code generated by the hash transformation of the IP version information corresponding to the minimum component unit can be directly obtained through the minimum component unit instance name, without backtracking stage by stage, thereby improving the acquisition efficiency and accuracy of the IP version information corresponding to the minimum component unit, thereby reducing the communication time cost between engineers at different stages and improving the chip development efficiency.

[0025] As an embodiment, the method further includes:

[0026] Step S10: Generate a second physical SOC version information file based on the second physical SOC version information.

[0027] It should be noted that, in order to facilitate the second physical SOC stage to obtain the IP version information corresponding to the minimum component unit, the second physical SOC version information is directly stored in a file, that is, the second physical SOC version information file.

[0028] Step S20: query the second physical SOC version information file to obtain the target minimum component unit instance name of the target minimum component unit.

[0029] Step S30: parse the hash code in the instance name of the target minimum component unit to determine the target IP version information corresponding to the target minimum component unit.

[0030] Among them, by querying the second physical SOC version information file and parsing the hash code, the IP version information corresponding to any minimum component unit in the second physical SOC can be accurately and quickly obtained.

[0031] It should be noted that in other stages, such as the logic SOC and the first SOC stages, there may also be a need to obtain the IP version information corresponding to the minimum component unit. Therefore, the version information corresponding to each stage can be stored in the database for subsequent search.

[0032] As an embodiment, the step S1 includes:

[0033] Step S11: construct a minimum component unit library, wherein the minimum component unit library includes all minimum component units required for chip development.

[0034] Step S12: Obtain the minimum component unit interconnection generation IP from the minimum component unit library n , and generate IP n Corresponding version information UP n =(P1 n , P2 n ), P1 n IP n The corresponding branch identifier, P2 n For P1 n The corresponding version number, n, ranges from 1 to N, where N is the total number of chip IPs.

[0035] It should be noted that the same IP may have different branches, and different branches have different versions. Therefore, it is necessary to record the branch identifier corresponding to the IP and the branch corresponding version number to accurately determine the corresponding IP.

[0036] As an embodiment, step S2 includes:

[0037] Step S21: Based on IP n and UP n Generate Logic SOC m and logic SOC m Version Information US m =(SC m , IPL m ), SC m For logic SOC m Version number, IPL m For logic SOC mContains IP list information, which is used to store logical SOC m Included IP n 、IP n The smallest components and IP included n Corresponding UP n .

[0038] It should be noted that SOC m There is a corresponding relationship between each IP, there is a corresponding relationship between each IP and the smallest component unit, and each IP has corresponding version information. Therefore, the mapping relationship between each smallest unit and the corresponding IP version information is clearly recorded in the IP list information.

[0039] Step S22: Logic SOC m The version information is stored in a preset data storage area, where the value of m ranges from 1 to M, and M is the total number of logical SOC versions.

[0040] As an embodiment, step S3 includes:

[0041] Step S31: Generate a mapping relationship between the smallest component unit and the chip IP and the physical group based on the logical interconnection relationship and physical layout between the smallest component units in the logic SOC.

[0042] It should be noted that the interconnection relationship between the smallest components is clearly defined in the logic SOC. When performing physical layout and routing, the smallest components need to be grouped according to the physical layout, but the interconnection relationship between the smallest components remains unchanged.

[0043] Step S32: Based on the mapping relationship between the smallest component unit, the chip IP and the physical group, the logical SOC m The smallest constituent units contained in the reorganization generate the first physical SOC m And the first physical SOC m Version InformationUQ m =(QC m , GL m ), QC m For the first physical SOC m Version number, GL m For the first physical SOC m The first physical group list includes the minimum component unit identifier included in the physical group and the IP version information corresponding to the minimum component unit.

[0044] It should be noted that the first physical SOC m The version information clearly states the first physical SOC m, physical group, minimum component unit identifier and the mapping relationship between the IP version information corresponding to the minimum component unit.

[0045] Step S33: The first physical SOC m The version information is stored in the preset data storage area, and the first physical SOC is established m Version information and logic SOC m The mapping relationship of version information.

[0046] As an embodiment, step S4 includes:

[0047] Step S41: Based on the first physical SOC m And the first physical SOC m Version information for the first physical SOC m Perform logic synthesis to generate the second physical SOC m and the second physical SOC m Version InformationUR m =(RC m ,RGL m ),RC m For the second physical SOC m Version number, RGL m For the second physical SOC m The second physical group list includes the instance name of the smallest component unit included in the second physical group, and the instance name of the smallest component unit includes a hash code generated by hash transformation of IP version information corresponding to the smallest component unit.

[0048] It should be noted that the first physical SOC m In the form of RTL code, the second physical SOC m Is the corresponding first physical SOC m The gate-level netlist form. Due to the second physical SOC m There are many scenarios where the IP version information corresponding to the minimum component unit needs to be determined in the stage. In order to further speed up the second physical SOC m The efficiency of determining the IP version information corresponding to the smallest component unit is directly determined in the second physical SOC m The minimum component unit instance name includes IP version information, and in order to further ensure information security, the IP version information corresponding to the minimum component unit is hashed and then added to the minimum component unit instance name.

[0049] Step S42: The second physical SOC m The version information is stored in the preset data storage area, and a second physical SOC is established m Version information and first physical SOC mThe mapping relationship between version information.

[0050] As an embodiment, the preset data storage area is a preset database, that is, the preset database is directly set, and the version information generated in each stage is directly stored in the preset database. In order to further improve the data processing speed, the version information generated in each stage can be first stored in the memory area, and then stored in the preset database together after all stages are executed. As an embodiment, the preset storage area is a memory area, and the step S4 includes:

[0051] Step S5: storing the data in the preset storage area into a preset database.

[0052] After the preset database is established, the target IP version information corresponding to the minimum component unit of any stage can be obtained through the preset database. As an embodiment, the method further includes:

[0053] Step S100: Obtain a target SOC identifier and a target minimum component unit identifier.

[0054] Step S200: query the preset database based on the target SOC identifier to determine the target version information corresponding to the target SOC identifier.

[0055] Step S300: query the target version information based on the target minimum component unit identifier to determine the target IP version information corresponding to the target minimum component unit.

[0056] It should be noted that, in addition to the target IP version information, other information at different stages in the preset database can also be obtained, for example, obtaining the first physical SOC m Corresponding physical group list, first physical SOC m A list of the smallest component unit identifiers in a corresponding physical group, etc.

[0057] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0058] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0059] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0060] The embodiment of the present invention manages the version information of the minimum component unit in the chip development process, so that the version information of each stage carries the mapping relationship between the minimum component unit and the IP version information, so that the version information of the IP corresponding to the minimum component unit in any stage can be queried, thereby improving the efficiency and accuracy of determining the version information of the IP corresponding to the minimum component unit.

[0061] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A method for managing version information of a chip minimum component unit, characterized in that: include: Step S1, generating a chip IP and chip IP version information based on a chip minimum component unit, and establishing a mapping relationship between the minimum component unit and the chip IP version information; Step S2, generating a logic SOC and logic SOC version information based on the chip IP and the chip IP version information, wherein the logic SOC version information includes the chip IP version information corresponding to the smallest component unit; Step S3, generating a first physical SOC and first physical SOC version information based on the logical SOC and the logical SOC version information, wherein the first physical SOC includes a plurality of physical groups, each physical group includes at least one minimum component unit, the minimum component units included in the first physical SOC and the interconnection relationship between the minimum component units are the same as those in the logical SOC, and the first physical SOC version information includes chip IP version information corresponding to the minimum component unit; Step S4, performing logic synthesis based on the first physical SOC and the first physical SOC version information to generate the second physical SOC and the second physical SOC version information, the minimum component unit instance name in the version information corresponding to the second physical SOC contains a hash code generated by hash transformation of the IP version information corresponding to the minimum component unit, the first physical SOC is in the form of RTL code, and the second physical SOC is in the form of a gate-level netlist of the corresponding first physical SOC.

2. The method according to claim 1, characterized in that The method further comprises: Step S10: generating a second physical SOC version information file based on the second physical SOC version information; Step S20, querying the second physical SOC version information file to obtain the target minimum component unit instance name of the target minimum component unit; Step S30: parse the hash code in the instance name of the target minimum component unit to determine the target IP version information corresponding to the target minimum component unit.

3. The method according to claim 1, characterized in that The step S1 comprises: Step S11, constructing a minimum component unit library, wherein the minimum component unit library includes all minimum component units required for chip development; Step S12: Obtain the minimum component unit interconnection generation IP from the minimum component unit library n , and generate IP n Corresponding version information UP n =(P1 n , P2 n ), P1 n IP n The corresponding branch identifier, P2 n For P1 n The corresponding version number, n, ranges from 1 to N, where N is the total number of chip IPs.

4. The method according to claim 3, characterized in that: The step S2 comprises: Step S21: Based on IP n and UP n Generate Logic SOC m and logic SOC m Version Information US m =(SC m , IPL m ), SC m For logic SOC m Version number, IPL m For logic SOC m Contains IP list information, which is used to store logical SOC m Included IP n 、IP n The smallest components and IP included n Corresponding UP n ; Step S22: Logic SOC m The version information is stored in a preset data storage area, where the value of m ranges from 1 to M, and M is the total number of logical SOC versions.

5. The method according to claim 4, characterized in that The step S3 comprises: Step S31, generating a mapping relationship between the smallest component unit and the chip IP and the physical group based on the logical interconnection relationship and physical layout between the smallest component units in the logic SOC; Step S32: Based on the mapping relationship between the smallest component unit, the chip IP and the physical group, the logical SOC m The smallest constituent units contained in the reorganization generate the first physical SOC m And the first physical SOC m Version InformationUQ m =(QC m , GL m ), QC m For the first physical SOC m Version number, GL m For the first physical SOC m A first physical group list included, the first physical group including a minimum component unit identifier included in the physical group and IP version information corresponding to the minimum component unit; Step S33: The first physical SOC m The version information is stored in the preset data storage area, and the first physical SOC is established m Version information and logic SOC m The mapping relationship of version information.

6. The method according to claim 5, characterized in that The step S4 comprises: Step S41: Based on the first physical SOC m And the first physical SOC m Version information for the first physical SOC m Perform logic synthesis to generate the second physical SOC m and the second physical SOC m Version InformationUR m =(RC m ,RGL m ),RC m For the second physical SOC m Version number, RGL m For the second physical SOC m A second physical group list is included, the second physical group list includes a minimum component unit instance name included in the second physical group, the minimum component unit instance name includes a hash code generated by hash transformation of IP version information corresponding to the minimum component unit; Step S42: The second physical SOC m The version information is stored in the preset data storage area, and a second physical SOC is established m Version information and first physical SOC m The mapping relationship between version information.

7. The method according to claim 6, characterized in that The preset data storage area is a preset database, or the preset data storage area is a memory area, and the step S4 includes: Step S5: storing the data in the preset data storage area into a preset database.

8. The method according to claim 7, characterized in that The method further comprises: Step S100, obtaining a target SOC identifier and a target minimum component unit identifier; Step S200: query the preset database based on the target SOC identifier to determine the target version information corresponding to the target SOC identifier; Step S300: query the target version information based on the target minimum component unit identifier to determine the target IP version information corresponding to the target minimum component unit.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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