FFT (Fast Fourier Transform) processor capable of resisting single node upset

Abstract

The invention discloses an FFT (Fast Fourier Transform) processor capable of resisting single-node upset. The FFT processor comprises a controller, a cache module, a butterfly operation module, a multiplication module, a first MUX (Multiplexer) and a second MUX, according to the invention, a design scheme that internal structures are respectively reinforced is adopted, a cache module adopts Hamming code error detection and correction, a butterfly operation module adopts berger code error detection and correction, a multiplication module adopts low-overhead approximate triple-modular redundancy error detection and correction, and a controller adopts triple-modular redundancy. According to the method, functional abnormality caused by single-node upset of the FFT processor due to the influence of the single event effect can be avoided, the resource overhead used for reinforcement is less, and the method is suitable for the resource-limited cosmic environment.

Description

Technical Field

[0001] The present invention relates to the field of FFT processors of circuits and systems, and in particular to an FFT processor resistant to single-node flipping. Background Art

[0002] As the complexity of space missions continues to increase, higher requirements are placed on the reliability and performance of integrated circuits. However, due to factors such as the reduction in device feature size, the shortening of device spacing, and the reduction in threshold voltage, the single particle effect has an increasingly significant impact on semiconductor devices in aerospace equipment, and conventional process-level reinforcement technology has gradually lost its effectiveness. Therefore, under nanotechnology, it is necessary to study and explore integrated circuit reinforcement technology from the circuit level.

[0003] As the basis of many digital signal processing algorithms, FFT has extensive and important applications in the aerospace field, covering many key areas such as signal modulation and demodulation, spectrum analysis and interference detection, radar target detection, navigation systems and harmonic analysis. In these application scenarios, the FFT processor plays an indispensable role, and its performance and reliability directly affect the operation of the entire aerospace system.

[0004] The fault-tolerant design of the FFT processor currently proposed has the problems of excessive resource overhead, which makes it unsuitable for resource-constrained aerospace scenarios, as well as poor fault-tolerance effect. When affected by single-particle effects, the FFT accuracy is seriously impaired. Therefore, it is particularly important to design an FFT processor with low overhead and good single-particle resistance. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an FFT processor resistant to single-node flipping in view of the problems involved in the background.

[0006] The present invention adopts the following technical solutions to solve the above technical problems:

[0007] An FFT processor resistant to single-node flipping includes a controller, a cache module, a butterfly operation module, a multiplication module, a first MUX and a second MUX;

[0008] The controller is used to receive external input data x[n-1:0] to be subjected to FFT and the recalculation indication signal recal output by the butterfly operation module, count the data x[n-1:0], and when the counting result cnt is less than the preset threshold value cnt_th1, set the control signal Sel1 to 0 and send it to the selection end of the first MUX, otherwise set Sel1 to 1 and send it to the selection end of the first MUX; when cnt is less than the preset threshold value cnt_th2, set the control signal Sel2 to 0 and send it to the selection end of the second MUX, otherwise set Sel2 to 1 and send it to the selection end of the second MUX; at the same time, judge the value of recal, if recal is 0, send the control signal to the decoding unit of the cache module;

[0009] The cache module includes a Hamming encoding unit, a cache unit and a decoding unit;

[0010] The Hamming encoding unit is used to receive the data to be cached output by the first MUX, encode it, and send the encoded information to the cache unit;

[0011] The cache unit is used to cache the encoded information;

[0012] The decoding unit is used to take out the encoded information from the cache unit for error detection, error correction and decoding, and to convert the information D after error detection, error correction and decoding into decode [n-1:0] are respectively transmitted to the butterfly operation module and the I0 terminal of the second MUX, and the information of the cache unit is decoded again when the control signal output by the controller is received;

[0013] The butterfly operation module comprises a butterfly operation unit, a butterfly operation error detection unit, a parity judgment unit, a comparator and a control unit;

[0014] The butterfly operation unit is used to convert the external input data x[n-1:0] to be FFT-ed and D decode [n-1:0] are added by ripple carry addition to obtain a sum signal Sum[n-1:0] and a carry signal C[n-1:0], and Sum[n-1:0] is sent to the parity judgment unit and the control unit, and C[n-1:0] is sent to the butterfly operation error detection unit;

[0015] The butterfly operation error detection unit is used to receive external input data x[n-1:0] that needs to be FFT, the output D of the cache module decode [n-1:0], the output of the butterfly operation unit C[n-1:0], according to the formula P(x[n-1:0])^P(D decode[n-1:0])^P(C[n-1:0]) performs the operation and sends the operation result F to the comparator, where P() is a bitwise XOR operation;

[0016] The parity judgment circuit is used to perform a bitwise XOR operation on the received sum signal Sum[n-1:0], and output the information P_S after the operation to the comparator;

[0017] The comparator is used to perform an XOR operation on the received F and P_S, and send the comparison result flag to the control unit;

[0018] The control unit is used to judge the output result flag of the comparator. If the flag is 0, the signal recal is set to 0 and sent to the control module; if the flag is 1, the received sum signal Sum[n-1:0] is sent to the I1 end of the first MUX and the I1 end of the second MUX respectively, and the signal recal is set to 1 and sent to the control module;

[0019] The multiplication module includes an n*n multiplier, a k*k multiplier, a data truncation unit, DFF1, a data expansion unit, a voting unit and DFF2;

[0020] The n*n multiplier is used to receive the operation result output by the second MUX, multiply it by the preset rotation factor A[n-1:0] to obtain the result D1[2*n-1:0], and send D1[2*n-1:0] to the voting unit;

[0021] The data truncation unit is used to receive the operation result output by the second MUX, save it as B[n-1:0], perform truncation operation on B[n-1:0] and the preset rotation factor A[n-1:0] according to the preset constant k, and obtain A t [k-1:0] and B t [k-1:0], and A t [k-1:0] and B t [k-1:0] output to k*k multiplier, A t [k-1:0] and B t The specific form of [k-1:0] is as follows:

[0022]

[0023] Where u represents the number of bits of data that are consecutively adjacent to and identical to the sign bit of A[n-1:0], and p represents the number of bits of data that are consecutively adjacent to and identical to the sign bit of B[n-1:0]. When u>k-1, u is set to k-1, and when p>k-1, p is set to k-1.

[0024] The k*k multiplier is used to convert A t [k-1:0] and B t [k-1:0] are multiplied to obtain the result R2[2*k-1:0], and R2[2*k-1:0] is sent to the data expansion unit and DFF1 respectively;

[0025] The DFF1 is used to perform falling edge sampling on R2[2*k-1:0] to obtain R3[2*k-1:0], and send R3[2*k-1:0] to the data expansion unit;

[0026] The data expansion unit performs expansion operations on the received R2[2*k-1:0] and R3[2*k-1:0] to obtain D2[2*n-1:0] and D3[2*n-1:0], and sends D2[2*n-1:0] and D3[2*n-1:0] to the voting unit;

[0027]

[0028] The voting unit comprises XOR gates XOR1 to XOR2n, a subtractor, a comparator, a NOR unit, an AND gate AND and a third MUX;

[0029] The XOR gates XOR1 to XOR2n are used to perform an XOR operation on the outputs D2[2*n-1:0] and D3[2*n-1:0] of the receiving data expansion unit, wherein the XOR gate XORj performs an XOR operation on D2[j] and D3[j], j is a natural number greater than or equal to 0 and less than or equal to 2*n-1, and the result after the XOR operation is sent to the NOR unit;

[0030] The subtractor is used to receive the output D2[2*n-1:0] of the data expansion unit and the output D1[2*n-1:0] of the n*n multiplier, subtract D2[2*n-1:0] from D1[2*n-1:0] to obtain ε, and output ε to the comparator;

[0031] The comparator is used to judge the size of ε and a preset threshold Th. If |ε| is greater than or equal to Th, the comparator sends 1 to the AND gate AND. If |ε| is less than Th, the comparator sends 0 to the AND gate AND.

[0032] The NOR unit is used to perform NOR operation on the outputs of the XOR gates XOR1 to XOR2n, and output the result to the AND gate AND;

[0033] The AND gate AND is used to perform an AND operation on the output of the comparator and the output of the NOR unit, and output the result to the selection end of the third MUX;

[0034] The third MUX is used to select D2[2*n-1:0] and D1[2*n-1:0] according to the output of the AND gate AND. If the output of the AND gate AND is 0, D2[2*n-1:0] is sent to DFF2; if the output of the AND gate AND is 1, D1[2*n-1:0] is sent to DFF2;

[0035] The DFF2 is used to perform rising edge sampling on the output of the receiving voting unit and output the result to the outside;

[0036] The first MUX is used to select x[n-1:0] and Sum[n-1:0] according to the control signal Sel1 of the controller received by its selection end, and if Sel1 is 0, x[n-1:0] is sent to the Hamming coding unit, and if Sel1 is 1, Sum[n-1:0] is sent to the Hamming coding unit;

[0037] The second MUX is used to select D according to the control signal Sel2 of the controller received by its selection end. decode [n-1:0] and Sum[n-1:0] are selected. If Sel2 is 0, D decode [n-1:0] to the n*n multiplier and the data truncation unit. If Sel2 is 1, Sum[n-1:0] is sent to the n*n multiplier and the data truncation unit respectively.

[0038] As a further optimization solution of the FFT processor resistant to single node flipping of the present invention, the information encoded by the Hamming coding unit is D code [n+r:0];

[0039] The D code The formula [n+r:0] is as follows, including information bits a[0]~a[n-1], check bits b[0]~b[r-1], and global parity bit op, where n and r are both natural numbers greater than 1, and 2 r ≥n+r+1; check digit is 2 m , m is a natural number greater than or equal to 0 and less than or equal to r-1; op is at the lowest bit, which is the result of XOR of all information bits; information bits a[0]~a[n-1] are n bits of data to be cached received by the Hamming coding unit, and are supplemented in the remaining positions from low to high bits;

[0040] D code [n+r:0]={a[n-1:2 r -r], b[r-1],…, b[3], a[3:1], b[2], a[0], b[1:0], op};

[0041] The encoding process of the check bit b[r-1:0] is as follows:code The binary format of all indexes in [n+r:0], where the indexes with the g-th bit being 1 are grouped as the g-th group, and r groups of indexes are obtained, 0≤g≤r-1; for each group of indexes, the indexes whose corresponding data are information bits are filtered out, and then the information bit data corresponding to all the filtered indexes are XORed to obtain the check bit corresponding to the group of indexes, where the check bit corresponding to the g-th group of indexes is b[g];

[0042] The error detection and correction process of the decoding unit is as follows: for the binary format of all indexes in the encoded information read from the cache module, the indexes whose g-th bit is 1 are grouped as the g-th group to obtain r groups of indexes, 0≤g≤r-1, for each group of indexes, the indexes whose corresponding data are information bits are screened out, and then the information bit data corresponding to all the screened indexes are XORed to obtain the check bits corresponding to the group of indexes, wherein the check bits corresponding to the g-th group of indexes are b_decode[g], and then the syndrome s[r-1:0] is obtained according to the following formula:

[0043]

[0044] If s[r-1:0] is 0 and op is 0, it means that there is no error in the transmission process; if s[r-1:0] is 0 and op is 1, it means that op has an error in the transmission process; if s[r-1:0] is between 1 and n+r, op is 1, it means that there is an error in the transmission process, and the number of errors is D code [(s[r-1:0]) 10 ], invert this bit to achieve error correction, and the data after error correction is D_cor[n+r:0];

[0045] The decoding process of the decoding unit is as follows:

[0046] Get the information bit D from the error-corrected data D_cor[n+r:0] decode [n-1:0], the formula is as follows:

[0047] D decode [n-1:0] = {D_cor[n-1:2 r -r], ...D-cor[15:9], D_cor[7:5], D_cor[3]}.

[0048] As a further optimization solution of the FFT processor resistant to single-node flipping of the present invention, the cache unit adopts SRAM or a register group.

[0049] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0050] The FFT processor proposed by the present invention can perform error detection and correction when a single node flip occurs, which basically does not affect the result of the FFT output, and has low resource overhead, saves design costs, and has portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of a module of the present invention;

[0052] Figure 2 is a schematic diagram of the principle of the data truncation unit;

[0053] Figure 3 It is a schematic diagram of the principle of the data expansion unit. DETAILED DESCRIPTION

[0054] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings:

[0055] The present invention may be implemented in many different forms and should not be considered limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0056] The following takes n=16 as an example to illustrate the specific implementation method;

[0057] like Figure 1 As shown, the present invention discloses an FFT processor resistant to single-node flipping, including a cache module, a butterfly operation module, a multiplication module and a controller, a first MUX and a second MUX;

[0058] The controller is implemented with triple-module redundancy, and is used to receive external input data x[15:0] to be subjected to FFT and the recalculation indication signal recal output by the butterfly operation module, and count the data x[15:0]. When the counting result cnt is less than the preset threshold value cnt_th1, the control signal Sel1 is set to 0 and sent to the selection end of the first MUX, otherwise Sel1 is set to 1 and sent to the selection end of the first MUX; when cnt is less than the preset threshold value cnt_th2, the control signal Sel2 is set to 0 and sent to the selection end of the second MUX, otherwise Sel2 is set to 1 and sent to the selection end of the second MUX; at the same time, the value of recal is judged, and if recal is 0, the control signal is sent to the decoding unit of the cache module;

[0059] The cache module includes a Hamming encoding unit, a cache unit and a decoding unit;

[0060] The Hamming encoding unit is used to receive the to-be-buffered data output by the first MUX, encode it, and convert the encoded information D code[21:0] is sent to the cache unit; when n=16, according to inequality 2 r ≥n+r+1, r is 5, and D code [21:0] formula is as follows, including information bits a[0]~a

[15] , check bits b[0]~b[4] and global parity bit op, check bits in 2 m , m is a natural number greater than or equal to 0 and less than or equal to 4; op is at the lowest bit and is the result of XORing all information bits; information bits a[0] to a

[15] are the 16-bit buffered data received by the Hamming coding unit, and are supplemented in the remaining positions from the lowest bit to the highest bit;

[0061] D code [21:0]={a[15:11],b[4],a[10:4],b[3],a[3:1],b[2],a[0],b[1:0],op};

[0062] The encoding process of the check bit b[4:0] is as follows: code The binary format of all indexes in [21:0], where the indexes with the g-th bit being 1 are grouped as the g-th group, resulting in 5 groups of indexes, 0≤g≤4; for each group of indexes, the indexes whose corresponding data are information bits are filtered out, and then the information bit data corresponding to all the filtered indexes are XORed to obtain the check bit corresponding to the group of indexes, where the check bit corresponding to the g-th group of indexes is b[g]; the specific formula for b[4:0] is as follows:

[0063]

[0064] The cache unit is used to cache the encoded information;

[0065] The decoding unit is used to take out the encoded information from the cache unit for error detection, error correction and decoding, and to convert the information D after error detection, error correction and decoding into decode [15:0] are respectively transmitted to the butterfly operation module and the I0 terminal of the second MUX, and the information of the cache unit is decoded again when the control signal output by the controller is received;

[0066] The error detection and correction process of the decoding unit is as follows: for the binary format of all indexes in the encoded information read from the cache module, the indexes whose g-th bit is 1 are grouped as the g-th group, and 5 groups of indexes are obtained, 0≤g≤4. For each group of indexes, the indexes whose corresponding data are information bits are screened out, and then the information bit data corresponding to all the screened indexes are XORed to obtain the check bits corresponding to the group of indexes, wherein the check bits corresponding to the g-th group of indexes are b_decode[g], and the specific formula of b_decode[4:0] is as follows:

[0067]

[0068] Then the syndrome s[r-1:0] is obtained according to the following formula:

[0069]

[0070] If s[4:0] is 0 and op is 0, it means that there is no error in the transmission process; if s[4:0] is 0 and op is 1, it means that op has an error in the transmission process; if s[4:0] is between 1 and 21 and op is 1, it means that there is an error in the transmission process, and the number of errors is D code [(s[4:0]) 10 ], invert this bit to achieve error correction, and the data after error correction is D_cor[21:0];

[0071] The decoding process of the decoding unit is as follows:

[0072] Get the information bit D from the error-corrected data D_cor[21:0] decode [15:0], the formula is as follows:

[0073] D decode [15:0]={D_cor[21:17],D_cor[15:9],D_cor[7:5],D_cor[3]}.

[0074] The butterfly operation module comprises a butterfly operation unit, a butterfly operation error detection unit, a parity judgment unit, a comparator and a control unit;

[0075] The butterfly operation unit is used to convert the external input data x[15:0] to be FFT-ed and D decode [15:0] are added by ripple carry addition to obtain a sum signal Sum[15:0] and a carry signal C[15:0], and Sum[15:0] is sent to the parity judgment unit and the control unit, and C[15:0] is sent to the butterfly operation error detection unit;

[0076] The butterfly operation error detection unit is used to receive external input data x[15:0] that needs to be FFT, the output D of the cache module decode [15:0], the output of the butterfly operation unit C[15:0], according to the formula P(x[15:0])^P(D decode [15:0])^P(C[15:0]) performs the operation and sends the operation result F to the comparator, where P() is a bitwise exclusive OR operation;

[0077] The error detection principle of the butterfly operation error detection unit is as follows: According to the Berger code relationship of addition, N(x[15:0])+N(D decode [15:0]) = N(S[15:0]) + N(C[15:0]), where N() operation represents the Berger code. Since the Berger code calculation is expensive, it can be rewritten as P(S[15:0]) = P(x[15:0])^P(D decode [15:0])^P(C[15:0]), where P() operation represents bitwise XOR. When the butterfly operation unit fails, the parity on both sides of the equation will be inconsistent. Therefore, it is only necessary to determine whether the equation is true to determine whether the calculation is wrong. The output F of the butterfly operation error detection unit is the value on the right side of the equation, and the output P_S of the parity judgment unit is the value on the left side of the equation. If the two values ​​are consistent, it means that the calculation is correct. If the two values ​​are inconsistent, it means that the calculation is wrong.

[0078] The parity judgment circuit is used to perform a bitwise XOR operation on the received sum signal Sum[15:0], and output the information P_S after the operation to the comparator;

[0079] The comparator is used to perform an XOR operation on the received F and P_S, and send the comparison result flag to the control unit;

[0080] The control unit is used to judge the output result flag of the comparator. If the flag is 0, the signal recal is set to 0 and sent to the control module; if the flag is 1, the received sum signal Sum[15:0] is sent to the I1 end of the first MUX and the I1 end of the second MUX respectively, and the signal recal is set to 1 and sent to the control module;

[0081] The multiplication module includes a 16*16 multiplier, an 11*11 multiplier, a data truncation unit, DFF1, a data expansion unit, a voting unit and DFF2;

[0082] The 16*16 multiplier is used to receive the operation result output by the second MUX, multiply it by the preset rotation factor A[15:0] to obtain the result D1[31:0], and send D1[31-1:0] to the voting unit;

[0083] The data truncation unit is used to receive the operation result output by the second MUX, save it as B[15:0], perform truncation operation on B[15:0] and the preset rotation factor A[15:0] according to the preset constant k=11, and obtain A t [10:0] and B t [10:0], and A t [10:0] and Bt [10:0] output to 11*11 multiplier, A t [10:0] and B t The specific form of [10:0] is as follows:

[0084]

[0085] Where u represents the number of bits of data that are consecutive and identical to the sign bit of A[15:0], and p represents the number of bits of data that are consecutive and identical to the sign bit of B[15:0]. When u>10, u is set to 10, and when p>10, p is set to 10.

[0086] The 11*11 multiplier is used to convert A t [10:0] and B t [10:0] are multiplied to obtain the result R2[21:0], and R2[21:0] is sent to the data expansion unit and DFF1 respectively; the value of k is based on the following: according to the area overhead of k*k multipliers (k is a positive integer greater than or equal to 8 and less than or equal to 16) with different bit widths and its impact on the accuracy of FFT results, it is found that when k is 11, the maximum benefit is obtained, so in this example, k is 11;

[0087] The DFF1 is used to perform falling edge sampling on R2[21:0] to obtain R3[21:0], and send R3[21:0] to the data expansion unit;

[0088] The data expansion unit performs expansion operations on the received R2[21:0] and R3[21:0] to obtain D2[31:0] and D3[31:0], and sends D2[31:0] and D3[31:0] to the voting unit;

[0089]

[0090] The voting unit comprises XOR gates XOR1 to XOR32, a subtractor, a comparator, a NOR unit, an AND gate AND and a third MUX;

[0091] The XOR gates XOR1 to XOR32 are used to perform an XOR operation on the outputs D2[31:0] and D3[31:0] of the receiving data expansion unit, wherein the XOR gate XORj performs an XOR operation on D2[j] and D3[j], where j is a natural number greater than or equal to 0 and less than or equal to 31, and the result after the XOR operation is sent to the NOR unit;

[0092] The subtractor is used to receive the output D2[31:0] of the data expansion unit and the output D1[31:0] of the n*n multiplier, subtract D2[31:0] from D1[31:0] to obtain ε, and output ε to the comparator;

[0093] The comparator is used to determine the size of ε and a preset threshold Th. If |ε| is greater than or equal to Th, the comparator sends 1 to the AND gate AND. If |ε| is less than Th, the comparator sends 0 to the AND gate AND. The value of Th is based on the following: when k is 11, the maximum error when no fault occurs is calculated to be 0.0039 (approximately 1 / 256), so the threshold Th is determined as That is, |D1[31:8]|;

[0094] The NOR unit is used to perform NOR operation on the outputs of the XOR gates XOR1 to XOR32, and output the result to the AND gate AND;

[0095] The AND gate AND is used to perform an AND operation on the output of the comparator and the output of the NOR unit, and output the result to the selection end of the third MUX;

[0096] The third MUX is used to select D2[31:0] and D1[31:0] according to the output of the AND gate AND. If the output of the AND gate AND is 0, D2[31:0] is sent to DFF2; if the output of the AND gate AND is 1, D1[31:0] is sent to DFF2;

[0097] The DFF2 is used to perform rising edge sampling on the output of the receiving voting unit and output the result to the outside;

[0098] The error correction process of the multiplication module is as follows: if a single-node flip occurs during the calculation process of the 16*16 multiplier, the absolute value of the difference between D1 and D2 is less than or equal to the threshold value Th, which means that the multiplication result is not greatly affected, and D1 is still selected as the output of the multiplication module. If the difference between D1 and D2 is greater than the threshold value Th, it means that the result of the 16*16 multiplier is wrong, and D2 is selected as the output of the multiplication module at this time; if a single-node flip occurs during the calculation process of the 11*11 multiplier, it will cause the values ​​of D2 and D3 to be inconsistent, and D1 is directly selected as the output of the multiplication module.

[0099] The first MUX is used to select x[15:0] and Sum[n-1:0] according to the control signal Sel1 of the controller received by its selection end, and if Sel1 is 0, x[15:0] is sent to the Hamming coding unit, and if Sel1 is 1, Sum[n-1:0] is sent to the Hamming coding unit;

[0100] The second MUX is used to select D according to the control signal Sel2 of the controller received by its selection end. decode [15:0] and Sum[n-1:0] to select, if Sel2 is 0, send D decode[15:0] to the 16*16 multiplier and the data truncation unit. If Sel2 is 1, Sum[n-1:0] is sent to the 16*16 multiplier and the data truncation unit respectively.

[0101] The following takes the input of the data truncation unit A[15:0]=16'b0000111110011001, B[15:0]=16'b1110110111010011 as an example to specifically illustrate the implementation process of the data truncation unit and the data expansion unit: The specific implementation principle of the data truncation unit is as follows: Figure 2 As shown in the figure, the number of consecutive and identical data after the sign bit of A[15:0] is 3, so u=3. The effective bit of A[15:0] is the sign bit 0 plus the 10-bit data 10'b1111100110. In order to compensate for the data truncation error, the highest bit A[1] of the truncated data needs to be added. Finally, the truncated data A is obtained. t is 11'b01111000111; the number of bits of data that are consecutive and identical to the sign bit after the sign bit of B[15:0] is 2 bits, so p=2. In order to compensate for the data truncation error, the highest bit B[2] of the truncated data needs to be added, and finally the truncated data B is obtained. t is 11'b10110111010; the result R2 output by the 11*11 multiplier is 22'b1101110110100110010110. The specific implementation principle of the data expansion unit is as follows Figure 3 As shown: the highest 5 bits of D2 (u+p=5) are the same as the sign bit of R2, the next 22 bits are the same as R2, and the remaining bits are padded with 0s.

[0102] In summary, the FFT processor resistant to single-node flipping proposed in the present invention can perform error detection and correction when a single-node flipping occurs, which basically does not affect the FFT output result, and has low resource overhead, saves design costs, and is portable.

[0103] The specific implementations shown above have described the purpose and technical solutions of the present invention in detail. It should be noted that several substitutions and improvements can be made without departing from the principle of the present invention, and these substitutions and improvements should also be considered as the protection scope of the present invention.

Claims

1. An FFT processor resistant to single-node flipping, characterized in that: It includes a controller, a cache module, a butterfly operation module, a multiplication module, a first MUX and a second MUX; The controller is used to receive external input data x[n-1:0] to be subjected to FFT and the recalculation indication signal recal output by the butterfly operation module, count the data x[n-1:0], and when the counting result cnt is less than the preset threshold value cnt_th1, set the control signal Sel1 to 0 and send it to the selection end of the first MUX, otherwise set Sel1 to 1 and send it to the selection end of the first MUX; When cnt is less than the preset threshold cnt_th2, the control signal Sel2 is set to 0 and sent to the selection end of the second MUX, otherwise Sel2 is set to 1 and sent to the selection end of the second MUX; at the same time, the value of recal is determined, and if recal is 0, the control signal is sent to the decoding unit of the cache module; The cache module includes a Hamming encoding unit, a cache unit and a decoding unit; The Hamming encoding unit is used to receive the data to be cached output by the first MUX, encode it, and send the encoded information to the cache unit; The cache unit is used to cache the encoded information; The decoding unit is used to take out the encoded information from the cache unit for error detection, error correction and decoding, and to convert the information D after error detection, error correction and decoding into decode [n-1:0] are respectively transmitted to the butterfly operation module and the I0 terminal of the second MUX, and the information of the cache unit is decoded again when the control signal output by the controller is received; The butterfly operation module comprises a butterfly operation unit, a butterfly operation error detection unit, a parity judgment unit, a comparator and a control unit; The butterfly operation unit is used to convert the external input data x[n-1:0] to be FFT-ed and D decode [n-1:0] are added by ripple carry addition to obtain a sum signal Sum[n-1:0] and a carry signal C[n-1:0], and Sum[n-1:0] is sent to the parity judgment unit and the control unit, and C[n-1:0] is sent to the butterfly operation error detection unit; The butterfly operation error detection unit is used to receive external input data x[n-1:0] that needs to be FFT, the output D of the cache module decode [n-1:0], the output of the butterfly operation unit C[n-1:0], according to the formula P(x[n-1:0])^P(D decode [n-1:0])^P(C[n-1:0]) performs the operation and sends the operation result F to the comparator, where P() is a bitwise XOR operation; The parity judgment circuit is used to perform a bitwise XOR operation on the received sum signal Sum[n-1:0], and output the information P_S after the operation to the comparator; The comparator is used to perform an XOR operation on the received F and P_S, and send the comparison result flag to the control unit; The control unit is used to judge the output result flag of the comparator. If the flag is 0, the signal recal is set to 0 and sent to the control module; if the flag is 1, the received sum signal Sum[n-1:0] is sent to the I1 end of the first MUX and the I1 end of the second MUX respectively, and the signal recal is set to 1 and sent to the control module; The multiplication module includes an n*n multiplier, a k*k multiplier, a data truncation unit, DFF1, a data expansion unit, a voting unit and DFF2; The n*n multiplier is used to receive the operation result output by the second MUX, multiply it by the preset rotation factor A[n-1:0] to obtain the result D1[2*n-1:0], and send D1[2*n-1:0] to the voting unit; The data truncation unit is used to receive the operation result output by the second MUX, save it as B[n-1:0], perform truncation operation on B[n-1:0] and the preset rotation factor A[n-1:0] according to the preset constant k, and obtain A t [k-1:0] and B t [k-1:0], and A t [k-1:0] and B t [k-1:0] output to k*k multiplier, A t [k-1:0] and B t The specific form of [k-1:0] is as follows: Where u represents the number of bits of data that are consecutively adjacent to and identical to the sign bit of A[n-1:0], and p represents the number of bits of data that are consecutively adjacent to and identical to the sign bit of B[n-1:0]. When u>k-1, u is set to k-1, and when p>k-1, p is set to k-1. The k*k multiplier is used to convert A t [k-1:0] and B t [k-1:0] are multiplied to obtain the result R2[2*k-1:0], and R2[2*k-1:0] is sent to the data expansion unit and DFF1 respectively; The DFF1 is used to perform falling edge sampling on R2[2*k-1:0] to obtain R3[2*k-1:0], and send R3[2*k-1:0] to the data expansion unit; The data expansion unit performs expansion operations on the received R2[2*k-1:0] and R3[2*k-1:0] to obtain D2[2*n-1:0] and D3[2*n-1:0], and sends D2[2*n-1:0] and D3[2*n-1:0] to the voting unit; The voting unit comprises XOR gates XOR1 to XOR2n, a subtractor, a comparator, a NOR unit, an AND gate AND and a third MUX; The XOR gates XOR1 to XOR2n are used to perform an XOR operation on the outputs D2[2*n-1:0] and D3[2*n-1:0] of the receiving data expansion unit, wherein the XOR gate XORj performs an XOR operation on D2[j] and D3[j], j is a natural number greater than or equal to 0 and less than or equal to 2*n-1, and the result after the XOR operation is sent to the NOR unit; The subtractor is used to receive the output D2[2*n-1:0] of the data expansion unit and the output D1[2*n-1:0] of the n*n multiplier, subtract D2[2*n-1:0] from D1[2*n-1:0] to obtain ε, and output ε to the comparator; The comparator is used to judge the size of ε and a preset threshold Th. If |ε| is greater than or equal to Th, the comparator sends 1 to the AND gate AND. If |ε| is less than Th, the comparator sends 0 to the AND gate AND. The NOR unit is used to perform NOR operation on the outputs of the XOR gates XOR1 to XOR2n, and output the result to the AND gate AND; The AND gate AND is used to perform an AND operation on the output of the comparator and the output of the NOR unit, and output the result to the selection end of the third MUX; The third MUX is used to select D2[2*n-1:0] and D1[2*n-1:0] according to the output of the AND gate AND. If the output of the AND gate AND is 0, D2[2*n-1:0] is sent to DFF2; if the output of the AND gate AND is 1, D1[2*n-1:0] is sent to DFF2; The DFF2 is used to perform rising edge sampling on the output of the receiving voting unit and output the result to the outside; The first MUX is used to select x[n-1:0] and Sum[n-1:0] according to the control signal Sel1 of the controller received by its selection end, and if Sel1 is 0, x[n-1:0] is sent to the Hamming coding unit, and if Sel1 is 1, Sum[n-1:0] is sent to the Hamming coding unit; The second MUX is used to select D according to the control signal Sel2 of the controller received by its selection end. decode [n-1:0] and Sum[n-1:0] are selected. If Sel2 is 0, D decode [n-1:0] to the n*n multiplier and the data truncation unit. If Sel2 is 1, Sum[n-1:0] is sent to the n*n multiplier and the data truncation unit respectively.

2. The FFT processor resistant to single node flipping according to claim 1, characterized in that: The information encoded by the Hamming encoding unit is D code [n+r:0]; The D code The formula [n+r:0] is as follows, including information bits a[0]~a[n-1], check bits b[0]~b[r-1], and global parity bit op, where n and r are both natural numbers greater than 1, and 2 r ≥n+r+1; check digit is 2 m , m is a natural number greater than or equal to 0 and less than or equal to r-1; op is at the lowest bit, which is the result of XOR of all information bits; information bits a[0]~a[n-1] are n bits of data to be cached received by the Hamming coding unit, and are supplemented in the remaining positions from low to high bits; D code [n+r:0]={a[n-1:2 r -r],b[r-1],…,b[3],a[3:1],b[2],a[0],b[1:0],op}; The encoding process of the check bit b[r-1:0] is as follows: code The binary format of all indexes in [n+r:0], where the indexes with the g-th bit being 1 are grouped as the g-th group, and r groups of indexes are obtained, 0≤g≤r-1; for each group of indexes, the indexes whose corresponding data are information bits are filtered out, and then the information bit data corresponding to all the filtered indexes are XORed to obtain the check bit corresponding to the group of indexes, where the check bit corresponding to the g-th group of indexes is b[g]; The error detection and correction process of the decoding unit is as follows: for the binary format of all indexes in the encoded information read from the cache module, the indexes whose g-th bit is 1 are grouped as the g-th group to obtain r groups of indexes, 0≤g≤r-1, for each group of indexes, the indexes whose corresponding data are information bits are screened out, and then the information bit data corresponding to all the screened indexes are XORed to obtain the check bits corresponding to the group of indexes, wherein the check bits corresponding to the g-th group of indexes are b_decode[g], and then the syndrome s[r-1:0] is obtained according to the following formula: If s[r-1:0] is 0 and op is 0, it means that there is no error in the transmission process; if s[r-1:0] is 0 and op is 1, it means that op has an error in the transmission process; if s[r-1:0] is between 1 and n+r, op is 1, it means that there is an error in the transmission process, and the number of errors is D code [(s[r-1:0]) 10 ], invert this bit to achieve error correction, and the data after error correction is D_cor[n+r:0]; The decoding process of the decoding unit is as follows: Get the information bit D from the error-corrected data D_cor[n+r:0] decode [n-1:0], the formula is as follows: D decode [n-1:0]={D_cor[n-1:2 r -r],…D_cor[15:9],D_cor[7:5],D_cor[3]}。 3. The FFT processor resistant to single node flipping according to claim 1, characterized in that: The cache unit adopts SRAM or register group.

Images