Vector processing device, chip, electronic equipment and method

Abstract

The invention discloses a vector processing device, a chip, electronic equipment and a method, and belongs to the technical field of chips. The vector processing device comprises an instruction buffer, a vector decoding unit, a register unit and a plurality of pipelines, the instruction buffer is used for storing instruction packets to be executed, and each instruction packet comprises a plurality of vector instructions which can be executed in parallel; the vector decoding unit is used for decoding each vector instruction included in the instruction packet to obtain a control signal corresponding to each vector instruction, and broadcasting the control signal corresponding to each vector instruction to the register unit and the plurality of assembly lines in a clock period; a register unit to store data related to the vector instruction; and the assembly line is used for processing data related to the vector instruction according to the control signal corresponding to the vector instruction to obtain a processing result corresponding to the vector instruction. By processing a plurality of vector instructions in one clock period, the processing efficiency of the vector instructions can be remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a vector processing device, chip, electronic equipment and method. Background Art

[0002] In the scenario of performing unified operations on large-scale data, vector processing devices can achieve efficient processing of vector data compared to scalar processing devices.

[0003] In the related art, during the operation of the vector processing device, the vector processing device issues a vector instruction in each clock cycle, and the vector processing device processes the vector data according to the vector instruction. When there is a need to improve the parallelism of the vector processing device, by expanding the number of data paths, multiple vector processing devices can process different vector instructions in one clock cycle, thereby achieving the purpose of improving parallelism.

[0004] However, in the related art, setting up a new data path in the vector processing device will increase the parallelism while also causing a substantial increase in the size of the vector processing device. Further research is needed to improve the architecture of the vector processing device's parallelism. Summary of the invention

[0005] The present application provides a vector processing device, chip, electronic device and method. The technical solution is as follows:

[0006] According to one aspect of an embodiment of the present application, a vector processing device is provided, the vector processing device comprising: an instruction buffer, a vector decoding unit, a register unit and a plurality of pipelines;

[0007] The instruction buffer is used to store at least one instruction packet to be executed, each of which includes a plurality of vector instructions that can be executed in parallel;

[0008] The vector decoding unit is used to decode each of the vector instructions included in the instruction packet to obtain a control signal corresponding to each of the vector instructions, and broadcast the control signal corresponding to each of the vector instructions to the register unit and the plurality of pipelines within one clock cycle;

[0009] The register unit is used to store data related to the vector instruction;

[0010] The pipeline is used to process data related to the vector instruction according to a control signal corresponding to the vector instruction to obtain a processing result corresponding to the vector instruction.

[0011] According to one aspect of an embodiment of the present application, a chip is provided, and the chip includes: the vector processing device as described above.

[0012] According to one aspect of an embodiment of the present application, an electronic device is provided, which includes the vector processing device as described above.

[0013] According to one aspect of an embodiment of the present application, there is provided an instruction processing method applied to a vector processing device, the vector processing device comprising: an instruction buffer, a vector decoding unit, a register unit and a plurality of pipelines; the method comprising:

[0014] The instruction buffer stores at least one instruction packet to be executed, each of the instruction packets including a plurality of vector instructions executable in parallel;

[0015] The vector decoding unit decodes each of the vector instructions included in the instruction packet to obtain a control signal corresponding to each of the vector instructions, and broadcasts the control signal corresponding to each of the vector instructions to the register unit and the plurality of pipelines within one clock cycle;

[0016] The register unit stores data related to the vector instruction;

[0017] The pipeline processes data related to the vector instruction according to a control signal corresponding to the vector instruction to obtain a processing result corresponding to the vector instruction.

[0018] The technical solution provided in the present application provides a new vector processing device architecture. The vector decoding unit in the vector processing device transmits multiple vector instructions in one clock cycle, so that the vector processing device can process multiple vector instructions in parallel in one clock cycle. On the one hand, the parallel execution of vector instructions by the vector processing device is realized, which helps to improve the parallelism of the vector processing device and improve the efficiency of the vector processing device in processing vector instructions.

[0019] On the other hand, since the vector processing device provided by the present application executes multiple vector instructions in one clock cycle, if there are at least two vector instructions with data interaction requirements in a certain clock cycle, the data interaction can be completed through the register unit in the vector processing device. Compared with data interaction through L2 Memory, the register unit inside the vector processing device has a faster data reading and writing speed, which helps to improve the efficiency of data interaction during the execution of vector instructions, so as to reduce the time consumption of executing vector instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a method for improving the parallelism of a vector processing unit in the related art;

[0021] Figure 2is a schematic diagram of data interaction of a vector processing unit provided by an exemplary embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of an inventive concept provided by an exemplary embodiment of the present application;

[0023] Figure 4 is a schematic diagram of a vector processing device provided by an exemplary embodiment of the present application;

[0024] Figure 5 is a schematic diagram of a vector decoding unit provided by an exemplary embodiment of the present application;

[0025] Figure 6 is a schematic diagram of a second feedforward network provided by an exemplary embodiment of the present application;

[0026] Figure 7 is a schematic diagram of a second feedforward network provided by another exemplary embodiment of the present application;

[0027] Figure 8 is a schematic diagram of a vector processing device provided by an exemplary embodiment of the present application;

[0028] Fig. 9 is a data flow diagram of a vector processing device provided by an exemplary embodiment of the present application;

[0029] Fig.10 It is a flowchart of an instruction processing method applied to a vector processing device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0031] Before introducing the present application, the terms involved in the present application are explained.

[0032] Scalar Process Unit (SPU): used to process serial programs, that is, the scalar processing unit is used to process a scalar data according to a scalar instruction.

[0033] Vector Process Unit (VPU): refers to a processing unit that processes vector data. The vector processing unit corresponds to the vector processing device in the claims. The vector processing unit can also be called a vector processor (VPE). Compared with a scalar processing unit, a vector processing unit can realize parallel processing of data. In particular, for application scenarios where the program logic itself is not complex but the amount of data is large, using a vector processor for processing helps to improve data processing efficiency. The vector processing device in the claims is equivalent to a part of a vector processing unit, or a complete vector processing unit.

[0034] Vector Load (VLD) operation: used to indicate reading vector data.

[0035] Vector Store (VST) operation: used to indicate the storage of vector data.

[0036] Vector Register (VR): refers to the register used to store vector data in the vector processing unit.

[0037] Prediction Register (PR): refers to the register used to store Boolean data in the vector processing unit.

[0038] A common architecture of vector processors is the Single Instruction Multi Data (SIMD) architecture, that is, multiple execution units execute the same vector instruction in the same clock cycle, and different execution units input different data in the process.

[0039] The vector processor of this architecture only processes one vector instruction in one clock cycle. If the parallelism needs to be improved, it needs to be expanded by increasing the number of data paths. Increasing the number of data paths can be understood as setting up multiple independent vector processing units.

[0040] Figure 1 It is a schematic diagram of a method for improving the parallelism of a vector processing unit in the related art.

[0041] In one clock cycle, different vector processing units can respectively execute different vector instructions, and n vector processing units are regarded as a whole, where n is a positive integer greater than . Then the whole can process n vector instructions in one clock cycle, thereby improving the degree of parallelism.

[0042] However, since the vector processing unit is a hardware entity with a certain structure, it also needs to occupy a certain area. Therefore, expanding the number of data paths will also increase the area consumption. In particular, when the data path is expanded to a certain extent, further expansion of the data path will not only bring about a large area consumption, but also fail to effectively improve the calculation speedup ratio of the operator.

[0043] Figure 2 It is a schematic diagram of data interaction of a vector processing unit provided by an exemplary embodiment of the present application.

[0044] The vector processing unit can process vector instructions. In the process of executing vector instructions, the operation data corresponding to the vector instructions needs to be processed. The method of increasing the degree of parallelism by increasing the data path in the related technology will have some problems in data interaction. If three tasks need to be processed in a certain application scenario (the task includes at least one vector instruction), the three tasks need to be sent to VPU0, VPU1 and VPU2 respectively through the task scheduler. If there is a need for data interaction between these three tasks, the above three VPUs need to exchange data through the external L2 (Level 2) Memory.

[0045] Since L2 Memory is set outside the three VPUs and is limited by the L2 Memory structure, the latency of data reading and writing on L2 Memory is relatively large. This results in low efficiency of data exchange between the three VPUs using L2 Memory, which is not conducive to efficient execution of tasks.

[0046] In the field of processors, vector processing capability has a great impact on the performance of parallel computing. The present application proposes a vector processing device that issues multiple vector instructions in one clock cycle, which helps to improve the processing performance of vector data and improve parallelism. In addition, the chip area consumed by the vector processing device is small, which helps to improve the parallel computing performance of the chip.

[0047] Figure 3 It is a schematic diagram of the inventive concept provided by an exemplary embodiment of the present application.

[0048] Compared to the vector processing unit in the related art, which can only execute a single vector instruction in a single clock cycle, the present application provides a new architecture of a vector processing device. The architecture of the vector processing device is provided with a vector decoding unit and rear units (such as a register unit and a pipeline, please refer to the following embodiments for details) for executing different types of vector instructions. The vector decoding unit can emit multiple vector instructions in one clock cycle, so that each rear unit in the vector processing device executes the vector instruction for which it is responsible in one clock cycle.

[0049] The vector processing device provided in the embodiment of the present application can be used as a complete vector processor, or a part of the vector processor can be encapsulated in a chip for processing vector type data. The chip can be an AI (Artificial Intelligence) chip for model training, a chip for completing image processing, a chip for completing video processing, etc. The present application does not limit the chip type used by the vector processing device.

[0050] In addition, the vector processing device is also provided with a register unit for storing data related to vector instructions. In the same clock cycle, if there is data interaction between different vector instructions, the read and write operations are performed through the register unit in the vector processing device, and the data is read faster.

[0051] Figure 4 is a schematic diagram of a vector processing device provided by an exemplary embodiment of the present application.

[0052] The vector processing device 400 includes an instruction buffer 410 , a vector decoding unit 420 , a register unit 430 and a plurality of pipelines 440 .

[0053] The vector processing device 400 is used to execute multiple vector instructions in one clock cycle and obtain processing results corresponding to the multiple vector instructions. A vector instruction refers to an instruction for operating vector type data. In other words, the basic operation object of a vector instruction is a vector, and a vector refers to a set of numbers arranged in an orderly manner. Vector data can be called a vector operand.

[0054] The vector processing device 400 performs the same operation on each value in the data related to the vector instruction according to the vector instruction.

[0055] In some embodiments, a vector instruction refers to an instruction for processing vector type data. Alternatively, a vector instruction refers to an instruction unit for processing vector type data. That is, a vector instruction is used to indicate the minimum processing step for processing vector type data, a vector instruction cannot be divided into smaller instructions, and vector type data is also data related to vector instructions in the claims.

[0056] Vector instructions are executed in clock cycles, and the vector processing device 400 needs to consume at least one clock cycle to execute a vector instruction. Optionally, the clock cycle is related to the frequency of the computer's main clock, and the computer refers to a device that supports the operation of the vector processing device 400. For example, the clock cycle is equal to the inverse of the main frequency during the operation of the computer.

[0057] Exemplarily, the type of vector instruction includes at least one of the following: a read instruction, a write instruction, an operation instruction, a logic processing instruction and a control instruction, wherein the read instruction is used to read data related to the vector instruction, the write instruction is used to write data related to the vector instruction, the operation instruction is used to perform arithmetic operations on the data related to the vector instruction, the logic processing instruction is used to perform logic processing on the data related to the vector instruction, and the control instruction is used to adjust the pipeline 440 in the vector processing device 400.

[0058] In some embodiments, the vector processing device 400 is connected to other devices in the processor. The vector processing device 400 obtains vector instructions and data related to the vector instructions from other devices, executes the vector instructions, processes the data related to the vector instructions, and implements the process of processing vector type data.

[0059] For the specific content of this part, please refer to the following examples.

[0060] Next, the composition and functions of the vector instruction processing device are introduced and explained.

[0061] The instruction buffer 410 is used to store at least one instruction packet to be executed, each instruction packet including a plurality of vector instructions that can be executed in parallel.

[0062] The instruction packet to be executed includes multiple vector instructions, and the multiple vector instructions included in one instruction packet to be executed are executed in parallel in one clock cycle. That is to say, the vector instructions executed in the same clock cycle are transmitted to the instruction buffer 410 of the vector processing device 400 in the form of an instruction packet. For the convenience of description, the instruction packet to be executed is simply described as an instruction packet below.

[0063] Optionally, there is no dependency between the multiple vector instructions included in the instruction packet, that is, there is no dependency between any two vector instructions in the multiple vector instructions.

[0064] Exemplarily, the dependency between vector instructions means: there is a dependency between data related to the vector instructions, that is, there is data dependency between the vector instructions in the same clock cycle. For example, the type of dependency between two vector instructions includes at least one of the following: in a first clock cycle, the two vector instructions need to operate on the vector data stored in the same register, and in the first clock cycle, the processing result obtained by executing the first vector instruction is the data to be processed by the second vector instruction; wherein the first clock cycle can be any clock cycle in the working process of the vector processing device 400.

[0065] For example, vector instruction 1 is used to operate on vector data V1, and vector instruction 2 is also used to operate on V1; in this case, vector instruction 1 processes V1 first, and vector instruction 2 processes V1 first, which may result in different final results of V1. Therefore, in this case, there is a dependency relationship between vector instruction 1 and vector instruction 2.

[0066] For another example, vector instruction 3 is used to operate on V3 to obtain the processed V3, and vector instruction 4 is used to operate on the processed V3. The processed V3 can only be obtained after vector instruction 3 is executed. Vector instruction 4 needs to be executed after vector instruction 3 is executed. Vector instruction 3 and vector instruction 4 cannot be executed in the same clock cycle. There is a dependency relationship between vector instruction 3 and vector instruction 4.

[0067] In some embodiments, the instruction packet is generated by a compiler related to the vector processing device 400. The compiler stores the execution timing of various types of vector instructions executable by the vector processing device 400; wherein the execution timing of the vector instruction refers to: the operations required to be performed during the execution of the vector instruction and the clock cycles occupied by each step.

[0068] The compiler predicts the execution status of the vector instructions at any time based on the execution timing of the vector instructions and the start time of the vector instructions. This enables the compiler to determine multiple vector instructions without dependencies from multiple vector instructions to be executed and generate an instruction package including the multiple vector instructions.

[0069] Optionally, after the user instructs to perform a task, the compiler generates all vector instructions required to complete the task in batches; the compiler determines the dependency between the vector instructions according to the execution timing of each vector instruction; and according to the dependency between the vector instructions, all vector instructions are divided to obtain at least one instruction package related to the task. Exemplarily, if the task needs to be completed by only one vector processing device 400, there is a timing relationship between at least one instruction package, that is, one clock cycle corresponds to at most one instruction package.

[0070] At least one instruction packet related to the task is executed by the vector processing device 400. In order to implement concurrent execution of vector instructions by the vector processing device 400, the vector processing device 400 sends multiple vector instructions in the same instruction packet within one clock cycle.

[0071] Exemplarily, after the compiler generates at least one instruction packet, it transmits the at least one instruction packet to the vector processing device 400 in sequence according to the timing of the instructions.

[0072] Exemplarily, the compiler transmits at least one instruction packet to the scalar processor, and before the vector processing device 400 obtains the instruction packet, the scalar processor executes the scalar instruction; after the scalar instruction is executed, the scalar processor transmits the instruction packet to be executed to the vector processing device 400. Optionally, the instruction packet sent by the scalar processor is received by the instruction buffer 410 of the vector processing device 400.

[0073] In one example, the scalar processor can transmit the instruction packet to the vector processing device while executing the scalar instruction. For example, each vector instruction included in the instruction packet does not need to use the operand generated by a certain scalar instruction, then in the process of executing the scalar instruction, the scalar processor can transmit the instruction packet 1 to the vector processing device 400. Different clock cycles correspond to different instruction packets, so before a task is completed, the vector processing device can continuously obtain instruction packets related to the task.

[0074] It should be noted that the present application focuses on a vector processing device 400 that implements high-performance processing of vector instructions. The steps of compiling the compiler to generate instruction packets are not described in detail. The instruction packets can be understood as instruction packets that have been encoded and converted into machine language that can be directly processed by the vector processing device 400.

[0075] Optionally, the number of vector instructions included in different instruction packets is equal. For example, each instruction packet includes n vector instructions, where n is a positive integer greater than 1, and n is less than or equal to the maximum number of vector instructions that can be executed in parallel by the vector processing device 400. For example, the maximum number of vector instructions that can be executed in parallel by the vector processing device 400 is 3, and n is equal to 3 or 2.

[0076] Optionally, there are at least two instruction packets, and the numbers of vector instructions respectively included in the two instruction packets are not equal. For example, the first instruction packet includes x vector instructions, and the second instruction packet includes y vector instructions, x and y are positive integers greater than 1, x is not equal to y, and x and y are both less than or equal to the maximum number of vector instructions that the vector processing device 400 can execute in parallel. Assume that the maximum number of vector instructions that the vector processing device 400 can execute in parallel is 3, x is equal to 2, and y is equal to 3.

[0077] It should be noted that the specific number of vector instructions included in the instruction packet and the vector processing device are determined according to actual needs, and this application does not limit this.

[0078] In some embodiments, the instruction buffer 410 is used to store at least one instruction packet. Optionally, there is a transmission path for the instruction packet between the instruction buffer 410 and a scalar processor outside the vector processing device 400, and the scalar processor sends the instruction packet to the instruction buffer 410 through the transmission path for the instruction packet.

[0079] For a certain instruction packet to be executed, before the instruction buffer 410 transmits the instruction packet to the vector decoding unit 420 , the instruction buffer 410 continues to store the instruction packet.

[0080] Optionally, the instruction buffer 410 determines the timing of sending the instruction packet to the vector decoding unit 420 according to the clock cycle. Exemplarily, after the vector decoding unit 420 transmits each vector instruction in the instruction packet y in the i-th clock cycle, the instruction buffer 410 transmits the instruction packet y+1 to the vector decoding unit 420 in the i+1-th clock cycle, where i is a positive integer. For the specific content of the vector decoding unit 420, please refer to the following embodiments.

[0081] In one example, the instruction cache 410 determines which instruction packet to be executed is preferentially transmitted to the vector decoding unit 420 according to the timing of receiving the instruction packets to be executed. Optionally, the instruction cache 410 adopts the first-in-first-out principle to determine which instruction packet to be executed is transmitted to the vector decoding unit 420; wherein the first-in-first-out principle means: preferentially transmitting the earliest received instruction packet to be executed to the vector decoding unit 420. After the instruction cache 410 sends a certain instruction packet to be executed, the instruction cache 410 can delete the instruction packet to be executed to prevent repeated transmission of the same instruction packet.

[0082] In this case, the instruction cache 410 may be a memory capable of implementing a queue data structure, and the instruction cache 410 may be called a vector instruction queue. Of course, the instruction cache 410 may also be a memory capable of implementing other data structures, which is not limited in this application.

[0083] In some embodiments, the instruction cache 410 in the vector processing device 400 is an entry for obtaining vector instructions. All vector instructions that need to be processed by the vector instruction device 400 must be transmitted from an external device (such as a scalar processor) to the vector processing device 400 through the instruction cache 410.

[0084] The vector decoding unit 420 is introduced and described below.

[0085] The vector decoding unit 420 is used to decode each vector instruction included in the instruction packet, obtain the control signal corresponding to each vector instruction, and broadcast the control signal corresponding to each vector instruction to the register unit 430 and multiple pipelines 440 within one clock cycle.

[0086] Decoding a vector instruction can be understood as extracting the information carried in the vector instruction, and the subsequent units in the vector processor use this information to control the pipeline to execute this vector instruction.

[0087] After receiving the instruction packet sent by the instruction cache 410, the vector decoding unit 420 decodes the instruction packet to obtain control signals corresponding to each vector instruction. Optionally, the vector decoding unit 420 decodes each vector instruction in the instruction packet and can also obtain data signals corresponding to each vector instruction. The data signal can also be called an immediate number. An immediate number refers to data carried by a vector instruction and required to be used in the process of executing the vector instruction. An immediate number belongs to scalar data.

[0088] The vector decoding unit 420 broadcasts control signals corresponding to each vector instruction to the register unit 430 and the plurality of pipelines 440 at an appropriate clock cycle. In some embodiments, the appropriate clock cycle means that in the clock cycle, there is no dependency between each vector instruction in the instruction packet and any vector instruction being executed, or there is no vector instruction being executed in the vector processing device at the clock cycle.

[0089] Optionally, the vector instruction being executed refers to a vector instruction whose control signal has been broadcast by the vector decoding unit 420 but has not been executed. For example, in the kth clock cycle, the vector decoding unit 420 broadcasts the control signal corresponding to the vector instruction a to the register unit 430 and the plurality of pipelines 440. In the k+1th clock cycle, the vector instruction a has not been executed. Then, for the k+1th clock cycle, the vector instruction a belongs to the vector instruction being executed, and k is a positive integer. The vector instruction being executed can also be called the predecessor instruction of the vector instruction to be emitted.

[0090] That is, before sending the control signals corresponding to the respective vector instructions in the instruction packet, the vector decoding unit 420 needs to check the dependency between the vector instruction to be issued (ie, any one of the multiple vector instructions included in the instruction packet) and the vector instruction being executed.

[0091] Optionally, for a certain clock cycle, if there is a dependency relationship between the vector instructions in the instruction packet and the vector instructions being executed, the vector decoding unit 420 will not emit each of the multiple vector instructions in the instruction packet in the clock cycle. Exemplarily, in this case, the vector decoding unit 420 temporarily stores the multiple vector instructions in the instruction packet; the vector decoding unit 420 waits for the next clock cycle, re-verifies the dependency relationship between each of the vector instructions in the instruction packet and the vector instructions being executed, until a suitable instruction cycle is found to broadcast the control signals of each of the vector instructions included in the instruction packet, and then the vector decoding unit 420 obtains the next instruction packet from the instruction buffer 410.

[0092] Optionally, if there is no dependency relationship between all vector instructions in the instruction packet and the vector instruction being executed, the vector decoding unit 420 transmits multiple vector instructions included in the instruction packet in the clock cycle. It should be noted that in this application, "transmitting vector instructions" and "the vector decoding unit 420 broadcasting the control signal corresponding to the vector instruction" have the same meaning.

[0093] For example, a certain instruction packet includes vector instruction a, vector instruction b and vector instruction c. The vector decoding unit 420 determines whether there is a dependency relationship between the vector instruction being executed in the vector processing device 400 and vector instruction a, between the vector instruction being executed and vector instruction b, and between the vector instruction being executed and vector instruction c in clock cycle 1. The vector decoding unit 420 determines that there is a dependency relationship between vector instruction b and the vector instruction being executed, and then the vector decoding unit 420 determines that the control signals corresponding to vector instruction a, vector instruction b and vector instruction c respectively cannot be broadcast in clock cycle 1. The vector decoding unit 420 temporarily stores the instruction packet. In clock cycle 2 after clock cycle 1, the vector decoding unit 420 re-determines the dependency relationship between vector instruction a, vector instruction b and vector instruction c respectively and the vector instruction being executed; if there is no dependency relationship between vector instruction a, vector instruction b and vector instruction c and the vector instruction being executed, then the vector decoding unit 420 broadcasts the control signals corresponding to vector instruction a, vector instruction b and vector instruction c respectively in clock cycle 2.

[0094] In some embodiments, there is a transmission line of control signals between the vector decoding unit 420 and the register unit 430, and there is a transmission line of control signals between the vector decoding unit 420 and the pipeline 440. For example, for the vector instruction a in the instruction packet, the vector decoding unit 420 broadcasts the control signal corresponding to the vector instruction a to the register unit 430 and the plurality of pipelines 440, which can be understood as: the vector decoding unit 420 transmits the control signal corresponding to the vector instruction a to the register unit 430 and the plurality of pipelines 440 through the transmission line of the control signal. For the structural composition of the vector decoding unit 420, please refer to the following example.

[0095] The rear unit of the vector decoding unit 420 mentioned above includes a register unit 430 and a plurality of pipelines 440 .

[0096] The register unit 430 is introduced below through several embodiments.

[0097] The register unit 430 is used to store data related to vector instructions.

[0098] In some embodiments, the data related to the vector instruction includes at least one of the following: the operation data of the vector instruction, the execution result of the vector instruction. The operation data of the vector execution refers to the data object that needs to be processed by the vector instruction. For example, for a read instruction in a vector instruction, the data to be read is the operation data of the read instruction. The execution result of the vector instruction refers to the intermediate result or the final result obtained by performing calculation or logical processing on the operation data according to the vector instruction. For example, for a vector instruction that performs an addition operation, the result of the addition operation is the execution result of the vector instruction.

[0099] Optionally, the register unit 430 is a data register for storing vector type data.

[0100] Since different vector instructions are used to process different types of operation data, the vector processing device 400 may include different types of registers, and different registers are used to store different types of operation data and execution results; wherein the operation data belongs to vector type data, and the operation data may also be called vector operand.

[0101] Optionally, the vector processing device 400 includes at least two types of register units 430, which are: vector registers and prediction registers; wherein the vector registers are used to store vector data to be subjected to arithmetic operations and processing results obtained by performing arithmetic operations; the prediction registers are used to store Boolean data to be subjected to logical processing and to obtain processing results by performing logical processing on the Boolean data.

[0102] For different vector instructions, the types of data associated with the vector instructions may be different. For example, the data associated with a certain vector instruction is vector data, and the data associated with another vector instruction is Boolean data.

[0103] In some embodiments, the operation data in the register unit 430 comes from a storage space outside the vector processing device 400. The storage space may be called a vector memory. The storage space may be a storage space corresponding to a static address, such as L1 Memory.

[0104] Optionally, the vector memory is used to store data that the vector processing device 400 needs to use in the process of executing vector instructions, and the processing results obtained after the vector processing device 400 executes the vector instructions. Exemplarily, the data related to the vector instructions in the register unit 430 comes from the vector memory, and the register unit 430 reads the operation data from the vector memory, or the register unit 430 stores the processing results in the vector memory. The vector processing device 400 may also include a vector load storage unit (Vector Load Store Unit, VLSU). Data is transmitted between the L1 Memory and the register unit 430 through the vector load storage unit. For the specific content of the vector load storage unit, please refer to the following embodiments.

[0105] Optionally, the operation data in the register unit 430 may come from the pipeline 440. There is an operation data transmission path between the register unit 430 and the pipeline 440. The register unit 430 transmits the to-be-processed data corresponding to the vector instruction to the pipeline 440 through the operation data transmission path. The pipeline 440 sends the processing result to the register unit 430 through the operation data transmission path. The processing result can be used as the operation data of the vector instruction issued in the subsequent clock cycle.

[0106] The pipeline is introduced and explained through several embodiments below.

[0107] The pipeline 440 is used to process data related to the vector instruction according to a control signal corresponding to the vector instruction to obtain a processing result corresponding to the vector instruction.

[0108] Optionally, for pipeline 440 , data related to vector instructions refers to operation data that needs to be processed by the pipeline, that is, data transmitted to the pipeline through the entrance of pipeline 440 .

[0109] The pipeline 440 includes: an entry, at least one arithmetic logic unit (ALU), at least one register, and an exit; wherein the entry is used to pass the operation data into the pipeline 440, the arithmetic logic unit is used to process the operation data, the register in the pipeline is used to store the intermediate data generated during the vector data calculation process, and the exit is used to output the processing result obtained by processing the operation data.

[0110] It can be seen from the above content that the data related to the vector instruction includes: vector type operation data (hereinafter referred to as vector data) and vector type Boolean data (hereinafter referred to as Boolean data).

[0111] Optionally, the plurality of pipelines 440 include at least one of the following: a pipeline for performing arithmetic operations on vector data, and a pipeline for performing logical processing on Boolean data. For example, the plurality of pipelines 440 include two pipelines for performing arithmetic operations on vector data, and one pipeline for performing logical processing on Boolean data. For another example, the plurality of pipelines 440 include three pipelines for performing arithmetic operations on vector data, and one pipeline for performing logical processing on Boolean data.

[0112] It should be noted that the number of pipelines in the vector processing device 400 is set according to actual needs and is not limited in this application.

[0113] Optionally, a pipeline includes at least one operation unit, different operation units are used to perform different types of arithmetic operations, and multiple operation units share the inlet and outlet of the pipeline. This configuration enables multiple operation units to reuse the outlet and inlet of the pipeline 400, avoiding the need to set multiple outlets and read ports in the pipeline 400, which helps reduce the hardware consumption of the vector processing device 400.

[0114] In some embodiments, after receiving the control signal broadcast by the vector decoding unit 420, the register unit 430 and the pipeline 440 each determine whether the received control signal can be processed. Optionally, the control signal includes an attribute identifier of a vector instruction, and the attribute identifier is used to indicate a subsequent unit that can execute the vector instruction, and the subsequent unit includes the register unit 430 and the pipeline 440. The register unit 430 and the pipeline 440 determine whether the vector instruction corresponding to the control signal can be executed through the attribute identifier of the vector instruction in the control signal.

[0115] For the register unit 430, if the register unit 430 determines that the received control signal cannot be processed, the register unit 430 regards the control signal as an invalid control signal, and the register unit 430 ignores the control signal; if the register unit 430 determines that the received control signal can be processed, the register unit 430 regards the control signal as a valid control signal, and the register unit 430 executes the corresponding vector instruction according to the valid control signal, for example, the register unit 430 performs read and write operations on the operation data according to the valid control signal.

[0116] For pipeline 440, if pipeline 440 determines that it cannot process the received control signal, pipeline 440 treats the control signal as an invalid control signal and pipeline 440 ignores the control signal; if pipeline 440 determines that it can process the received control signal, pipeline 440 treats the control signal as a valid control signal and pipeline 440 executes operation data according to the valid control signal to obtain a processing result.

[0117] In one example, the instruction buffer 410 transmits the instruction packet 1 to the vector decoding unit 420 through the transmission path of the instruction packet; wherein the instruction packet includes 3 vector instructions. The vector decoding unit 420 decodes the instruction packet 1 to obtain the control signals corresponding to the above 3 vector instructions respectively; the vector decoding unit 420 determines whether there is a dependency relationship between the above 3 vector instructions and the vector instructions being executed in clock cycle 1 (current clock cycle). If there is no dependency relationship between the above 3 vector instructions and the vector instructions being executed in clock cycle 1, the vector decoding unit 420 broadcasts the control signals corresponding to the 3 vector instructions respectively in clock cycle 1, so that the register unit 430 and the multiple pipelines 440 can receive the control signals corresponding to the 3 vector instructions respectively.

[0118] For any vector instruction a among the three vector instructions, after receiving the control signal corresponding to the vector instruction a, the register unit 430 determines whether the control signal is a valid control signal for the register unit 430. If the control signal is a valid control signal, the register unit 430 executes the vector instruction a according to the control signal; if the control signal is an invalid control signal, it means that the vector instruction a cannot be executed by the register unit 430.

[0119] For any vector instruction a among the three vector instructions, after receiving the control signal corresponding to the vector instruction a, pipeline p1 determines whether the control signal is a valid control signal for pipeline p1. If the control signal is a valid control signal, pipeline p1 executes vector instruction a according to the control signal; if the control signal is an invalid control signal, it means that vector instruction a cannot be executed by pipeline p1, and pipeline p1 ignores the control signal corresponding to the vector instruction a. Optionally, pipeline p1 waits to receive control signals of other vector instructions in this clock cycle.

[0120] To sum up, the vector decoding unit in the vector processing device emits multiple vector instructions in one clock cycle, so that the vector processing device can process multiple vector instructions in parallel in one clock cycle. On the one hand, the parallel execution of vector instructions by the vector processing device is realized, which helps to improve the parallelism of the vector processing device and improve the efficiency of the vector processing device in processing vector instructions.

[0121] On the other hand, since the vector processing device provided by the present application executes multiple vector instructions in one clock cycle, if there is a vector instruction with data interaction requirements in a certain clock cycle, the data interaction can be completed through the register unit in the vector processing device. Compared with data interaction through L2 Memory, the register unit in the vector processing device has a faster data reading and writing speed, which helps to improve the efficiency of data interaction during the execution of vector instructions, so as to reduce the time consumption of executing vector instructions.

[0122] The vector decoding unit is introduced and explained through several embodiments below.

[0123] In some embodiments, the vector decoding unit includes: a decoder, a scoreboard and a harzard detector; the decoder is used to decode the instruction packet to obtain the immediate values ​​and control signals corresponding to each vector instruction in the instruction packet; the scoreboard is used to record the execution status of at least one vector instruction being executed, and the control signal corresponding to the vector instruction being executed is broadcast by the vector decoding unit before the clock cycle; the harzard detector is used to determine the dependency between each vector instruction in the instruction packet and the vector instruction being executed, so as to broadcast the control signals corresponding to each vector instruction to the register unit and multiple pipelines within one clock cycle when there is no dependency between each vector instruction in the instruction packet and the vector instruction being executed.

[0124] Optionally, the decoder obtains the instruction packet from the instruction buffer and decodes the multiple vector instructions included in the instruction packet to obtain control signals corresponding to the respective vector instructions in the instruction packet. Exemplarily, the decoder can decode the multiple vector instructions included in the instruction packet simultaneously, or can decode the vector instructions in the instruction packet one by one.

[0125] Optionally, the scoreboard is used to count the dependencies between vector instructions, and the scoreboard includes at least one entry, which can characterize the execution status of the vector execution being executed. When the control signal corresponding to a certain vector instruction is broadcast by the vector decoding unit, the scoreboard starts to record the execution status of the vector execution. Exemplarily, the scoreboard includes multiple entries, and the execution status of a vector instruction being executed is recorded by at least one entry. If the scoreboard includes 40 entries, it should be noted that the number of entries included in the scoreboard is set according to actual needs, and this application will not be repeated here.

[0126] In some embodiments, the vector processing device is configured with execution information of different types of vector instructions, and the execution information is used to characterize the execution status of the vector instruction at different time points after the vector instruction starts executing. After the control signal of a vector instruction is broadcast, the scoreboard updates the entry corresponding to the vector instruction according to the execution information of the vector instruction, thereby achieving the effect of recording the execution status of the vector through the entry.

[0127] Optionally, the chaos detector is used to determine whether there is a dependency relationship between the vector instruction in the instruction packet and the vector instruction being executed according to the execution status of at least one executing vector instruction recorded in the scoreboard.

[0128] If there is a dependency relationship between the vector instructions in the instruction packet and the vector instruction being executed, the confusion detector determines that the vector decoding unit cannot broadcast control signals corresponding to each vector instruction included in the instruction packet in the current clock cycle.

[0129] If there is no dependency relationship between the vector instructions in the instruction packet and the vector instruction being executed, the confusion detector determines that the vector decoder can broadcast control signals corresponding to each vector instruction included in the instruction packet in the current clock cycle.

[0130] In some embodiments, there is a transmission path between the decoder and the scoreboard; there is an execution status transmission path between the scoreboard and the chaos detector. After the decoder obtains the control signal corresponding to the vector instruction, the decoder transmits each vector instruction in the instruction packet to the scoreboard through the transmission path, and the scoreboard transmits the execution status of the vector instruction being executed in the clock cycle and the above-mentioned each vector instruction to the chaos detector through the transmission path of the execution status.

[0131] By setting the decoder to decode multiple vector instructions included in the instruction packet in one clock cycle, and verifying the dependency between the multiple vector instructions in the instruction packet and the instruction being executed through the scoreboard and the confusion detector, it is helpful to realize that the vector decoding unit broadcasts the control signals corresponding to the multiple vector instructions in one clock cycle, and ensures that the multiple vector instructions can be smoothly executed in parallel. Through this architecture, the vector decoding unit can emit multiple vector instructions in one clock cycle, which helps to improve the concurrency of the vector processing device.

[0132] In the case where there is a dependency between the vector instructions in the instruction packet and the vector instructions being executed, since the control signals corresponding to the multiple vector instructions in the instruction packet cannot be transmitted in the current clock cycle, the instruction packet needs to be stored in the vector decoding unit. The device for realizing this function in the vector decoding unit is described below.

[0133] In some embodiments, the vector decoding unit also includes: an instruction packet register; an instruction packet register, which is used to store control signals corresponding to each vector instruction in the instruction packet before the execution of the executing vector instruction is completed, when there is a dependency relationship between at least one vector instruction in the instruction packet and any vector instruction being executed.

[0134] In some embodiments, the instruction packet register can store control signals of each vector instruction included in an instruction packet. Optionally, there is a transmission path for instruction signals between the instruction packet register and the decoder, and there is a transmission path between the confusion detector and the instruction packet register. Of course, it can also be understood that the instruction packet register is used to store an instruction packet, and after a certain clock cycle starts, the decoder re-decodes the instruction packet stored in the instruction packet register to obtain control signals corresponding to each vector instruction included in the instruction packet.

[0135] Exemplarily, after the decoder decodes and obtains the control signals corresponding to the respective vector instructions in the instruction packet, the decoder transmits the control signals corresponding to the respective vector instructions to the instruction packet register through the control signal transmission path, and the instruction packet register stores the control signals corresponding to the respective vector instructions.

[0136] Exemplarily, after the chaos detector completes the verification of whether there is a dependency relationship between each vector instruction and the vector instruction being executed, the chaos detector transmits the dependency verification result to the instruction packet register through the transmission path. The dependency verification result includes two types: the existence of a dependency relationship and the non-existence of a dependency relationship; the existence of a dependency relationship means that there is a dependency relationship between at least one vector instruction in the instruction packet and any vector instruction being executed, and the non-existence of a dependency relationship means that there is no dependency relationship between any vector instruction in the instruction packet and any vector instruction being executed. Exemplarily, the dependency verification result is represented by at least one bit character.

[0137] The instruction packet register determines whether it is necessary to store the control signals corresponding to each vector instruction in the current clock cycle according to the dependency verification result. If the dependency verification result is that there is a dependency, the instruction packet register determines to store the control signals corresponding to each vector instruction in the instruction packet in the current clock cycle. If the dependency verification result is that there is no dependency, the instruction packet register determines that the control signals corresponding to each vector instruction will be broadcast in the current clock cycle. Optionally, after the vector decoding unit broadcasts the control signals corresponding to each vector instruction, the instruction packet register deletes the control signals corresponding to each vector instruction in the instruction packet.

[0138] Figure 5 It is a schematic diagram of a vector decoding unit provided by an exemplary embodiment of the present application.

[0139] like Figure 5 As shown, the vector decoding unit includes a decoder, a scoreboard, a confusion detector and an instruction packet register. After the decoder receives the instruction packet, the decoder decodes each vector instruction in the instruction packet to obtain a control signal corresponding to each vector instruction. The confusion detector determines whether the control signal corresponding to each vector instruction can be broadcast in the current clock cycle according to the execution status of the vector instruction being executed recorded in the scoreboard.

[0140] If there is a dependency relationship between the vector instructions in the instruction packet and any instruction being executed, the control signals corresponding to the respective vector instructions are stored in the current clock cycle via the instruction packet register.

[0141] If there is no dependency between each vector instruction in the instruction packet and the instruction being executed, the vector decoding unit broadcasts the control signals corresponding to each vector instruction to the memory unit and multiple pipelines in the current clock cycle. Subsequently, the decoder obtains a new instruction packet and continues to run from the step of decoding the new instruction packet.

[0142] This setting allows the vector decoding unit to wait for the appropriate clock cycle to transmit the control signal corresponding to each vector instruction in the instruction package, thereby ensuring that multiple vector instructions in the instruction package can be executed in the same clock cycle, thereby reducing the time interval between the moments when multiple vector instructions in the instruction package are executed. It helps to reduce the number of clock cycles that need to be waited before the control signal of the vector instruction in the subsequent instruction package begins to be broadcast, thereby improving the efficiency of the vector processing device in processing vector instructions.

[0143] Since some vector instructions need to use scalar data, i.e., scalar operands, during their execution. "Operands" in this application, without a qualifier, refer to scalar data. This part of scalar data can be obtained by a scalar processor processing a scalar instruction, or it can be carried in a vector instruction. The following describes the settings for implementing the transmission of scalar data in a vector processing device through several embodiments.

[0144] In some embodiments, the vector processing device also includes: at least one operand buffer and at least one selection unit, the operand buffer being used to store the operands required to be processed by the first vector instruction when the vector instruction is a first vector instruction that performs mixed operations on vector data and operands; the selection unit being used to select target data from the operands and the immediate numbers corresponding to the first vector instruction according to the first vector instruction, the target data being the operands or the immediate numbers corresponding to the first vector instruction; and a transmission path for the target data being provided between the selection unit and the pipeline.

[0145] Optionally, the operand buffer is used to store operands calculated by the scalar processor. Exemplarily, there is an operand transmission path between the operand buffer and the scalar processor, and the scalar processor transmits the operand obtained by executing the scalar instruction to the operand buffer through the operand transmission path, and the operand participates in the execution process of the corresponding vector instruction. Optionally, the vector instruction corresponding to the operand is a vector instruction for performing arithmetic operations.

[0146] Exemplarily, the operand buffer follows the first-in-first-out principle, that is, when operands are involved in the vector instruction, the operand buffer outputs the operand that is first written into the operand buffer according to the input timing of each operand in the operand buffer. Optionally, after the operand buffer outputs an operand, the operand buffer deletes the output operand.

[0147] In this case, the operand buffer may be a buffer having a queue structure, and the operand buffer may be called a scalar operand queue.

[0148] Optionally, the operand buffer has a data structure of a circular queue. For example, in the process of managing operands by the operand buffer having the data structure of a circular queue, after a certain operand is output from the operand queue, the operand queue does not delete the operand, and when a new operand is input, the operand queue uses the new operand to overwrite the operand that has been output.

[0149] Since operands are used only when a vector instruction performs an arithmetic operation on vector data, an operand buffer is required to provide operands to a pipeline for performing an arithmetic operation.

[0150] In some embodiments, at least one operand buffer is provided in the vector processing device, and different operands are stored in different operand buffers. Optionally, the number of operand buffers included in the vector processing device is related to the number of pipelines used for performing arithmetic operations. Exemplarily, the number of operand buffers is less than or equal to the number of pipelines used for performing arithmetic operations.

[0151] For example, the number of operand buffers is equal to the number of pipelines for performing arithmetic operations. In this case, each pipeline for performing arithmetic operations independently corresponds to an operand buffer.

[0152] For another example, the number of operand buffers is less than the number of pipelines for performing arithmetic operations. In this case, there are at least two pipelines for performing arithmetic operations in the vector processing device that share one operand buffer.

[0153] In one example, the vector processing device includes two pipelines for performing arithmetic operations, namely pipeline 1 and pipeline 2, and the vector processing device includes operand buffer 1 and operand buffer 2. The (scalar) operands required for pipeline 1 are stored through operand buffer 1, and the operands required for pipeline 2 are stored through operand buffer 2. By configuring operand buffers for different pipelines in the vector processing device, it helps to simplify the management method of operands by the operand buffer, so that the operand buffer can directly transmit operands to the corresponding pipeline without the need for the operand buffer to perform logical judgment to determine which pipeline to transmit the operand to. This setting helps to avoid transmitting operands to the wrong pipeline, thereby improving the accuracy of the vector processing device in processing vector instructions.

[0154] In some embodiments, the target pipeline refers to a pipeline for executing the first vector instruction. In a certain clock cycle, the vector decoding unit sends control signals corresponding to the respective vector instructions belonging to the same instruction package to the multiple pipelines. For the target pipeline, the control signal corresponding to the first vector instruction is a valid control signal, and the control signals corresponding to the other vector instructions in the instruction package except the first vector instruction are invalid control signals; after receiving the control signal corresponding to the first vector instruction, the target pipeline starts to perform the corresponding operation.

[0155] It should be noted that before multiple vector instructions that need to be executed in one clock cycle are transmitted to the vector processing device in the form of an instruction packet, which pipeline the first vector instruction is executed by is pre-configured. Optionally, the pre-configuration is implemented by an application that generates the instruction packet, or is implemented in the process of encoding the instruction packet, which is not limited in this application.

[0156] Exemplarily, after calculating the operands required during the execution of a first vector instruction, the scalar processor searches for a preconfigured target pipeline for executing the first vector instruction in a subsequent clock cycle; the scalar processor passes the operands to the operand buffer corresponding to the target pipeline through the operand transmission path, so that at the beginning of the clock cycle that broadcasts the control signal corresponding to the first vector instruction, the target pipeline can obtain the operands required to execute the first vector instruction through its corresponding operand buffer.

[0157] In some embodiments, the selection unit is used to select from the operand and the immediate number corresponding to the first vector instruction to obtain target data, that is, the target data is the operand, or the immediate number corresponding to the first vector instruction; there is a transmission path for the target data between the selection unit and the pipeline.

[0158] Optionally, the immediate number corresponding to the first vector instruction refers to a data signal obtained after the vector decoding unit decodes the first vector instruction. Exemplarily, there is an immediate number transmission path between the decoder in the vector decoding unit and the selection unit; after the decoder decodes the instruction packet and obtains the immediate number corresponding to the first vector instruction, the decoder transmits the immediate number corresponding to the first vector instruction to the selection unit through the immediate number transmission path.

[0159] Exemplarily, the selection unit includes two data inputs and one data output; wherein, one data input is used to transfer the operand in the operand buffer to the selection unit, and the other data input is used to transfer the immediate number corresponding to the first vector instruction to the selection unit; the selection unit selects one from the operand and the immediate number corresponding to the first vector instruction as the target data according to the first vector instruction.

[0160] In some embodiments, the target data refers to scalar data actually used in the process of executing the first instruction data. The target data is related to the type of the first vector instruction. For example, the selection unit determines whether to select an operand as the target data or to select an immediate value corresponding to the first vector instruction as the target data according to the type of the first vector instruction. There is a transmission path for the target data between the selection unit and the target pipeline for executing the first vector instruction. After determining the target data, the selection unit transmits the target data to the entrance of the target pipeline through the transmission path of the target data.

[0161] Exemplarily, the data size of the target data is 32 bits. It should be noted that the data size of the target data is set according to actual needs, and this application does not limit it. That is, the data transmission bandwidth between the target pipeline and the selection unit needs to be greater than or equal to 32 bits.

[0162] Since the time when the selection unit determines the target data may be different from the time when the vector decoding unit transmits the control signal corresponding to the first vector instruction, a target data register is further provided on the transmission path of the target data between the selection unit and the target pipeline. The target data register is used to store the target data of the first vector instruction before the control signal corresponding to the first vector instruction is transmitted. Optionally, after the vector decoding module broadcasts the control signal corresponding to the first vector instruction, the target data register transmits the target register to the target pipeline.

[0163] By setting the operand buffer and the selection unit, the orderly storage and transmission of scalar data can be realized when the vector instruction involves scalar data. By setting the target data register, it helps to align the time when the control signal of the target data and the vector instruction reaches the pipeline, avoiding the target data from being passed into the pipeline too early, causing the target data to participate in the execution process of the preceding vector instruction. At the same time, it avoids the target data from being passed into the pipeline too late, prolonging the time to execute the vector instruction, helping to reduce the probability of errors in the execution process of the vector instruction, and helping to ensure the correct execution of the vector instruction.

[0164] Due to the type of vector instruction, the type of data related to the vector instruction is also different. For example, some data related to the vector instruction is a decimal, and other data related to the vector instruction is an integer or a Boolean value. In order to adaptively store the type of data related to the vector instruction, the register unit includes different types.

[0165] In some embodiments, the register unit includes at least one of the following: a vector register and a prediction register; the vector register is used to store vector data related to the vector instruction; the prediction register is used to store Boolean (bool) data related to the vector instruction.

[0166] Vector data refers to vectors waiting for arithmetic operations, or the processing results obtained after arithmetic operations are completed. Boolean data refers to vectors waiting for logic processing, or the processing results obtained after logic processing. The vector data and Boolean data mentioned here are both data in vector form.

[0167] Optionally, vector data and Boolean data have different data volumes. Each numerical value included in the vector data requires multiple bits to represent, while each number in the Boolean data can take only two values, "0" and "1", and therefore can be represented using only 1 bit.

[0168] In the case where the data related to the vector instruction is vector data, the data related to the vector instruction is stored in the vector register. In the case where the data related to the vector instruction is Boolean data, the data related to the vector instruction is stored in the prediction register. That is, in the case where the vector instruction is a vector instruction for performing arithmetic operations, the vector data is stored in the vector register, and in the case where the vector instruction is a vector instruction for performing logical processing, the vector data is stored in the prediction register.

[0169] In some embodiments, the vector processing device includes at least one of a vector register and a prediction register. For example, if the vector processing device is only used to implement arithmetic operations, the vector processing device only includes vector registers; if the vector processing device is only used to implement logical processing, the vector processing device only includes prediction registers; if the vector processing device is required to have both arithmetic operation functions and logical processing functions, the vector processing device needs to include both vector registers and prediction registers.

[0170] In order to improve the processing capability of the vector processing device for different types of vector instructions, a vector register and a prediction register need to be set in the vector processing device at the same time. Optionally, the vector processing device includes at least one vector register and at least one prediction register. In one example, in order to simplify the read and write operations of the operation data, reduce the hardware resource consumption of the vector processing device, and control the area of ​​the vector processing device, the vector processing device includes a vector register and a prediction register.

[0171] Since the data types stored in the vector register and the prediction register are different, there is rarely a need for data exchange between the two. Therefore, a data path may not be set between the vector register and the prediction register.

[0172] In some embodiments, a read port and a write port are provided in the vector register; wherein the read port of the vector register is used to read vector data from the vector register, and the write port of the vector register is used to write vector data into the vector register.

[0173] Optionally, there are multiple vector data data paths between the vector register and the pipeline for processing the vector data; wherein a part of the vector data data paths are connected to the write port of the vector register, and the vector data paths of this part are used to write the vector data generated by the pipeline into the vector register through the write port of the vector register; another part of the vector data data paths are connected to the read port of the vector register, and the vector data paths of this part are used to read the vector data from the vector register through the read port of the vector detector. The specific content of this part will be explained after the pipeline is introduced below.

[0174] Optionally, the vector register includes multiple entries, and the entries are used to store vector data. Exemplarily, the vector register includes 32 entries, each entry is used to store at least one vector data, or multiple consecutive entries are used to store one vector data. The capacity of each entry can be 128 bits, 256 bits, 512 bits, etc. The capacity of the entries in the vector register is set according to actual needs, and this application does not set this.

[0175] Optionally, the number of read ports and write ports in the vector register are not equal. Exemplarily, the number of read ports and write ports in the vector register is set according to the read-in and write-out requirements of the vector register in one clock cycle, which is not limited in this application. For example, the vector register includes 5 read ports and 4 write ports. The read port in the vector register is used to read the vector data stored in the vector register, and the write port in the vector register is used to write the vector data into the vector register. Exemplarily, there is a transmission path for vector data between the read port of the vector register and the entrance of the pipeline for arithmetic operations, there is a transmission path for vector data between the write port in the vector register and the exit of the pipeline for arithmetic operations, and there is a transmission path for vector data between the write port in the vector register and the vector load storage unit. For the specific content of this part, please refer to the following embodiments.

[0176] In some embodiments, a read port and a write port are provided in the prediction register; wherein the read port of the prediction register is used to read Boolean data from the prediction register, and the write port of the prediction register is used to write Boolean data into the prediction register.

[0177] Optionally, there are multiple Boolean data data paths between the prediction register and the pipeline used to process Boolean data; among them, a part of the Boolean data data paths are connected to the write port of the prediction register, and this part of the Boolean data data paths are used to write the Boolean data generated by the pipeline into the prediction register through the write port of the prediction register; another part of the Boolean data data paths are connected to the read port of the prediction register, and this part of the Boolean data data paths are used to read the Boolean data from the prediction register through the read port of the vector detector.

[0178] Optionally, the prediction register includes at least one entry for storing Boolean data. For example, the prediction register includes 8 entries. It should be noted that the number of entries included in the prediction register is set according to the processing requirements of the vector processing device for Boolean data, and is not set in this application.

[0179] Since the frequency of occurrence of vector instructions for processing vector data and vector instructions for processing Boolean data is not equal, and the frequency of occurrence of vector instructions for processing vector data is higher; that is, the transmission pressure of vector data in the vector register is greater than the transmission pressure of Boolean data in the prediction register, in order to save the hardware overhead of the vector processing device, the number of entries in the prediction register can be set to be smaller than the number of entries in the vector register, so as to improve the utilization rate of each entry in the prediction register and reduce the idle ratio of entries in the prediction register. For example, the prediction register includes 8 entries and the vector register includes 32 entries.

[0180] In some embodiments, there is multiplexing between the read ports of the vector register and the prediction register. Optionally, there is a transmission path for vector data between the prediction register and the pipeline for performing arithmetic operations. Exemplarily, when the read port of the prediction register is in an idle state, the read port of the prediction register transmits vector data to the pipeline through the transmission path for vector data between the pipeline for performing arithmetic operations. That is, there is a transmission path for vector data between the read port of the prediction register and the entrance of the first pipeline. Exemplarily, the prediction register obtains vector data through the vector load storage unit in the vector processing device, and transmits the vector data to the entrance of the first pipeline through the transmission path for vector data between the first pipeline; wherein the first pipeline refers to the pipeline for performing arithmetic operations.

[0181] When there are multiple pipelines for performing arithmetic operations, vector data transmission paths are respectively provided between the prediction register and the multiple pipelines for performing arithmetic operations, or vector data transmission paths are provided between the prediction register and some of the multiple pipelines for performing arithmetic operations. In one example, a vector processing device includes s pipelines for performing arithmetic operations, wherein a vector data transmission interface is established between the prediction register and r of the s pipelines, and for any one of the r pipelines, there is a vector data transmission path between the entrance of the pipeline and the read port of the prediction register; s is a positive integer, and r is a positive integer less than or equal to s.

[0182] In some embodiments, in the process of multiplexing the first read port of the prediction register, the source of the vector data transmitted to the entrance of the pipeline through the read port includes at least one of the following: a vector register, a vector memory, and the first read port refers to a read port that can establish a transmission path for vector data between the prediction register and the entrance of the pipeline.

[0183] For example, when all read ports of the vector register are occupied, the vector register transfers the vector data to be transferred to the prediction register, and the prediction register uses the first read port to transfer the vector data to the entry of the pipeline.

[0184] For another example, in a certain clock cycle, there is an idle read port in the prediction register. The prediction register reads vector data required for the vector instruction to be executed from the vector register through the vector load storage unit, and transmits the vector data to the entrance of the pipeline through the first read port.

[0185] In order to improve the efficiency of the vector processing device in processing vector instructions, a plurality of pipelines for performing arithmetic operations are provided in the vector processing device. In order to enable the read port of the prediction register to transmit the vector data to the correct pipeline, there is a transmission path for vector data between the first read port in the prediction register and the entry of at least one pipeline. For example, there is a transmission path for vector data between the first read port and the entry of pipeline 1 and pipeline 2. For another example, there is a transmission path for vector data only between the first read port and the entry of pipeline 1, and the first read port refers to any read port in the prediction register.

[0186] This setting helps to improve the utilization efficiency of the read ports in the prediction register, helps to reduce the demand for the number of read ports in the vector register, reduces the hardware overhead of the vector processing device and saves the area of ​​the vector processing device.

[0187] Optionally, there is a Boolean data transmission path between the prediction register and the pipeline for performing logic processing. Exemplarily, when the read port of the vector register is in an idle state, the read port of the vector register transmits the Boolean data to the pipeline through the Boolean data transmission path between the prediction register and the pipeline for performing logic processing.

[0188] By multiplexing the read ports of the vector registers and the prediction registers, the efficiency of data transmission to the pipeline within the unit time of the vector processing device is improved, and the hardware overhead of the vector processing device is reduced.

[0189] There is a dependency relationship between some preamble instructions with an earlier broadcast time and subsequent instructions with a later broadcast time. For example, the preamble instruction is used to instruct the first data to be written into the register unit, and the subsequent instruction is used to instruct the first data to be read from the register unit. Then the first data belongs to the dependent data between the preamble instruction and the subsequent instruction. In this case, the control signal corresponding to the subsequent instruction can only be transmitted after the execution of the preamble instruction is completed. Since it takes at least one clock cycle to write the first data into the register unit, the subsequent instruction needs to wait for at least one clock cycle after the preamble instruction is transmitted before it can be transmitted. This architecture design that can only read the written data from the register unit will bring some operation delays, resulting in the need for the subsequent vector instruction to wait for at least one clock cycle. The following describes the design of solving this problem in the vector processing device through several embodiments.

[0190] In some embodiments, a forwarding network is provided in the register unit, and the forwarding network is used to obtain data related to vector instructions generated by the pipeline and not written into the register unit. The forwarding network includes establishing a data transmission path between the register unit and the read port of the register unit. That is, through the forwarding network, the read port of the register unit can directly read the data that has not been written into the register unit from the write port of the register unit.

[0191] Optionally, the register unit includes a vector register and a prediction register, a forward pass network can be set in the vector register, and a forward pass network can also be set in the prediction register. The following takes the vector register as an example to introduce and explain the method for setting the forward pass network in the register unit.

[0192] In some embodiments, a first forward pass network is provided in the vector register, and the first forward pass network is used to obtain vector data generated by the pipeline and not written into the vector register.

[0193] Optionally, the first forward network is arranged between the read port and the write port of the vector register. For the vector data written into the vector register through the write port, the vector data can be read from the write port of the vector register by the read port of the vector register through the first forward network before being written into the vector register.

[0194] Setting a forward pass network in a vector processor helps improve the execution efficiency of two vector instructions with dependent data, helps reduce the clock cycles required to wait before executing vector instructions, and helps improve the efficiency of a vector processing device in executing vector instructions within a unit time.

[0195] The following describes a method for setting up the first forwarding network through an embodiment.

[0196] In some embodiments, the vector register is provided with p read ports and y write ports, where p and y are positive integers; the read port is used to read vector data from the vector register, and the write port is used to write vector data into the vector register; the first forward network is used to establish a transmission path for vector data between the write port and the read port.

[0197] Optionally, there are t write ports among the y write ports, and the t write ports are all used to write the vector data output by the pipeline into the vector register, t is a positive integer less than or equal to y, and the first forward network is used to establish a transmission path for the vector data between the t write ports and the s read ports, s is a positive integer less than or equal to p.

[0198] Optionally, t is greater than s, that is, the first forward network is used to establish a data path between any one of the t write ports and multiple read ports. Through this setting, vector instructions that have dependent data and need to read the dependent data can obtain the dependent data through any one of the t read ports in the vector register.

[0199] Optionally, t is equal to s. Exemplarily, for any one of the t write ports, a data path is established between the write port and a read port.

[0200] This configuration helps reduce the area of ​​the first forward network and helps reduce the area of ​​the vector processing device.

[0201] In some embodiments, the vector processing device further includes: a control status register; the control status register is used to store control instructions, where the control instructions are vector instructions used to adjust pipeline configuration.

[0202] In some embodiments, there is a transmission path for control instructions between the control status register and at least one pipeline; the pipeline is used to adjust the operation logic of the pipeline according to the control signal corresponding to the control instruction after receiving the control signal corresponding to the control instruction.

[0203] In some embodiments, the control state register may be referred to as a vector control state register (VCSR), which is used to set the pipeline. Optionally, there is a transmission path for control instructions between the control state register and any one of the multiple pipelines. For example, the multiple pipelines include three pipelines, namely pipeline0, pipeline1 and pipeline2; then there is a transmission path for control instructions between the control state register and pipeline0, a transmission path for control instructions between the control state register and pipeline1, and a transmission path for control instructions between the control state register and pipeline2. The control instruction may be referred to as a control state register read and write instruction. Optionally, the control instruction is used to adjust the pipeline's processing method for different types of data. Exemplarily, when the data type of the vector data to be processed changes, a control signal of the control instruction is sent to the pipeline through the control state register to change the pipeline's processing method for the vector data.

[0204] There is a control signal transmission path between the vector decoding unit and the control status register. In the process of broadcasting the control signal corresponding to the vector instruction, the vector decoding unit sends the control signal corresponding to the vector instruction to the control status register through the control signal transmission path. If the vector instruction is a control instruction, the control status register determines that the control signal is a valid signal, and the control status register transmits the control signal corresponding to the control instruction to the pipeline configured for the control instruction through the control instruction transmission path.

[0205] By setting the control status register, the pipeline can be set according to actual needs, which helps to improve the flexibility of the pipeline setting process.

[0206] The pipeline is introduced and explained through several embodiments below.

[0207] In some embodiments, the plurality of pipelines include at least one of the following: at least one first pipeline and at least one second pipeline; the first pipeline is used to process vector data; and the second pipeline is used to perform logic processing on Boolean data.

[0208] The first pipeline is the pipeline used to perform mathematical elements on vector data in the above embodiment.

[0209] Optionally, the first pipeline is used to perform arithmetic operations on the vector data, and the arithmetic operations mainly include: addition, subtraction, multiplication and division operations, fused multiplication and addition operations, comparison operations, exponentiation operations, square root operations, etc. Exemplarily, the vector data processed by the first pipeline can be floating point numbers or fixed point numbers. For example, each numerical value included in the vector data is a 32-bit floating point number. For another example, each numerical value included in the vector data is a 16-bit floating point number.

[0210] Optionally, the first pipeline includes at least one operation unit, and different operation units are used to perform different types of arithmetic operations. For example, the first pipeline includes two operation units, where operation unit 1 is used to perform addition, subtraction, multiplication and division operations, and operation unit 2 is used to perform fused multiplication and addition operations.

[0211] Exemplarily, the functions and numbers of operation units included in different first pipelines are different; the numbers of arithmetic logic units and registers included in different operation units are different, which are not limited in the present application.

[0212] The second pipeline is used to perform logic processing on Boolean data, and the logic processing includes "and", "or", "not" and the like.

[0213] In some embodiments, a forward pass network is provided in the pipeline, and the forward pass network establishes a data transmission path between the data outlet of the pipeline and the inlet of the pipeline. Optionally, a forward pass network is provided in the first pipeline, and a forward pass network is provided in the second pipeline.

[0214] The following takes the first pipeline as an example to introduce the setting of the forward network in the pipeline.

[0215] In some embodiments, a second forward-pass network is provided in the first pipeline; the second forward-pass network is used to transfer the processing result outputted from the outlet of the first operation unit in the first pipeline to the inlet of the first pipeline, the inlet of the first pipeline is used to input the vector data to be processed, and the first operation unit is used to complete the basic floating-point operation on the vector data to be processed.

[0216] The first operation unit may be any one of the multiple operation units included in the first pipeline. Optionally, the first operation unit is the most frequently used operation unit in the first pipeline, for example, the first operation unit is used to complete addition, subtraction and multiplication operations.

[0217] The outlet of the first operation unit is used to output a processing result obtained by the first operation unit processing the vector data.

[0218] In some embodiments, the multiple pipelines include multiple first pipelines for performing arithmetic operations on vector data, and the second forward network can act on one first pipeline or multiple first pipelines.

[0219] Optionally, when the second forward network acts on a first pipeline, the second forward network is used to establish a transmission path for vector data between the exit of the first pipeline and the entrance of the first pipeline. For example, for the first pipeline 1, the second forward network is used to transmit the processing result output by the exit of the first operation unit in the first pipeline 1 to the entrance of the first pipeline 1, so that the result obtained by the first operation unit in the first pipeline in the i-th clock cycle can be used as input data of any operation unit in the first pipeline in the i+1-th clock cycle at the earliest, which helps to improve the transmission efficiency of vector data in the vector processing device.

[0220] Figure 6 is a schematic diagram of a second feedforward network provided by an exemplary embodiment of the present application.

[0221] like Figure 6 As shown, there is a second forward network between the exit of the first operation unit in the pipeline and the entrance of the pipeline.

[0222] Optionally, when the second forward-passing network acts on multiple first pipelines, the second forward-passing network is used to respectively establish transmission paths for vector data between an exit in the first pipeline and entrances of the multiple first pipelines.

[0223] Figure 7 is a schematic diagram of a second feedforward network provided by another exemplary embodiment of the present application.

[0224] There is a second forward pass network between the exit of the first operation unit in pipeline 0 and the entrance of pipeline 0. There is a second forward pass network between the exit of the first operation unit in pipeline 0 and the entrance of pipeline 1. There is a second forward pass network between the exit of the first operation unit in pipeline 1 and the entrance of pipeline 0. There is a second forward pass network between the exit of the first operation unit in pipeline 1 and the entrance of pipeline 1. This makes the transmission of vector data more efficient.

[0225] By establishing a transmission path for vector data between the exit of the operation unit in the pipeline and the entrance of the pipeline, compared with the setting of outputting the processing result of the operation unit through the pipeline, it is helpful to reduce the data transmission delay of transmitting the processing result calculated by the operation unit in the pipeline, and help improve the data transmission efficiency of the vector processing device. Furthermore, for two vector instructions with a dependency relationship, the processing result processed by the operation unit is transmitted to the entrance of the pipeline, so that the subsequent vector instructions do not need to obtain the dependent data from the vector register, which helps to reduce the waiting time for issuing subsequent instructions, that is, reduce the generation of bubbles.

[0226] The connection relationship between the vector processing device and the external device is described below through several embodiments. The vector processing device needs to obtain data from at least two devices, and the data includes scalar data (ie, scalar operands) and vector data.

[0227] In some embodiments, there is an operand transmission path between the vector processing device and the scalar processor, and there is a vector data transmission path between the vector processing device and the vector memory; the scalar processor is used to transmit the instruction packet to the instruction buffer in the vector processing device after executing the scalar instruction; the vector memory is used to provide data related to the vector instruction to the register unit, and to store data related to the vector instruction.

[0228] The scalar processor is used to execute the scalar instruction and obtain the processing result corresponding to the scalar instruction. The processing result corresponding to the scalar instruction can be used as the scalar operand required in the execution process of the vector instruction, that is, the operand mentioned in the above embodiment. Optionally, the scalar processor transmits the operand to the vector processing device through the operand transmission path. For the specific content of the operand acquisition method, please refer to the above embodiment of the operand queue.

[0229] Vector memory refers to the storage space outside the vector processing device. Optionally, according to the classical computer architecture, the vector processing device in this application refers to the core in the vector processor, which is used to complete the processing of vector type data. Vector memory refers to the storage space in the vector processor, that is, L1Menmory.

[0230] In some embodiments, the vector memory is used to provide data related to the vector instruction to the register unit, that is, when the vector processing device starts working, the data in the vector register and the prediction register are all from the vector memory. Optionally, the vector processing device and the vector register need to be completed through the vector loading storage unit in the vector processing device. For the specific content of this process, please refer to the next embodiment.

[0231] When the vector processing device provided by the present application executes multiple vector instructions in parallel in one clock cycle, data interaction can be completed through the register unit in the vector processing device. When the scale of data interaction is large, data interaction between vector instructions can be completed through the vector memory. Since the data reading and writing speed of L1 Menmory is fast, this setting will not affect the data interaction efficiency between the vector processing device and the outside too much.

[0232] The following describes several embodiments of the configuration for implementing data transmission between the vector processing device and the vector memory.

[0233] In some embodiments, the vector processing device further includes: a vector load storage unit; the vector load storage unit is used to transfer data related to the vector instruction between the vector processing device and the vector memory.

[0234] Optionally, there is a first data transmission path between the data transmission path and the vector memory, and the vector load storage unit reads data related to the vector instruction, such as vector data and Boolean data, from the vector memory through the first data transmission path; there is a second data transmission path between the vector load storage unit and the register unit, and the vector load storage unit transfers the data read from the vector memory to the register unit through the second data transmission path.

[0235] Optionally, the vector load storage unit reads data related to the vector instruction from the register unit through the second data transmission path, and transmits the data related to the vector instruction to the vector memory through the first data transmission path.

[0236] In some embodiments, the vector load storage unit includes at least one of the following: at least one vector load (VLD) buffer, at least one vector store (VST) buffer, and a converged access register. The vector load buffer is used to read data related to the vector instruction from the vector memory through a load path in a first data transmission path, the vector store buffer is used to store data related to the vector instruction to the vector memory through a storage path in the first data transmission path, and the converged access register is used to accelerate the converged hash memory access operation.

[0237] Optionally, when the vector load storage unit includes multiple vector load buffers, different vector load buffers have independent load paths to the vector registers. Optionally, when the vector load storage unit includes multiple vector storage buffers, different vector storage buffers have independent transmission paths to the vector registers.

[0238] Figure 8 It is a structural diagram of a vector processing device provided by an exemplary embodiment of the present application.

[0239] The vector processing device is externally connected to a scalar processor and a vector memory. The vector memory is used to store data related to vector instructions, and the data related to vector instructions stored in the vector register and the prediction register can be read from the vector memory. The scalar processor is used to process the scalar instruction and transmit the operand to the operand buffer in the vector processing device. The scalar processor is also used to send the instruction packet including the vector instruction executed in the same clock cycle to the instruction buffer in the vector processing device.

[0240] The vector processing device includes an instruction buffer, an operand buffer, a selection unit, a vector decoding unit, a register unit, three pipelines (pipeline 0, pipeline 1 and pipeline 2), a control status register and a vector load storage unit.

[0241] The instruction buffer may be referred to as a vector instruction queue, which is used to obtain instruction packets from a scalar processor, and there is no dependency between the vector instructions in the instruction packet.

[0242] The vector decoding unit includes: a decoder, a scoreboard, a confusion detector and an instruction packet register. The decoder decodes the instruction packet to obtain the control signals and immediate values ​​corresponding to each vector instruction in the instruction packet. Optionally, the decoder transmits the control signals corresponding to each vector instruction to the instruction packet register, and transmits the immediate values ​​corresponding to each vector instruction to the selection unit. The scoreboard provides the execution status of the vector instruction being executed to the confusion detector, so that the confusion detector determines whether there is a dependency relationship between the vector instruction being executed and each vector instruction in the instruction packet according to the execution status of the vector instruction being executed, and determines whether to broadcast the control signals corresponding to each vector instruction in the instruction packet in the current clock cycle.

[0243] If there is a dependency relationship between the vector instruction being executed and the vector instructions in the instruction packet, the instruction packet register stores the control signals corresponding to each vector instruction in the instruction packet in the current clock cycle. If there is no dependency relationship between the vector instruction being executed and each vector instruction in the instruction packet, the vector decoding unit broadcasts the control signals corresponding to each vector instruction to the register unit and the three pipelines in the current clock cycle.

[0244] Optionally, the register unit includes a vector register and a prediction register. In one example, the vector register includes a vector register body of 32 entries (for storing vector data), and the vector register is provided with 5 read ports and 4 write ports; the prediction register includes a prediction register body of 8 entries (for storing Boolean data), and the vector register is provided with 5 read ports and 2 write ports.

[0245] Exemplarily, both the vector register and the prediction register are provided with a forward pass network, specifically a first forward pass network. Taking the vector register as an example, the first forward pass network is used to establish a transmission path for vector data between the read port and the write port of the vector register. For the specific content of this part, please refer to the above embodiment.

[0246] If the register unit determines that the control signal is a valid control signal, the register unit performs a read / write operation of the operation data based on the valid control signal; if the register unit determines that the control signal is an invalid control signal, the register unit ignores the received control signal.

[0247] Pipeline 0 and pipeline 1 are used to perform arithmetic operations on vector data. Pipeline 2 is used to perform logical processing on Boolean data. Pipeline 0 and pipeline 1 include multiple operation units. For example, pipeline 0 includes an operation unit for addition, subtraction, and multiplication, and an operation unit for fused multiplication and addition. Taking pipeline 0 as an example, if pipeline 0 determines that the control signal is a valid control signal, it performs arithmetic operations on the vector data based on the valid control signal. If it determines that the control signal is an invalid control signal, it ignores the received control signal.

[0248] Optionally, pipeline 0 and pipeline 1 are provided with a forward pass network, specifically a second forward pass network. For details of this part, please refer to the above embodiment, which will not be described here. The control state register is used to obtain control instructions from the vector decoding unit and transmit the control instructions to the corresponding pipeline.

[0249] The vector load storage unit is used to connect the register unit (including the vector register and the prediction register) with the apparent memory. In this embodiment, the vector load storage unit includes two vector carrier buffers, a vector storage buffer and a convergence access unit.

[0250] For specific details about the various components of the vector processing device, please refer to the above embodiments.

[0251] Fig. 9 It is a data flow diagram of a vector processing device provided by an exemplary embodiment of the present application.

[0252] D1 indicates that the vector load storage unit loads the source data from the vector memory into the vector register through the VLD instruction.

[0253] D2a indicates that the first vector instruction completes the calculation in pipeline 0 and writes back to the vector register.

[0254] D2b indicates that the second vector instruction completes the calculation in pipeline 1 and writes back to the vector register.

[0255] D3 indicates that the vector load storage unit moves data from the vector register to the vector memory through the VST instruction.

[0256] The following is an embodiment of the method of the present application. For details not disclosed in the embodiment of the method of the present application, please refer to the embodiment of the vector processing device of the present application. Fig.10 It is a flowchart of an instruction processing method applied to a vector processing device provided by an exemplary embodiment of the present application.

[0257] The vector processing device includes: an instruction buffer, a vector decoding unit, a register unit and a plurality of pipelines; the instruction processing method applied to the vector processing device may include steps (1010-1040).

[0258] Step 1010: The instruction buffer stores at least one instruction packet to be executed, each instruction packet including a plurality of vector instructions that can be executed in parallel.

[0259] Step 1020: the vector decoding unit decodes each vector instruction included in the instruction packet to obtain a control signal corresponding to each vector instruction, and broadcasts the control signal corresponding to each vector instruction to the register unit and multiple pipelines within one clock cycle.

[0260] In step 1030 , the register unit stores data related to the vector instruction.

[0261] Step 1040: The plurality of pipelines process the data related to the vector instruction according to the control signal corresponding to the vector instruction to obtain the processing result corresponding to the vector instruction.

[0262] For the specific content of this embodiment, please refer to the above embodiment, which will not be repeated here.

[0263] In some embodiments, the vector decoding unit includes: a decoder, a scoreboard, and a confusion detector; step 1020 may also include the following sub-steps:

[0264] In sub-step 1022, the decoder decodes the instruction packet to obtain the immediate values ​​and control signals corresponding to each vector instruction in the instruction packet.

[0265] In sub-step 1024, the scoreboard records the execution status of at least one vector instruction being executed, where the control signal corresponding to the vector instruction being executed is broadcast by the vector decoding unit before the clock cycle.

[0266] In sub-step 1026, the confusion detector determines the dependency between each vector instruction in the instruction packet and the vector instruction being executed, so that when there is no dependency between each vector instruction in the instruction packet and the vector instruction being executed, the control signal corresponding to each vector instruction is broadcast to the register unit and multiple pipelines within one clock cycle.

[0267] In some embodiments, the vector decoding unit also includes: an instruction packet register; and after sub-step 1026, sub-step 1028 is also included, in which the instruction packet register stores control signals corresponding to each vector instruction in the instruction packet before the execution of the executing vector instruction is completed, when there is a dependency relationship between at least one vector instruction in the instruction packet and any vector instruction being executed.

[0268] In some embodiments, the vector processing device also includes: at least one operand buffer and at least one selection unit; the method also includes: when the vector instruction is a first vector instruction that performs mixed operations on vector data and operands, the operand buffer stores the operands required to be processed by the first vector instruction; the selection unit selects target data from the operands and the immediate numbers corresponding to the first vector instruction according to the first vector instruction, the target data being the operand or the immediate number corresponding to the first vector instruction; and a transmission path for the target data exists between the selection unit and the pipeline.

[0269] In some embodiments, the register unit includes at least one of the following: a vector register, a prediction register; the method also includes storing vector data related to the vector instruction through the vector register by the vector processing device; and storing Boolean data related to the vector instruction through the prediction register by the vector processing device.

[0270] In some embodiments, a first forward pass network is provided in the vector register, and the method further includes obtaining, through the first forward pass network, vector data generated by the pipeline and not written into the vector register.

[0271] In some embodiments, p read ports and q write ports are provided in the vector register, where p and q are positive integers; the method further includes: reading vector data from the vector register through the read port in the vector register, and writing the vector data into the vector register through the write port in the vector register; wherein the first forward network is used to establish a transmission path for the vector data between the write port and the read port.

[0272] In some embodiments, the vector processing device further includes: a control status register; the method further includes: storing a control instruction via the control status register, the control instruction being a vector instruction for adjusting a pipeline configuration.

[0273] In some embodiments, there is a transmission path for control instructions between the control status register and at least one pipeline; the method also includes adjusting the operation logic of the pipeline according to the control signal corresponding to the control instruction after the pipeline receives the control signal corresponding to the control instruction.

[0274] In some embodiments, the plurality of pipelines include at least one of the following: at least one first pipeline and at least one second pipeline; the method further includes: processing vector data through the first pipeline; and performing logical processing on Boolean data through the second pipeline.

[0275] In some embodiments, a second forward-passing network is provided in the first pipeline; the method further includes: passing the processing result outputted from the outlet of the first operation unit in the first pipeline to the inlet of the first pipeline through the second forward-passing network, the inlet of the first pipeline is used to input the vector data to be processed, and the first operation unit is used to complete the basic floating-point operation on the vector data to be processed.

[0276] In some embodiments, there is an operand transmission path between the vector processing device and the scalar processor, and there is a vector data transmission path between the vector processing device and the vector memory; the method also includes: after the scalar processor completes the execution of the scalar instruction, the instruction packet is transmitted to the instruction buffer in the vector processing device; the data related to the vector instruction is provided to the register unit through the vector memory, and the data related to the vector instruction is stored.

[0277] In some embodiments, the vector processing device further comprises: a vector load storage unit; and the method further comprises, through the vector load storage unit, transmitting data related to the vector instruction between the vector processing device and the vector memory.

[0278] The embodiment of the present application further provides a chip, the electronic chip comprising the vector processing device as described above. Optionally, the chip comprises the vector processing device and a memory.

[0279] The embodiment of the present application also provides an electronic device, which includes the vector processing device as described above. Optionally, the electronic device includes a chip, which includes a memory and a hardware management module. The hardware management module is used to manage the storage space of the memory using the solution provided in the above embodiment.

[0280] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0281] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent switching, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A vector processing device, characterized in that: The vector processing device comprises: an instruction buffer, a vector decoding unit, a register unit and a plurality of pipelines; The instruction buffer is used to store at least one instruction packet to be executed, each of which includes a plurality of vector instructions that can be executed in parallel; The vector decoding unit is used to decode each of the vector instructions included in the instruction packet to obtain a control signal corresponding to each of the vector instructions, and broadcast the control signal corresponding to each of the vector instructions to the register unit and the plurality of pipelines within one clock cycle; The register unit is used to store data related to the vector instruction; The pipeline is used to process data related to the vector instruction according to a control signal corresponding to the vector instruction to obtain a processing result corresponding to the vector instruction.

2. The vector processing device according to claim 1, characterized in that: The vector decoding unit includes: a decoder, a scoreboard and a confusion detector; The decoder is used to decode the instruction packet to obtain the immediate value and control signal corresponding to each of the vector instructions in the instruction packet; The scoreboard is used to record the execution status of at least one vector instruction being executed, and the control signal corresponding to the vector instruction being executed is broadcast by the vector decoding unit before the clock cycle; The confusion detector is used to determine the dependency between each of the vector instructions in the instruction packet and the vector instruction being executed, so that when there is no dependency between each of the vector instructions in the instruction packet and the vector instruction being executed, the control signals corresponding to each of the vector instructions are broadcast to the register unit and the multiple pipelines within one clock cycle.

3. The vector processing device according to claim 2, characterized in that: The vector decoding unit further includes: an instruction packet register; The instruction packet register is used to store control signals corresponding to each of the vector instructions in the instruction packet before the execution of the vector instruction in execution is completed, when there is a dependency relationship between at least one of the vector instructions in the instruction packet and any one of the vector instructions in execution.

4. The vector processing device according to claim 2, characterized in that: The vector processing device further comprises: at least one operand buffer and at least one selection unit; The operand buffer is used for storing operands required to be processed by the first vector instruction when the vector instruction is a first vector instruction that performs mixed operations on vector data and operands; The selection unit is used to select target data from the operand and the immediate value corresponding to the first vector instruction according to the first vector instruction, and the target data is the operand or the immediate value corresponding to the first vector instruction; a transmission path for the target data exists between the selection unit and the pipeline.

5. The vector processing device according to claim 1, characterized in that: The register unit includes at least one of the following: a vector register and a prediction register; The vector register is used to store vector data related to the vector instruction; The prediction register is used to store Boolean data related to the vector instruction.

6. The vector processing device according to claim 5, characterized in that: A first forward pass network is arranged in the vector register, and the first forward pass network is used to obtain vector data generated by the pipeline and not written into the vector register.

7. The vector processing device according to claim 6, characterized in that: The vector register is provided with p read ports and q write ports, where p and q are positive integers; The read port is used to read the vector data from the vector register, and the write port is used to write the vector data into the vector register; The first forward network is used to establish a transmission path for the vector data between the write port and the read port.

8. The vector processing device according to claim 1, characterized in that: The vector processing device further comprises: a control status register; The control status register is used to store control instructions, and the control instructions are vector instructions used to adjust the pipeline configuration.

9. The vector processing device according to claim 8, characterized in that: There is a transmission path for the control instruction between the control status register and at least one of the pipelines; The pipeline is used to adjust the operation logic of the pipeline according to the control signal corresponding to the control instruction after receiving the control signal corresponding to the control instruction.

10. The vector processing device according to claim 1, characterized in that: The plurality of pipelines include at least one of the following: at least one first pipeline, at least one second pipeline; The first pipeline is used to process vector data; The second pipeline is used to perform logic processing on Boolean data.

11. The vector processing device according to claim 10, characterized in that: A second forwarding network is provided in the first pipeline; The second forward network is used to transfer the processing result output by the outlet of the first operation unit in the first pipeline to the inlet of the first pipeline, the inlet of the first pipeline is used to input the vector data to be processed, and the first operation unit is used to complete the basic floating-point operation on the vector data to be processed.

12. The vector processing device according to claim 1, characterized in that: There is an operand transmission path between the vector processing device and the scalar processor, and there is a vector data transmission path between the vector processing device and the vector memory; The scalar processor is used to transmit the instruction packet to the instruction buffer in the vector processing device after executing the scalar instruction; The vector memory is used to provide data related to the vector instruction to the register unit and store data related to the vector instruction.

13. The vector processing device according to claim 12, characterized in that: The vector processing device further comprises: a vector loading storage unit; The vector load storage unit is used to transmit data related to the vector instruction between the vector processing device and the vector memory.

14. A chip, characterized in that: The chip comprises a memory and a vector processing device as claimed in any one of claims 1 to 10.

15. An electronic device, characterized in that: The electronic device comprises the vector processing device according to any one of claims 1 to 10.

16. An instruction processing method applied to a vector processing device, characterized in that: The vector processing device comprises: an instruction buffer, a vector decoding unit, a register unit and a plurality of pipelines; the method comprises: The instruction buffer stores at least one instruction packet to be executed, each of the instruction packets including a plurality of vector instructions executable in parallel; The vector decoding unit decodes each of the vector instructions included in the instruction packet to obtain a control signal corresponding to each of the vector instructions, and broadcasts the control signal corresponding to each of the vector instructions to the register unit and the plurality of pipelines within one clock cycle; The register unit stores data related to the vector instruction; The pipeline processes data related to the vector instruction according to a control signal corresponding to the vector instruction to obtain a processing result corresponding to the vector instruction.

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