A Sampling Method, Controller, Device, and System for Internal Signals of a Chip

Abstract

A method for sampling internal signals of a chip, a controller, a device, and a system provided by an embodiment of the present invention have the following beneficial effects: By receiving an internal signal sequence of the chip; if an idle identifier is received, a first level is output according to a time length T0; if a logical coding signal carrying logical information 0 is received, a second level is output according to a time length T1 and a first level is output according to a time length T2; if a logical coding signal carrying logical information 1 is received, a second level is output according to a time length T2 and a first level is output according to a time length T1; the first level and / or the second level are output to an off-chip acquisition device through a single pin to acquire the internal signals of the chip according to a time length T3. The present invention uses a single pin to realize serial output and acquisition of signals, without occupying a large number of pins to connect to an on-chip memory, saving pin resources, and getting rid of the dependence on internal storage, improving the integrity of the acquired signals.

Description

Technical Field

[0001] The present invention relates to the field of chip debugging, and in particular to a method for sampling internal signals of a chip, a controller, a device, and a system. Background Art

[0002] In the development and debugging stage of a chip, it is usually necessary to send a large number of internal signals of the chip to the outside of the chip for data analysis. The internal signal sequence of the chip can be temporarily stored in the on-chip memory, and then the off-chip sampling device reads the on-chip data through the memory access bus of multiple pins. This method will occupy multiple pins of the chip and has a dependency on the on-chip storage. The number of pins of the chip is a precious resource, and the fewer pins occupied, the better. Moreover, the on-chip storage capacity is limited and cannot store all information.

[0003] As can be seen from the above description, the current method for sampling internal signals of a chip occupies a large amount of pin resources and is limited by the internal storage capacity. How to reduce the pin resources occupied by the sampling of internal signals of a chip and improve the integrity of chip signal sampling is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] In order to overcome the deficiencies of the existing method for sampling internal signals of a chip, which occupies many pins and depends on internal storage, the present invention provides a method for sampling internal signals of a chip, a controller, a device, and a system.

[0005] To achieve the above object, according to the first aspect of the present invention, an embodiment of the present invention provides a method for sampling internal signals of a chip, which is applied to a signal output controller. The method includes the following steps:

[0006] Receiving an internal signal sequence of the chip, where the internal signal sequence of the chip includes an idle identifier that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1;

[0007] If an idle identifier is received, output a first level according to a time length T0;

[0008] If a logic coding signal that carries logic information 0 is received, output a second level according to a time length T1 and output a first level according to a time length T2;

[0009] If a logic coding signal that carries logic information 1 is received, output a second level according to a time length T2 and output a first level according to a time length T1;

[0010] The first level and / or the second level are output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal signals of the chip according to a time length T3;

[0011] Wherein, T0>T1>T2>T3, and the first level and the second level are different level signals.

[0012] Optionally, when the first level is a high level, the second level is a low level.

[0013] Optionally, when the first level is a low level, the second level is a high level.

[0014] According to a second aspect of the present invention, an embodiment of the present invention provides a method for sampling internal signals of a chip, which is applied to an off-chip acquisition device. The method includes the following steps:

[0015] Receiving the first level and / or the second level output by a preset single-pin signal output controller; wherein, the first level and / or the second level output by the signal output controller include: the signal output controller receives an internal signal sequence of the chip, and the internal signal sequence of the chip includes an idle identifier that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if an idle identifier is received, output the first level according to a time length T0; if a logic coding signal that carries logic information 0 is received, output the second level according to a time length T1 and output the first level according to a time length T2; if a logic coding signal that carries logic information 1 is received, output the second level according to a time length T2 and output the first level according to a time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals;

[0016] If P first levels are sampled, no information needs to be extracted, where P is an integer obtained by rounding down T0 / T3.

[0017] If a combination of 1 first level and M second levels is sampled, extract logic information 0, where M is an integer obtained by rounding down T1 / T3.

[0018] If a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, extract logic information 1, where N is an integer obtained by rounding down T2 / T3.

[0019] Wherein, P>M+1, and M>N+1.

[0020] Optionally, when the first level is a high level, the second level is a low level.

[0021] Optionally, when the first level is a low level, the second level is a high level.

[0022] According to a third aspect of the present invention, an embodiment of the present invention further provides a signal output controller, including:

[0023] A receiving module, configured to receive an internal chip signal sequence, where the internal chip signal sequence includes an idle identifier that does not carry information, a logical coding signal that carries logical information 0, and a logical coding signal that carries logical information 1;

[0024] An encoding module, configured to output a first level according to a time length T0 if an idle identifier is received; output a second level according to a time length T1 and output a first level according to a time length T2 if a logical coding signal that carries logical information 0 is received; output a second level according to a time length T2 and output a first level according to a time length T1 if a logical coding signal that carries logical information 1 is received;

[0025] An output module, configured to output the first level and / or the second level to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal chip signal according to a time length T3; where T0>T1>T2>T3, and the first level and the second level are different level signals.

[0026] Optionally, when the first level is a high level, the second level is a low level; or when the first level is a low level, the second level is a high level.

[0027] According to a fourth aspect of the present invention, an embodiment of the present invention further provides an off-chip acquisition device, including:

[0028] An acquisition module, configured to receive the first level and / or the second level output by a signal output controller through a preset single pin; where the first level and / or the second level output by the signal output controller includes: the signal output controller receives an internal chip signal sequence, where the internal chip signal sequence includes an idle identifier that does not carry information, a logical coding signal that carries logical information 0, and a logical coding signal that carries logical information 1; output a first level according to a time length T0 if an idle identifier is received; output a second level according to a time length T1 and output a first level according to a time length T2 if a logical coding signal that carries logical information 0 is received; output a second level according to a time length T2 and output a first level according to a time length T1 if a logical coding signal that carries logical information 1 is received; and T0>T1>T2>T3, and the first level and the second level are different level signals;

[0029] A decoding module, configured to not extract information if P first levels are sampled, where P is an integer obtained by rounding down T0 / T3; extract logical information 0 if a combination of 1 first level and M second levels is sampled, where M is an integer obtained by rounding down T1 / T3; extract logical information 1 if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, where N is an integer obtained by rounding down T2 / T3; where P>M+1, and M>N+1;

[0030] When the first level is a high level, the second level is a low level; or when the first level is a low level, the second level is a high level.

[0031] According to the fifth aspect of the present invention, an embodiment of the present invention further provides a sampling system for internal signals of a chip. The system includes the signal output controller of the above embodiment and the off-chip acquisition device of the above embodiment. The signal output controller is communicatively connected to the off-chip acquisition device through a preset single pin.

[0032] As described above, a sampling method, a controller, a device, and a system for internal signals of a chip provided by an embodiment of the present invention have the following beneficial effects: by receiving an internal signal sequence of the chip, the internal signal sequence of the chip includes an idle identifier that does not carry information, a logical coding signal that carries logical information 0, and a logical coding signal that carries logical information 1; if an idle identifier is received, a first level is output according to a time length T0; if a logical coding signal that carries logical information 0 is received, a second level is output according to a time length T1 and a first level is output according to a time length T2; if a logical coding signal that carries logical information 1 is received, a second level is output according to a time length T2 and a first level is output according to a time length T1; the first level and / or the second level are output to the off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal signals of the chip according to a time length T3; wherein, T0>T1>T2>T3. The present invention uses a single pin to realize the serial output and acquisition of signals, without occupying a large number of pins to connect to the on-chip memory, saving pin resources, and getting rid of the dependence on internal storage, improving the integrity of the acquired signals. Description of the Drawings

[0033] Figure 1 is a schematic flowchart of a sampling method for internal signals of a chip executed by a signal output controller provided by an embodiment of the present invention;

[0034] Figure 2 is a schematic structural diagram of an internal signal sequence of a chip provided by an embodiment of the present invention;

[0035] Figure 3 is a schematic diagram of the level of a logical 0 provided by an embodiment of the present invention;

[0036] Figure 4 is a schematic diagram of the level of a logical 1 provided by an embodiment of the present invention;

[0037] Figure 5 is a schematic diagram of the level of a converted internal signal sequence of a chip provided by an embodiment of the present invention;

[0038] Figure 6It is a schematic flowchart of another method for the signal output controller to sample the internal signals of the chip provided by the embodiments of the present invention;

[0039] Figure 7 It is a schematic flowchart of a method for an off-chip acquisition device to sample the internal signals of the chip provided by the embodiments of the present invention;

[0040] Figure 8 It is a schematic diagram of a sampling process provided by the embodiments of the present invention;

[0041] Figure 9 It is a schematic flowchart of another method for an off-chip acquisition device to sample the internal signals of the chip provided by the embodiments of the present invention;

[0042] Figure 10 It is a schematic structural diagram of a signal output controller provided by the embodiments of the present invention;

[0043] Figure 11 It is a schematic structural diagram of an off-chip acquisition device provided by the embodiments of the present invention;

[0044] Figure 12 It is a schematic structural diagram of a chip internal signal sampling system provided by the embodiments of the present invention. Detailed implementation manners

[0045] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0046] Please refer to Figures 1 to 12 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0047] See Figure 1 , which is a schematic flowchart of a method for a signal output controller to sample the internal signals of the chip provided by the embodiments of the present invention. As Figure 1 shown, the embodiments of the present invention illustrate the process of the signal output controller executing this method.

[0048] In specific implementation, the designs, models, and packages of the chips to be sampled are not the same. From a design perspective, the signal output controller can be an integrated circuit unit integrated inside the chip, or the signal output controller can be an integrated circuit unit independent of the chip core, or the signal output controller can also be a controller outside the chip that communicates with the chip; in terms of form, the signal output controller can be a unit circuit with an MCU, or a circuit with other processing units. However, during use, the signal output controller is packaged with the chip core as a whole and provides pins externally. The package structure and form of the signal output controller are not limited in the embodiments of the present invention. The signal output controller can be equipped with a storage unit, or use the storage unit inside the chip to store firmware or programming, so as to execute the corresponding control logic for signal output. In this way, the internal signal sequence of the chip can be sent to the signal output controller for further processing.

[0049] In the first implementation case, the signal output controller encodes the internal signal sequence of the chip. The first level used for encoding is the high level, and the second level is the low level. The detailed process is as follows:

[0050] Step S101: Receive the internal signal sequence of the chip. The internal signal sequence of the chip includes idle signals that do not carry information, logic signals that carry logical information 0, and logic signals that carry logical information 1.

[0051] The signal output controller receives the internal signal sequence sent by the chip. The internal signal sequence of the chip is a signal sequence generated by internal control or calculation of the chip. Specifically, the internal signal sequence of the chip includes idle identifiers that do not carry information, logic encoded signals that carry logical information 0, and logic encoded signals that carry logical information 1.

[0052] See Figure 2 , which is a schematic structural diagram of an internal signal sequence of a chip provided by an embodiment of the present invention. As shown in the figure, the internal signal sequence of the chip includes multiple signal sequences with undefined widths. Each signal sequence (such as signal sequence 1, signal sequence 2... signal sequence N, etc.) further includes logic encoded signals (carrying logical information 0 or logical information 1) and idle identifiers. The entire internal signal sequence of the chip starts with an idle identifier and ends with an idle identifier, and is output to the signal output controller through a single pin in a traversing manner.

[0053] Step S102: If an idle identifier is received, output a high level according to the time length T0.

[0054] When the signal output controller receives an idle identifier, it outputs a continuous high level according to the time length T0. The idle identifier does not carry information.

[0055] Step S103: If a logical coding signal carrying logical information 0 is received, output a low level for a time length T1 and a high level for a time length T2.

[0056] The logical coding signal is the coding signal of the signal sequence that needs to be transmitted inside the chip, encoded with 0 and 1. Therefore, the logical coding signal includes the logical coding signal carrying logical information 0 and the logical coding signal carrying logical information 1.

[0057] When the signal output controller receives the logical coding signal carrying logical information 0, it outputs a low level for a time length T1 and a high level for a time length T2. See Figure 3 , which is a schematic diagram of the level of a logical 0 provided by an embodiment of the present invention. As shown in the figure, logical 0 consists of a low level for time length T1 and a high level for time length T2.

[0058] Step S104: If a logical coding signal carrying logical information 1 is received, output a low level for a time length T2 and a high level for a time length T1.

[0059] When the signal output controller receives the logical coding signal carrying logical information 1, it outputs a low level for a time length T2 and a high level for a time length T1. See Figure 4 , which is a schematic diagram of the level of a logical 1 provided by an embodiment of the present invention. As shown in the figure, logical 1 consists of a low level for time length T2 and a high level for time length T1.

[0060] Step S105: The high level and / or low level is output to the off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal signals of the chip according to the time length T3.

[0061] The signal output controller converts the internal signal sequence of the chip into a combination of high and low levels through the above implementation. See Figure 5 , which is a schematic diagram of the level of the converted internal signal sequence of the chip provided by an embodiment of the present invention. As shown in the figure, taking the internal signal sequence of the chip as an idle identifier, 1010, and an idle identifier as an example, after the signal output controller converts the level, it serially outputs a high level (idle identifier) for a time length T0, a low level for a time length T2, a high level for a time length T1 (logical 1), a low level for a time length T1, a high level for a time length T2 (logical 0), a low level for a time length T2, a high level for a time length T1 (logical 1), a low level for a time length T1, a high level for a time length T2 (logical 0), and a high level for a time length T0 (idle identifier).

[0062] The above high level or low level is output to an off-chip acquisition device through a preset single pin. This preset single pin can use a pin led out by a signal output controller, so that the signal output controller can communicate with the off-chip acquisition device through one pin. The off-chip acquisition device decodes the high level and / or low level output by the signal output controller according to the time length T3, and finally completes the acquisition of the internal signals of the chip.

[0063] In specific implementation, to ensure the accuracy of signal sampling, T0 > T1 > T2 > T3. In an exemplary embodiment, T0 can be configured as 35 ns, T1 can be configured as 20 ns, T2 can be configured as 10 ns, and T3 can be configured as 6 ns.

[0064] As can be seen from the description of the above embodiments, a method for sampling internal signals of a chip provided by an embodiment of the present invention includes receiving an internal signal sequence of the chip, where the internal signal sequence of the chip includes an idle identifier that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1; if an idle identifier is received, a high level is output according to the time length T0; if a logic coding signal that carries logic information 0 is received, a low level is output according to the time length T1 and a high level is output according to the time length T2; if a logic coding signal that carries logic information 1 is received, a low level is output according to the time length T2 and a high level is output according to the time length T1; the high level and / or low level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal signals of the chip according to the time length T3; where T0 > T1 > T2 > T3. The present invention uses a single pin to realize the serial output and acquisition of internal signals of the chip, without occupying a large number of pins to connect to the on-chip memory, saving pin resources, and getting rid of the dependence on internal storage, improving the integrity of the acquired signals.

[0065] In the second implementation case, the signal output controller encodes the internal signal sequence of the chip. The first level used for encoding is a low level and the second level is a high level. The detailed process is as follows:

[0066] See Figure 6 , which is a schematic flowchart of another method for the signal output controller to perform sampling of internal signals of the chip provided by an embodiment of the present invention. As Figure 6 shown, the embodiment of the present invention shows the process of the signal output controller executing this method.

[0067] Step S201: Receive an internal signal sequence of the chip, where the internal signal sequence of the chip includes an idle identifier that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1.

[0068] Step S202: If an idle identifier is received, output a low level according to the time length T0.

[0069] Step S203: If a logical coding signal carrying logical information 0 is received, output a high level for the time length T1 and a low level for the time length T2.

[0070] Step S204: If a logical coding signal carrying logical information 1 is received, output a high level for the time length T2 and a low level for the time length T1.

[0071] Step S205: The high level and / or the low level are output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal signals of the chip according to the time length T3; wherein, T0>T1>T2>T3.

[0072] The difference between the embodiment of the present invention and the foregoing embodiment lies in that the signal output controller has a different level output mode for the internal signals of the chip. The embodiment of the present invention takes the opposite of the level compared with the foregoing embodiment, so that the same effect of converting the internal signal sequence of the chip into a level output is achieved. However, since the low level occupies a longer time, the effect of power consumption saving can be achieved. For other parts that are the same as the foregoing embodiment, reference can be made to the description of the above embodiment, and details will not be described herein again.

[0073] See Figure 7 , which is a schematic flowchart of a method for an off-chip acquisition device to execute sampling of internal signals of a chip provided by an embodiment of the present invention. As Figure 7 shown, the embodiment of the present invention shows the process of the off-chip acquisition device executing this method. The embodiment of the present invention decodes the level output after the signal output controller executes the method for sampling the internal signals of the chip, corresponding to the first implementation case in the embodiment on the signal output controller side, that is, the case where the first level is a high level and the second level is a low level. Figure 1 shown, the embodiment of the present invention shows the process of the off-chip acquisition device executing this method. The embodiment of the present invention decodes the level output after the signal output controller executes the method for sampling the internal signals of the chip, corresponding to the first implementation case in the embodiment on the signal output controller side, that is, the case where the first level is a high level and the second level is a low level.

[0074] Step S301: Receive the high level and / or the low level output by the signal output controller through a preset single pin.

[0075] The high level and / or the low level output by the signal output controller include: the signal output controller receives an internal signal sequence of the chip, and the internal signal sequence of the chip includes an idle identifier not carrying information, a logical coding signal carrying logical information 0, and a logical coding signal carrying logical information 1; if an idle identifier is received, output a high level according to the time length T0; if a logical coding signal carrying logical information 0 is received, output a low level for the time length T1 and a high level for the time length T2; if a logical coding signal carrying logical information 1 is received, output a low level for the time length T2 and a high level for the time length T1; and T0>T1>T2>T3.

[0076] Step S302: If P high levels are sampled, no information needs to be extracted, where P is the integer obtained by taking the floor of T0 / T3.

[0077] After the off-chip acquisition device receives the level output by the signal output controller, it samples the level signal with a time length of T3. Here, the time length T3 can be understood as the period of the acquisition clock of the off-chip acquisition device, that is, the clock with a period of T3 of the off-chip acquisition device samples the received level signal. Specifically, the level signal of the signal output controller is sampled at the rising edge of the acquisition clock, and information is decoded and extracted.

[0078] For the sake of convenience of description, in an exemplary embodiment, if the signal sequence inside the chip is a 4-bit data sequence generated every 1 us, according to the relationship of T0, T1, T2, and T3, the values are taken as follows:

[0079]

[0080] The values of P, M, and N can be calculated as follows:

[0081]

[0082] Among them, P is T0 / T3 = 35 / 6 = 5.8, and the integer obtained by taking the floor is 5; M is T1 / T3 = 20 / 6 = 3.3, and the integer obtained by taking the floor is 3; N is T2 / T3 = 10 / 6 = 1.7, and the integer obtained by taking the floor is 1. Moreover, P, M, and N satisfy: P > M + 1, M > N + 1. The purpose of doing this is to prevent logical confusion during the subsequent decoding process, thereby further ensuring the sampling accuracy.

[0083] According to the above calculation results, if P high levels are sampled, that is, 5 high levels in the above example, it corresponds to the idle identifier in the chip internal signal sequence that does not carry information, and no information needs to be extracted.

[0084] In the specific sampling process, refer to Figure 8 , which is a schematic diagram of a sampling process provided by an embodiment of the present invention. As shown in the figure, in an exemplary embodiment, two 4-bit data 1010 and 0101 inside the chip (not shown, output after the last idle identifier) are output at an interval of 1 us. The signal output controller outputs the level to the off-chip sampling device, and the off-chip sampling device samples the level according to the above sampling clock (with a period of T3). Each rising edge of the clock is sampled. If a high level is sampled, it is recorded as 1. If a low level is sampled, it is recorded as 0, thereby obtaining the acquisition data; further analyzing the acquisition data to obtain the decoded data, and the decoded data corresponds to the signal sequence inside the chip.

[0085] In this step, it can also be seen that P = 5 high levels are collected, that is, corresponding to the collected data 11111 (5 ones), which is decoded as idle, indicating that the internal signal of the chip corresponds to the idle identifier.

[0086] Step S303: If a combination of 1 high level and M low levels is sampled, extract the logical information 0, where M is the integer obtained by rounding down T1 / T3.

[0087] According to the description of the above embodiments, combined with Figure 8 , when a combination of 1 high level and M low levels is sampled, the logical information 0 is extracted. Specifically, in the corresponding figure, for logical 0, 1 high level is collected, and M = 3 low levels are continuously collected. The collected data is 1000 (1 one, 3 zeros). By analyzing this collected data, the decoded data is obtained, and this decoded data corresponds to the logical coding signal (i.e., logical 0) carrying the logical information 0 in the internal signal sequence of the chip.

[0088] Step S304: If a combination of 1 high level, N or N + 1 low levels, and 1 high level is sampled, extract the logical information 1.

[0089] Similarly, combined with Figure 8 , when a combination of 1 high level, N or N + 1 low levels, and 1 high level is sampled, the logical information 1 is extracted. Specifically, in the corresponding figure, for logical 1, it corresponds to 1 high level, 1 low level (N = 1), and 1 high level. The collected data is 101 (1 one, 1 zero, 1 one). By analyzing this collected data, the decoded data is obtained, and this decoded data corresponds to the logical coding signal (i.e., logical 1) carrying the logical information 1 in the internal signal sequence of the chip.

[0090] According to the description of the above embodiments, the correspondence between the states of the internal signal sequence of the sampling chip and the collected data is summarized in the following table:

[0091]

[0092] It should be noted that during the sampling process, in order to avoid the problem of decoding errors caused by repeated counting, in the embodiments of the present invention, the decoding sequence starts from 1. Corresponding to the sampling levels, it starts to judge from the high level. In this way, for logical 0, such as the collected data 10001, if both 1000 and 0001 are considered as logical 0, in the embodiments of the present invention, it starts to judge from the high level, that is, 1000 is confirmed as logical 0, and 0001 is not considered as logical 0, thus avoiding repeated counting, improving the decoding accuracy, and further ensuring the sampling accuracy.

[0093] See Figure 9, which is a schematic flowchart of another method for an off-chip acquisition device to sample internal signals of a chip provided by an embodiment of the present invention. As Figure 9 shown, the embodiment of the present invention shows the process of the off-chip acquisition device executing this method. The embodiment of the present invention decodes the level output after the signal output controller shown in Figure 6 executes the method for sampling internal signals of the chip, corresponding to the second implementation case in the embodiment on the signal output controller side, that is, when the first level is low and the second level is high.

[0094] Step S401: Receive the high level and / or low level output by the signal output controller through a preset single pin.

[0095] The high level and / or low level output by the signal output controller includes: receiving an internal signal sequence of the chip, where the internal signal sequence of the chip includes an idle identifier that does not carry information, a logical coding signal that carries logical information 0, and a logical coding signal that carries logical information 1; if an idle identifier is received, output a low level according to a time length T0; if a logical coding signal that carries logical information 0 is received, output a high level according to a time length T1 and a low level according to a time length T2; if a logical coding signal that carries logical information 1 is received, output a high level according to a time length T2 and a low level according to a time length T1; and T0>T1>T2>T3.

[0096] Step S402: If P low levels are sampled, no information needs to be extracted, where P is the integer obtained by rounding down T0 / T3.

[0097] Step S403: If a combination of 1 low level and M high levels is sampled, extract logical information 0, where M is the integer obtained by rounding down T1 / T3.

[0098] Step S404: If a combination of 1 low level, N or N+1 high levels, and 1 low level is sampled, extract logical information 1, where N is the integer obtained by rounding down T2 / T3; where P>M+1 and M>N+1.

[0099] The difference between the embodiment of the present invention and the foregoing embodiment is that, adapted to the level output by the signal output controller shown in Figure 6 , the acquisition and decoding of the level by the off-chip acquisition device is also in an inverse relationship with the foregoing implementation method. It can also realize the sampling of internal signals of the chip and has the effect of low power consumption. For the same parts between the embodiment of the present invention and the foregoing embodiment, reference can be made to the description of the foregoing embodiment, which will not be repeated here.

[0100] Through the description of the above method embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. And the aforementioned storage medium includes: read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., various media that can store program codes.

[0101] Corresponding to the embodiment of the method for sampling internal signals of a chip provided by the present invention, the present invention also provides a signal output controller.

[0102] See Figure 10 , which is a schematic structural diagram of a signal output controller provided by an embodiment of the present invention. As shown in the figure, the controller includes:

[0103] A receiving module 11, configured to receive an internal signal sequence of the chip, where the internal signal sequence of the chip includes an idle identifier that does not carry information, a logical coding signal that carries logical information 0, and a logical coding signal that carries logical information 1;

[0104] An encoding module 12, configured to output a first level according to a time length T0 if an idle identifier is received; output a second level according to a time length T1 and a first level according to a time length T2 if a logical coding signal that carries logical information 0 is received; output a second level according to a time length T2 and a first level according to a time length T1 if a logical coding signal that carries logical information 1 is received;

[0105] An output module 13, configured to output the first level and / or the second level to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the internal signals of the chip according to a time length T3; where T0>T1>T2>T3, and the first level and the second level are different level signals.

[0106] In the first implementation case, when the first level is a high level, the second level is a low level.

[0107] In the second implementation case, when the first level is a low level, the second level is a high level.

[0108] See Figure 11, which is a schematic structural diagram of an off-chip acquisition device provided by an embodiment of the present invention. As shown in the figure, this device cooperates with the signal output controller in the above embodiment and performs corresponding decoding according to the encoding logic of the first level and the second level, specifically including:

[0109] An acquisition module 21, configured to receive the high level and / or low level output by the signal output controller through a preset single pin; wherein, the high level and / or low level output by the signal output controller includes: the signal output controller receives an internal chip signal sequence, and the internal chip signal sequence includes an idle identifier that does not carry information, a logic encoding signal that carries logic information 0, and a logic encoding signal that carries logic information 1; if the idle identifier is received, the first level is output according to the time length T0; if the logic encoding signal that carries logic information 0 is received, the second level is output according to the time length T1, and the first level is output according to the time length T2; if the logic encoding signal that carries logic information 1 is received, the second level is output according to the time length T2, and the first level is output according to the time length T1; and T0>T1>T2>T3. The first level and the second level are different level signals;

[0110] A decoding module 22, configured to, if P first levels are sampled, no information needs to be extracted, where P is the integer obtained by rounding down T0 / T3; if a combination of 1 first level and M second levels is sampled, extract logic information 0, where M is the integer obtained by rounding down T1 / T3; if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, extract logic information 1, where N is the integer obtained by rounding down T2 / T3; where P>M+1, and M>N+1;

[0111] When the first level is a high level, the second level is a low level; or, when the first level is a low level, the second level is a high level.

[0112] See Figure 12 , which is a schematic structural diagram of a chip internal signal sampling system provided by an embodiment of the present invention. As shown in the figure, this system includes a signal output controller 31 and an off-chip acquisition device 32. The signal output controller 31 and the off-chip acquisition device 32 are communicatively connected through a preset single pin (not marked). In this way, the internal chip signal sequence is received by the signal output controller 31 and encoded according to the method described in the above embodiment, and then sent to the off-chip acquisition device 32 for decoding through the single pin to complete the sampling of the internal chip signal sequence.

[0113] Specifically, the signal output controller 31 includes Figure 10 The receiving module 11, encoding module 12, and output module 13 shown in the figure; the off-chip acquisition device 32 includes Figure 11The acquisition module 21 and the decoding module 22 shown. Among them, the output module 13 is communicatively connected to the acquisition module 21 through a preset single pin.

[0114] The above product can execute the method provided by the embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference can be made to the method provided by the embodiment of the present invention.

[0115] The electronic device in the embodiment of the present invention exists in various forms, including but not limited to:

[0116] (1) Mobile communication devices: The characteristics of such devices are that they have mobile communication functions and mainly aim to provide voice and data communication. Such terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones, etc.

[0117] (2) Ultra-mobile personal computer devices: Such devices belong to the category of personal computers, have computing and processing functions, and generally also have the characteristic of mobile Internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as iPad.

[0118] (3) Portable entertainment devices: Such devices can display and play multimedia content. Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, and smart toys and portable in-vehicle navigation devices.

[0119] (4) Servers: Devices that provide computing services. The composition of a server includes a processor, hard disk, memory, system bus, etc. A server is similar to a general computer architecture, but due to the need to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0120] (5) Other electronic devices with data interaction functions.

[0121] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the device or system embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description of the method embodiments. The device and system embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.

[0123] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0124] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for sampling a chip internal signal, characterized in that: Applicable to signal output controllers, including: Receive a chip internal signal sequence, wherein the chip internal signal sequence includes an idle marker that does not carry information, a logic coded signal that carries logic information 0, and a logic coded signal that carries logic information 1, and the chip internal signal sequence starts with the idle marker and ends with the idle marker; If an idle flag is received, a first level is output according to the time length T0; If a logic coded signal carrying logic information 0 is received, the second level is output according to the time length T1 and the first level is output according to the time length T2; If a logic coded signal carrying logic information 1 is received, the second level is output according to the time length T2 and the first level is output according to the time length T1; The first level and / or the second level is output to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the chip internal signal according to the time length T3, including: if P first levels are sampled, no information extraction is required, wherein P is an integer rounded down from T0 / T3; if a combination of 1 first level and M second levels is sampled, logic information 0 is extracted, wherein M is an integer rounded down from T1 / T3; if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, logic information 1 is extracted, wherein N is an integer rounded down from T2 / T3; P>M+1, and M>N+1; Among them, T0>T1>T2>T3, the first level and the second level are different level signals.

2. The chip internal signal sampling method according to claim 1, characterized in that: Applicable to signal output controllers, including: When the first level is a high level, the second level is a low level.

3. The chip internal signal sampling method according to claim 1, characterized in that: Applicable to signal output controllers, including: When the first level is a low level, the second level is a high level.

4. A method for sampling a chip internal signal, characterized in that: Applied to off-chip acquisition equipment, including: The first level and / or the second level output by the signal output controller is received by a preset single pin; wherein the first level and / or the second level output by the signal output controller includes: the signal output controller receives a chip internal signal sequence, wherein the chip internal signal sequence includes an idle marker that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1, and the chip internal signal sequence starts with an idle marker and ends with an idle marker; if an idle marker is received, a first level is output according to a time length T0; if a logic coding signal that carries logic information 0 is received, a second level is output according to a time length T1, and a first level is output according to a time length T2; if a logic coding signal that carries logic information 1 is received, a second level is output according to a time length T2, and a first level is output according to a time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals; If P first levels are sampled, there is no need to extract information, where P is an integer obtained by rounding down T0 / T3; If a combination of 1 first level and M second levels is sampled, logic information 0 is extracted, where M is an integer obtained by rounding down T1 / T3; If a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, logic information 1 is extracted, where N is an integer obtained by rounding down T2 / T3; Among them, P>M+1, and M>N+1.

5. The method for sampling chip internal signals according to claim 4, characterized in that: Applied to off-chip acquisition equipment, including: When the first level is a high level, the second level is a low level.

6. The method for sampling chip internal signals according to claim 4, characterized in that: Applied to off-chip acquisition equipment, including: When the first level is a low level, the second level is a high level.

7. A signal output controller, characterized in that: include: A receiving module, configured to receive a chip internal signal sequence, wherein the chip internal signal sequence includes an idle marker that carries no information, a logic coded signal that carries logic information 0, and a logic coded signal that carries logic information 1, and the chip internal signal sequence starts with the idle marker and ends with the idle marker; The encoding module is configured to output a first level according to a time length T0 if an idle flag is received; If a logic coded signal carrying logic information 0 is received, the second level is output according to the time length T1 and the first level is output according to the time length T2; If a logic coded signal carrying logic information 1 is received, the second level is output according to the time length T2 and the first level is output according to the time length T1; An output module is used to output the first level and / or the second level to an off-chip acquisition device through a preset single pin, so that the off-chip acquisition device acquires the chip internal signal according to the time length T3, including: if P first levels are sampled, no information extraction is required, wherein P is an integer rounded down from T0 / T3; if a combination of 1 first level and M second levels is sampled, logic information 0 is extracted, wherein M is an integer rounded down from T1 / T3; if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, logic information 1 is extracted, wherein N is an integer rounded down from T2 / T3; P>M+1, and M>N+1; wherein T0>T1>T2>T3, and the first level and the second level are different level signals.

8. The signal output controller according to claim 7, characterized in that: include: When the first level is a high level, the second level is a low level; or, When the first level is a low level, the second level is a high level.

9. An off-chip acquisition device, characterized in that: include: An acquisition module, used for receiving a first level and / or a second level output by a signal output controller through a preset single pin; wherein the first level and / or the second level output by the signal output controller comprises: the signal output controller receives a chip internal signal sequence, wherein the chip internal signal sequence comprises an idle marker that does not carry information, a logic coding signal that carries logic information 0, and a logic coding signal that carries logic information 1, and the chip internal signal sequence starts with an idle marker and ends with an idle marker; if an idle marker is received, a first level is output according to a time length T0; if a logic coding signal that carries logic information 0 is received, a second level is output according to a time length T1, and a first level is output according to a time length T2; if a logic coding signal that carries logic information 1 is received, a second level is output according to a time length T2, and a first level is output according to a time length T1; and T0>T1>T2>T3, the first level and the second level are different level signals; A decoding module, for extracting logic information 0 if P first levels are sampled, where P is an integer rounded down from T0 / T3; extracting logic information 1 if a combination of 1 first level and M second levels is sampled, where N is an integer rounded down from T2 / T3; and extracting logic information 1 if a combination of 1 first level, N or N+1 second levels, and 1 first level is sampled, where N is an integer rounded down from T2 / T3; wherein P>M+1, and M>N+1; When the first level is a high level, the second level is a low level; or, when the first level is a low level, the second level is a high level.

10. A chip internal signal sampling system, characterized in that: It comprises the signal output controller as claimed in claim 7 or 8, and the off-chip acquisition device as claimed in claim 9, wherein the signal output controller is communicatively connected to the off-chip acquisition device via a preset single pin.

Images