Efficient cache management method and device

Abstract

The invention discloses an efficient cache management method, which comprises a system initialization stage, a cache state synchronization stage, a software pre-allocation stage, a data caching and forwarding stage, a state modification stage, a dynamic adjustment stage, a hardware completion reelable ring buffer and related settings, a software communication and data structure initialization stage and a cache state synchronization stage. The hardware monitors in real time and synchronizes buffer state information to the software, the software updates monitoring data accordingly, the software pre-distributes multiple rounds of buffers in sequence according to system requirements and the like and sends an instruction to the hardware, the hardware executes data storage and forwarding according to the instruction, updates and synchronizes the state to the software in real time, the software monitors data and processes the data, and the software sends a state modification instruction to the hardware. After hardware execution, the state is synchronously updated back to software, and the software continuously monitors the system condition and adjusts the cache management strategy as required. According to the method and the device, a rewinding buffer management mechanism is adopted, the software can pre-distribute the buffers for multiple rounds in advance, and the efficiency of distributing the buffers by the software is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of non-volatile memory, and in particular relates to an efficient cache management method and device. Background Art

[0002] Generally, there is a cache management unit in the hardware circuit, which is used to send and recycle the buffer and realize the caching and forwarding of data messages. In non-volatile memory products, cache management is particularly important, which requires the firmware to monitor the cache status and modify the cache status in real time.

[0003] Existing cache management methods and devices are generally implemented in hardware to achieve the purpose of efficient management, or implemented in software to facilitate the CPU to monitor the usage of the cache in real time. This patent provides an efficient cache management method and device, which facilitates firmware monitoring and buffer status modification on the premise of meeting efficient management, so as to achieve better software and hardware collaboration. Summary of the invention

[0004] The purpose of the present invention is to provide an efficient cache management method and device in order to solve the problem that the software allocates buffers in a non-volatile memory product in the existing cache management method and device.

[0005] The technical solution adopted by the present invention is as follows: An efficient cache management method comprises the following steps: During the system initialization phase, the hardware initializes the rewrapable ring buffer, determines its parameters and the mapping relationship between the physical buffer and the virtual buffer and sets the buffer to idle. The software initializes the hardware communication interface and the cache-related information storage structure. During the cache status synchronization phase, the hardware monitors in real time and synchronizes the buffer status to the firmware according to certain rules; In the software pre-allocation phase, the firmware determines the pre-allocation parameters according to the current cache state and combines the system load, data traffic prediction and task priority, and then pre-allocates the buffer in order and sends instructions to the cache management unit. According to the instruction content, the corresponding physical buffer unit is marked as allocated and is ready to receive or forward data packets. In the data caching and forwarding stage, when data arrives, it is stored in the corresponding entity buffer and stored in a ring structure. The real-time update status is synchronized to the firmware, and the firmware monitors the data. In the state modification phase, after the processing is completed, the firmware evaluates the actual scenario and sends a state modification instruction to the hardware, and the hardware executes it and updates the state synchronously; During the dynamic adjustment phase, the firmware continuously monitors the system status and dynamically adjusts the cache management strategy as needed.

[0006] Among them, in the system initialization stage, the cache management unit initializes the wraparound circular buffer, determines the total capacity, division granularity and other parameters of the circular buffer, establishes a mapping relationship with the virtual buffer unit for each physical buffer unit according to the preset mapping rules, and then sets the initial state of all buffer units in the circular buffer to idle, marking them as unallocated and unused, and initializes the relevant registers or storage areas for recording buffer status information.

[0007] Among them, in the cache status synchronization stage, the cache management unit collects the status information of each buffer unit in the circular buffer at a certain time interval or when a specific event is triggered, and then sends the collected status information to the firmware through a pre-established communication interface. The firmware receives the buffer status information from the cache management unit through the communication interface, and then updates the received status information to the corresponding data structure internally used to monitor the cache status.

[0008] Among them, in the software pre-allocation stage, the Firmware allocates virtual buffer units for the upcoming data packets in sequence starting from the starting position of the virtual buffer space according to the wraparound characteristics of the circular buffer and the mapping relationship between the virtual buffer. The Firmware sends the pre-allocation instruction to the hardware cache management unit. The instruction contains the physical buffer unit information corresponding to the pre-allocated virtual buffer unit and the usage of these units. After receiving the pre-allocation instruction from the Firmware, the hardware cache management unit marks the corresponding physical buffer unit as allocated according to the instruction content, and then prepares for the operation of receiving or forwarding data packets.

[0009] Among them, in the data caching and forwarding stage, when a data message arrives, the hardware cache management unit stores the data message in the corresponding allocated physical buffer unit according to the previous pre-allocation instructions of the firmware. During the storage process, the rewinding feature of the circular buffer is utilized. When the storage position reaches the end of the circular buffer, it automatically wraps around to the beginning to continue storing. At the same time, the hardware cache management unit updates the buffer status information in real time and synchronizes the updated status information to the firmware. The firmware monitors the progress of data caching based on the received status update information.

[0010] Among them, in the state modification stage, after the data message processing is completed, according to the needs of the actual scenario, the Firmware decides to modify the relevant buffer state. The Firmware sends a state modification instruction to the hardware cache management unit. After receiving the state modification instruction, the hardware cache management unit updates the state of the corresponding physical buffer unit according to the instruction content and synchronizes the updated state information back to the Firmware.

[0011] Among them, in the dynamic adjustment stage, the firmware can dynamically adjust the pre-allocation strategy according to the system operation status and changes in data traffic. At the same time, the firmware can also dynamically adjust the buffer allocation order according to the priority of different data messages.

[0012] An efficient cache management device includes an on-chip cache SRAM module, a firmware module, a hardware master module, a buffer management unit module and a CPU module. The on-chip cache SRAM module provides physical storage as a retractable circular buffer, and allows the firmware to obtain more available capacity through specific mapping for data message caching and forwarding. The firmware module can monitor the cache status, pre-allocate multiple rounds of buffers in advance and modify the buffer status according to the scenario, master the allocation initiative, and improve software performance. The hardware master module performs data caching and forwarding operations, and interacts with the on-chip cache module to store data. The buffer management unit module is responsible for specific management such as issuing and recycling the buffer of the on-chip cache module, and synchronizes status information to the firmware and hardware master module. The CPU module can interact with the firmware module, or guide the firmware to adjust the cache management strategy according to the overall system requirements.

[0013] Among them, the on-chip cache SRAM module serves as the temporary storage basis for data. It can wrap around the circular buffer structure and virtual buffer mapping to provide several times the available capacity for the Firmware module. The Firmware module determines pre-allocation and other operations based on system requirements and monitors and modifies the buffer status. By cooperating with the hardware Master module, the pre-allocation instructions are conveyed to the hardware Master module so that it can cache and forward data as required. After completing data processing, the hardware Master module feeds back information to the Firmware module. The Buffer management unit module is responsible for the specific management of the on-chip cache module, executes the instructions of the Firmware module, and monitors and synchronizes the buffer status to the Firmware module in real time. The CPU module can interact with the Firmware module, send instructions to it to adjust the cache management strategy, and obtain cache status information to assist system-level decision-making.

[0014] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: In the present invention, a rewrapable circular buffer is adopted to allow the firmware to obtain an available amount that is several times larger than the physical buffer, thereby achieving efficient buffer management. At the same time, the firmware can change the state of the current buffer according to the actual scenario. The rewrapable buffer management mechanism allows the firmware to handle caches that are several times larger than the physical buffer. The software can pre-allocate multiple rounds of buffers in advance, thereby solving the problem of low efficiency in software buffer allocation. At the same time, the hardware will also synchronize buffer status information to the software, so that the software can control buffer pre-allocation and change buffer status to implement buffer application and release. Through the above mechanism, the software only needs to perform buffer pre-allocation in sequence under the premise of monitoring the buffer status, thereby reducing the difficulty of software design and improving software performance. At the same time, the software has the initiative in buffer allocation, thereby providing great convenience for the firmware design of non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a flow chart of a cache management method of the present invention; Figure 2 It is a schematic diagram of the flow between the modules in the cache management device of the present invention; Figure 3 A schematic diagram of a flow chart showing step 4 in a cache area in the cache management method of the present invention; Figure 4 A schematic diagram of a flow chart showing step 6 in a cache area in the cache management method of the present invention; Figure 5 This is a flow chart illustrating step 7 in the cache area of ​​the cache management method of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] Reference Figure 1-Figure 5 , an efficient cache management method, comprising the following steps: During the system initialization phase, the hardware initializes the rewrapable ring buffer, determines its parameters and the mapping relationship between the physical buffer and the virtual buffer, and sets the buffer to idle. The software initializes the hardware communication interface and the cache-related information storage structure, and sets the ring buffer size to N storage units, which form a ring storage structure. In the S1 cache status synchronization phase, the hardware monitors in real time and synchronizes the buffer status to the firmware according to certain rules; In the S2 software pre-allocation phase, the firmware determines the pre-allocation parameters according to the current cache status and combines the system load, data traffic prediction and task priority, and then pre-allocates the buffer in order and sends instructions to the cache management unit. According to the instruction content, the corresponding physical buffer unit is marked as allocated and is ready to receive or forward data packets. In the S3 data caching and forwarding stage, when data arrives, it is stored in the corresponding entity buffer and stored in a ring structure. The real-time update status is synchronized to the firmware, and the firmware monitors the data. In the S4 state modification phase, after the processing is completed, the firmware evaluates the actual scenario and sends a state modification instruction to the hardware, and the hardware executes it and updates the state synchronously; In the S5 dynamic adjustment phase, the firmware continuously monitors the system status and dynamically adjusts the cache management strategy as needed.

[0018] By setting up a wraparound buffer management mechanism in the system, the firmware can handle caches that are several times larger than the physical buffer. The software can pre-allocate multiple rounds of buffers in advance, solving the problem of low efficiency in software buffer allocation. At the same time, the hardware will synchronize buffer status information to the software to facilitate software control of buffer pre-allocation and change buffer status to implement buffer application and release.

[0019] Reference Figure 1As shown, in the system initialization phase, the cache management unit initializes the rewrapable circular buffer, determines the total capacity of the circular buffer, the partition granularity and other parameters, sets the total capacity of the circular buffer to N bytes, takes 4K bytes as a basic partition unit, and establishes a mapping relationship with the virtual buffer unit for each physical buffer unit according to the preset mapping rule. Each physical 4K-byte buffer unit is mapped to four virtual 1K-byte buffer units, so that the firmware can handle a cache space several times that of the physical buffer. Then, the initial state of all buffer units in the circular buffer is set to idle, marking them as unallocated and unused. At the same time, the relevant registers or storage areas for recording buffer status information are initialized. The firmware performs its own initialization operation, establishes a communication interface with the cache management unit, ensures that it can accurately receive buffer status information from the hardware and send control instructions, and initializes the internal data structure used to store pre-allocation plans, buffer status monitoring data, etc.

[0020] Reference Figure 1 As shown, in the cache status synchronization stage, the cache management unit collects the status information of each buffer unit in the circular buffer at a certain time interval or when a specific event is triggered. The status information includes whether each unit is idle, whether a write or read operation is being performed, which data packet has been allocated, etc., and then sends the collected status information to the firmware through a pre-established communication interface. The firmware receives the buffer status information from the cache management unit through the communication interface, and then updates the received status information to the corresponding data structure used to monitor the cache status internally, and updates the status mark of the corresponding virtual buffer unit in the pre-allocated status array according to the received information.

[0021] Reference Figure 1As shown in the figure, during the software pre-allocation process, the firmware allocates virtual buffer units for the upcoming data packets in sequence starting from the starting position of the virtual buffer space according to the rewinding characteristics of the ring buffer and the mapping relationship between the virtual buffer. The firmware sends the pre-allocation instruction to the hardware cache management unit. The instruction contains the physical buffer unit information corresponding to the pre-allocated virtual buffer unit and the usage of these units. After receiving the pre-allocation instruction from the firmware, the hardware cache management unit marks the corresponding physical buffer unit as allocated according to the instruction content, and then prepares to receive or For the operation of forwarding data packets, if it is pre-allocation for writing data, the hardware will set up the corresponding write channel and storage location, etc. Assuming that each round of pre-allocation requires P virtual buffer units, the firmware first checks whether there are enough continuous free virtual buffer units in the current cache state to meet the needs of one round of pre-allocation. If so, these units are marked as pre-allocated, and the number of pre-allocated rounds, the starting virtual buffer unit position and other information are recorded; if there are not enough continuous free units, the firmware can wait for the hardware to synchronize new idle state information before allocating, or adjust the number of pre-allocated rounds and the number of units in each round according to the preset strategy.

[0022] Reference Figure 1 As shown, in the data caching and forwarding stage, when a data message arrives, the hardware cache management unit stores the data message in the corresponding allocated physical buffer unit according to the previous pre-allocation instruction of the firmware. During the storage process, the rewinding feature of the circular buffer is utilized. When the storage position reaches the end of the circular buffer, it automatically rewinds to the beginning to continue storing. At the same time, the hardware cache management unit updates the buffer status information in real time and synchronizes the updated status information to the firmware. The firmware monitors the progress of the data cache based on the received status update information. If an abnormality is found in the data cache (such as slow storage speed, storage error, etc.), corresponding measures can be taken according to the actual situation, such as adjusting the pre-allocation strategy, modifying the buffer status (such as pausing or reallocating some buffer units), etc.

[0023] Reference Figure 1As shown, during the state modification process, after the data message processing is completed, according to the needs of the actual scenario, the Firmware decides to modify the relevant buffer state, and the Firmware sends a state modification instruction to the hardware cache management unit. After receiving the state modification instruction, the hardware cache management unit updates the state of the corresponding physical buffer unit according to the instruction content, and synchronizes the updated state information back to the Firmware, so that the Firmware can grasp the latest state of the cache in real time.

[0024] Reference Figure 1 As shown in the figure, in the dynamic adjustment stage, according to the system operation status and the change of data flow, the firmware can dynamically adjust the pre-allocation strategy. At the same time, the firmware can also dynamically adjust the buffer allocation order according to the priority of different data packets. For high-priority data packets, free buffer units can be allocated first. Under the premise of ensuring data integrity, the lower-priority buffer units in use can be reallocated. These dynamic adjustment operations need to be implemented through close cooperation with the hardware cache management unit, including sending adjustment instructions and receiving updated status information.

[0025] Specifically, the size of the on-chip cache is (4K*N) Byte. The cache is divided and managed with 4K Byte as the granularity in design. The entire cache area can be divided into multiple groups. Each group has a cfg_start_buf_ptr and cfg_end_buf_ptr. A group has multiple buffers with 4K granularity. Each 4K Byte in a group will use a 4-bit loopidx to represent its number of wraparounds. Therefore, each 4K Byte physical buffer actually maps out a 16*4K Byte virtual buffer for CPU use. At the same time, each 4K Byte buffer will have a buf_flag flag to indicate whether the current buffer is free or occupied. The loopidx and buf_flag real-time information of all 4K buffers is stored in a ram table. Taking a group's buffer as an example, the working steps are as follows: 1. After reset, each 4K buffer is available, and the buffer is currently in loop 0, so loopidx=0 and buf_flag=0 for each buffer; 2. When the firmware pre-allocates the buffer, it starts from loopidx0 and allocates it on demand according to the amount of data. If it is allocated to the cfg_end_buf_ptr of the group, it wraps around to cfg_start_buf_ptr and allocates it again after loopidx+1; 3. After the hardware master receives the allocation instruction issued by the firmware, it will perform the corresponding get operation. If it is a write buffer operation, the hardware needs to perform get0, indicating that the hardware needs to apply for a free buffer for writing. If it is a read buffer operation, the hardware needs to perform get1, indicating that the hardware needs to apply for a completed buffer for reading. For the req_start_buf_ptr+req_len exceeding cfg_end_buf_ptr, the hardware will split it into 2 requests. The req_start_buf_ptr of the second request will wrap around to the cfg_start_buf_ptr of the current group, and req_loopidx will add 1 to the loopidx issued by the firmware. 4. After receiving the get request from each master, the buffer management unit checks the table mentioned above according to the req_start_buf_ptr, req_loopidx and req_len information to determine whether the request is successful. The process is as follows: Figure 3 As shown; 5. After the hardware master receives the information returned by the Buffer management unit, it starts to write / read data to the corresponding buffer, and a set operation is required after completion. If it is a write buffer operation, set1 is required to indicate that the data has been written and can be read; if it is a read buffer operation, set0 is required to indicate that the data has been read and the buffer can be released. For req_start_buf_ptr+req_len exceeding cfg_end_buf_ptr, the hardware will split it into 2 requests. For the second request, its req_start_buf_ptr will wrap around to the current group's cfg_start_buf_ptr, and req_loopidx will add 1 to the loopidx issued by the firmware; 6. Similar to step 4, after receiving the set request from each master, the Buffer management unit checks the table mentioned above for comparison according to the req_start_buf_ptr, req_loopidx and req_len information to determine whether the request is successful. For the request of set1, the Buffer management unit needs to set the buf_flag corresponding to 4K in the table to 1 after set1 is completed; for the request of set0, the Buffer management unit needs to set the buf_flag corresponding to 4K in the table to 1 after set0 is completed, and set the loopidx corresponding to 4K+1, indicating that the 4K buffer can be used for the application of the next loop. The process is as follows: Figure 4 As shown; 7. The buffer management unit will synchronize the latest information in the table to the memory specified by the CPU each time the set is completed, so that the CPU can monitor the status information of the buffer. The CPU can actively initiate a change operation to modify the buffer status based on the scenario requirements and the current buffer information. This operation has the highest priority and will return a successful ack after the operation is completed. The process is as follows: Figure 5 shown.

[0026] This embodiment also provides an efficient cache management device, including an on-chip cache SRAM module, a firmware module, a hardware Master module, a Buffer management unit module and a CPU module. The on-chip cache (SRAM) module provides physical storage as a rewrapable circular buffer, and allows the firmware to obtain more available capacity through specific mapping for data message caching and forwarding. The Firmware module can monitor the cache status, pre-allocate multiple rounds of buffers in advance and modify the buffer status according to the scenario, grasp the allocation initiative, and improve software performance. The Hardware Master module performs data caching and forwarding operations, and interacts with the on-chip cache module to store data. The Buffer management unit module is responsible for specific management such as issuing and recycling the buffer of the on-chip cache module, and synchronizing status information to the Firmware and the Hardware Master module. The CPU module can interact with the Firmware module, or guide the Firmware to adjust the cache management strategy according to the overall system requirements.

[0027] Reference Figure 2As shown, the on-chip cache SRAM module serves as the temporary storage basis for data. It can wrap around the circular buffer structure and virtual buffer mapping to provide several times of available capacity for the Firmware module. The Firmware module determines pre-allocation and other operations based on system requirements and monitors and modifies the buffer status. By cooperating with the hardware Master module, the pre-allocation instruction is conveyed to the hardware Master module so that it can cache and forward data as required. After completing data processing, the hardware Master module feeds back information to the Firmware module. The Buffer management unit module is responsible for the specific management of the on-chip cache module, executes the instructions of the Firmware module, and monitors and synchronizes the buffer status to the Firmware module in real time. The CPU module can interact with the Firmware module, send instructions to it to adjust the cache management strategy, and obtain cache status information to assist system-level decision-making. Through the collaborative work of the above-mentioned operating modules, a cache management method and device that meets efficient management requirements and facilitates Firmware monitoring and modification of buffer status can be implemented, thereby improving the performance of the entire system when processing data packets.

[0028] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An efficient cache management method, characterized in that: The steps include: During the system initialization phase, the hardware initializes the rewrapable ring buffer, determines its parameters and the mapping relationship between the physical buffer and the virtual buffer and sets the buffer to idle. The software initializes the hardware communication interface and the cache-related information storage structure. During the cache status synchronization phase, the hardware monitors in real time and synchronizes the buffer status to the firmware according to certain rules; In the software pre-allocation phase, the firmware determines the pre-allocation parameters according to the current cache state and combines the system load, data traffic prediction and task priority, and then pre-allocates the buffer in order and sends instructions to the cache management unit. According to the instruction content, the corresponding physical buffer unit is marked as allocated and is ready to receive or forward data packets. In the data caching and forwarding stage, when data arrives, it is stored in the corresponding entity buffer and stored in a ring structure. The real-time update status is synchronized to the firmware, and the firmware monitors the data. In the state modification phase, after the processing is completed, the firmware evaluates the actual scenario and sends a state modification instruction to the hardware, and the hardware executes it and updates the state synchronously; During the dynamic adjustment phase, the firmware continuously monitors the system status and dynamically adjusts the cache management strategy as needed.

2. The efficient cache management method according to claim 1, characterized in that: During the system initialization phase, the cache management unit initializes the wraparound circular buffer, determines the total capacity of the circular buffer, the partition granularity and other parameters, establishes a mapping relationship between each physical buffer unit and the virtual buffer unit according to the preset mapping rules, and then sets the initial state of all buffer units in the circular buffer to idle, marking them as unallocated and unused, and initializes the relevant registers or storage areas used to record buffer status information.

3. The efficient cache management method according to claim 1, characterized in that: During the cache status synchronization phase, the cache management unit collects the status information of each buffer unit in the circular buffer at certain time intervals or when a specific event is triggered, and then sends the collected status information to the firmware through a pre-established communication interface. The firmware receives the buffer status information from the cache management unit through the communication interface, and then updates the received status information to the corresponding internal data structure used to monitor the cache status.

4. The efficient cache management method according to claim 1, characterized in that: In the software pre-allocation stage, the Firmware allocates virtual buffer units for the upcoming data packets in sequence, starting from the starting position of the virtual buffer space, according to the wraparound characteristics of the circular buffer and the mapping relationship between the virtual buffer. The Firmware sends the pre-allocation instruction to the hardware cache management unit. The instruction contains the physical buffer unit information corresponding to the pre-allocated virtual buffer unit and how to use these units. After receiving the pre-allocation instruction from the Firmware, the hardware cache management unit marks the corresponding physical buffer unit as allocated according to the instruction content, and then prepares to receive or forward the data packet.

5. The efficient cache management method according to claim 1, characterized in that: During the data caching and forwarding stage, when a data packet arrives, the hardware cache management unit stores the data packet in the corresponding allocated physical buffer unit according to the previous pre-allocation instructions of the firmware. During the storage process, the rewrap feature of the circular buffer is utilized. When the storage position reaches the end of the circular buffer, it automatically wraps around to the beginning to continue storing. At the same time, the hardware cache management unit updates the buffer status information in real time and synchronizes the updated status information to the firmware. The firmware monitors the progress of data caching based on the received status update information.

6. The efficient cache management method according to claim 1, characterized in that: In the state modification stage, after the data message processing is completed, the Firmware decides to modify the relevant buffer state according to the needs of the actual scenario. The Firmware sends a state modification instruction to the hardware cache management unit. After receiving the state modification instruction, the hardware cache management unit updates the state of the corresponding physical buffer unit according to the instruction content and synchronizes the updated state information back to the Firmware.

7. The efficient cache management method according to claim 1, characterized in that: During the dynamic adjustment phase, the firmware can dynamically adjust the pre-allocation strategy according to the system operation status and changes in data traffic. At the same time, the firmware can also dynamically adjust the buffer allocation order according to the priority of different data messages.

8. An efficient cache management device, comprising an on-chip cache SRAM module, a firmware module, a hardware Master module, a Buffer management unit module and a CPU module, characterized in that: The on-chip cache SRAM module provides physical storage as a retractable circular buffer, allowing the firmware to obtain more available capacity through specific mapping for data message caching and forwarding. The Firmware module can monitor the cache status, pre-allocate multiple rounds of buffers in advance and modify the buffer status according to the scenario, take the initiative in allocation, and improve software performance. The hardware Master module performs data caching and forwarding operations, and interacts with the on-chip cache module to store data. The Buffer management unit module is responsible for specific management such as issuing and recycling the buffer of the on-chip cache module, and synchronizing status information to the Firmware and Hardware Master modules. The CPU module can interact with the Firmware module, or guide the Firmware to adjust the cache management strategy according to the overall system requirements.

9. The efficient cache management device according to claim 8, characterized in that: The on-chip cache SRAM module serves as the temporary storage basis for data. It can wrap around the circular buffer structure and virtual buffer mapping to provide several times the available capacity for the Firmware module. The Firmware module determines pre-allocation and other operations based on system requirements and monitors and modifies the buffer status. By cooperating with the hardware Master module, the pre-allocation instructions are conveyed to the Hardware Master module so that it can cache and forward data as required. After completing data processing, the Hardware Master module feeds back information to the Firmware module. The Buffer Management Unit module is responsible for the specific management of the on-chip cache module, executes the instructions of the Firmware module, and monitors and synchronizes the buffer status to the Firmware module in real time. The CPU module can interact with the Firmware module, send instructions to it to adjust the cache management strategy, and obtain cache status information to assist system-level decision-making.

Images