Power distribution network terminal data protection method and device based on memory access control and medium

Abstract

The application discloses a power distribution network terminal data protection method and device based on memory access control and a medium. The method comprises the following steps: S01. Dividing memory for a stage 2 page table, creating a page table, and enabling stage 2; S02. Building a memory protection mechanism, mapping an intermediate physical address to an actual physical address according to the stage 2 page table, and modifying a descriptor in the stage 2 page table to realize memory protection; S03. Dividing a block of memory in a memory space, storing required key data in the memory, setting access permissions of the memory by using the memory protection mechanism, checking the access, and realizing protection of the key data; and S04. Dividing a block of memory in the memory space, setting access permissions of the memory by using the memory protection mechanism, checking the access, and realizing a peripheral protection function. The application has the advantages of simple implementation method, low cost, strong flexibility, strong scalability, safety and reliability and the like.

Description

Technical Field

[0001] This invention relates to the field of distribution network terminal security control technology, and in particular to a method, device and medium for data protection of distribution network terminals based on memory access control. Background Technology

[0002] Distribution network terminals face security risks such as illegal eavesdropping, malicious tampering, and replay attacks. Once subjected to malicious network attacks, important information can be lost, which can seriously affect the normal operation of the power system and even lead to system paralysis. Given the large number of underlying distribution terminal devices, it is necessary to study solutions to improve the data confidentiality of distribution network terminals and the security protection of hardware devices in order to ensure the overall security of numerous distribution terminal devices and even the distribution automation system.

[0003] For data protection at distribution network terminals, existing technologies typically employ reactive, post-incident-response methods. This means that protective actions are taken only after a security incident occurs to prevent further attacks. However, these reactive methods only provide protection after an incident has happened; they cannot effectively protect critical terminal data and hardware before an incident occurs. Therefore, they still cannot prevent security incidents from happening and fail to meet current power security requirements. Summary of the Invention

[0004] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides a method, device and medium for data protection of distribution network terminals based on memory access control that is simple to implement, low in cost, flexible and scalable, and safe and reliable. It can protect the access of key data, key memory and peripheral devices of distribution network terminals based on memory access control, and effectively reduce security risks.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0006] A method for protecting distribution network terminal data based on memory access control, comprising the following steps:

[0007] Step S01. Allocate memory and create page tables for stage 2 page tables, and enable memory address translation stage 2. The memory address translation stage 2 is the stage in which intermediate physical addresses are mapped to actual physical addresses during the memory access control process using address translation. The stage 2 page table is the page table that stores the memory address translation stage 2.

[0008] Step S02. Construct a memory protection mechanism, wherein the memory protection mechanism maps intermediate physical addresses to actual physical addresses according to the stage 2 page table, and modifies the descriptors in the stage 2 page table to set access permissions for the corresponding protected memory, thereby achieving memory protection;

[0009] Step S03. Allocate a first critical memory block in the memory space to store the required critical data, store the required critical data in the first critical memory, use the memory protection mechanism to set the access permissions of the first critical memory, and check the access to the first critical memory to protect the critical data.

[0010] Step S04. Allocate a second critical memory block in the memory space to store peripheral registers, map the peripheral registers to the second critical memory, use the memory protection mechanism to set access permissions for the second critical memory, and check access to the second critical memory to realize the peripheral protection function.

[0011] Further, step S01 includes:

[0012] Step S101. Allocate a block of memory to store the stage 2 page table, and store the memory starting address of the stage 2 page table in a designated register;

[0013] Step S102. Divide the memory of both the normal world and the secure world into corresponding stage 2 page tables, so as to map the intermediate physical address to the actual physical address in the memory address translation stage 2, and modify the corresponding bits of the specified register according to the format of the stage 2 page table;

[0014] Step S103. Set the last bit of the HCR_EL2 register to enable the memory address translation stage 2.

[0015] Furthermore, each page table entry in the stage 2 page table includes a mapping status and access permissions. The descriptive attribute bits in each page table entry are used to describe the mapping attributes of the virtual page, including access permissions, caching strategy, and memory type.

[0016] Further, in step S02, mapping the intermediate physical address to the actual physical address according to the stage 2 page table includes:

[0017] Step S201. Page lookup: Locate the corresponding page table entry based on the first-level index of the virtual address;

[0018] Step S202. Attribute check: Check the attribute bits of the page table entries in the stage 2 page table to verify access permissions;

[0019] Step S203. Address translation: Calculate the corresponding physical address based on the physical page address and offset recorded in the page table entry of the page table in stage 2.

[0020] Furthermore, in step S03, checking the access to the first critical memory includes:

[0021] Step S301. Check whether the read, write, and execute permissions specified by the page table entry descriptor attribute bits match the current operation. If they do not match, trigger a permission exception and block access.

[0022] Step S302. Check if the current access mode matches the mode attribute of the page table. If they do not match, trigger a mode exception and block access.

[0023] Step S303. After the access control check is completed, modify the page table exception handling function to redirect the EL2 permission level instruction to access the required critical data, and return the required critical data to the trusted application along with the page table exception handling function.

[0024] Furthermore, in step S04, the check on access to the second critical memory includes:

[0025] Step S401. Check whether the read, write, and execute permissions specified by the page table entry descriptor attribute bits match the current operation. If they do not match, trigger a permission exception and block access.

[0026] Step S402. Check if the current access mode matches the mode attribute of the page table. If they do not match, trigger a mode exception and block access.

[0027] Furthermore, step S04 also includes a step of accessing the peripheral device through trusted means, including:

[0028] If an untrusted program accesses the second critical memory of the peripheral register, it triggers a processor exception to prevent unauthorized access.

[0029] If a trusted program accesses the second critical memory of the peripheral register, modify the page table exception handling function to allow access to the peripheral register with EL2 privilege level.

[0030] Furthermore, step S04 also includes encrypting and decrypting the data transmitted and written by the peripheral device.

[0031] A computer device includes a processor and a memory, the memory being used to store a computer program, and the processor being used to execute the computer program to perform the method described above.

[0032] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described above.

[0033] Compared with the prior art, the advantages of the present invention are as follows: The present invention combines the hardware conditions of the distribution network terminal with the introduction of trusted execution environment technology, and realizes the protection of key data of the distribution network terminal based on memory access control. It makes full use of the memory access permission control provided by modern operating systems to protect key memory, key data and ensure the security of peripheral access. It does not require modification of hardware or architecture, nor will it have an adverse impact on the normal operation of the operating system. It can not only ensure the security and trustworthiness of the system, but also improve the flexibility and scalability of the system. Attached Figure Description

[0034] Figure 1 This is a schematic diagram illustrating the implementation process of the data protection method for distribution network terminals based on memory access control in this embodiment.

[0035] Figure 2 This is a schematic diagram illustrating the address translation implementation principle after enabling memory address translation stage 2 in this embodiment.

[0036] Figure 3 This is a schematic diagram illustrating the principle of memory protection in this embodiment.

[0037] Figure 4 This is a schematic diagram illustrating the data protection implemented in this embodiment;

[0038] Figure 5 This is a schematic diagram illustrating the peripheral protection implemented in this embodiment. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0040] Address translation is divided into two stages: memory address translation stage 1, which translates virtual addresses into intermediate physical addresses, and memory address translation stage 2, which maps intermediate physical addresses into final physical addresses. If memory address translation stage 2 has higher memory access control privileges than operating system privileges, this means that even if the operating system is attacked or intruded, memory address translation stage 2 can still protect data security. Furthermore, due to its independent access control mechanism, memory address translation stage 2 can provide an additional layer of protection for critical memory, critical data, and peripherals of the power distribution network terminal.

[0041] This invention combines the hardware conditions of the distribution network terminal with the introduction of trusted execution environment technology. Based on memory access control, it protects the critical data of the distribution network terminal. It makes full use of the memory access permission control provided by modern operating systems to protect critical memory, critical data, and ensure the security of peripheral access. It does not require modification of the hardware or architecture and will not adversely affect the normal operation of the operating system. It can not only ensure the security and reliability of the system, but also improve the flexibility and scalability of the system.

[0042] like Figure 1 As shown, the detailed steps of the distribution network terminal data protection method based on memory access control in this embodiment include:

[0043] Step S01. Enable Memory Address Translation Phase 2: Allocate memory for the Phase 2 page table and create the page table, and enable Memory Address Translation Phase 2. Memory Address Translation Phase 2 is the phase in which intermediate physical addresses are mapped to actual physical addresses during the memory access control process using address translation. The Phase 2 page table is the page table that stores the Memory Address Translation Phase 2.

[0044] Before enabling Phase 2 of memory address translation, a memory space needs to be allocated to store the Phase 2 page table. Ensure that the Phase 2 page table is automatically loaded after system startup. Enable Phase 2 of memory address translation only after the page table is created.

[0045] As an optional implementation, enabling memory address translation phase 2 can be achieved through the following steps:

[0046] Step S101. Allocate a memory block in the device tree to store the stage 2 page table, and store the memory starting address of the stage 2 page table in a designated register (e.g., the VTTBR_EL2 register);

[0047] Step S102. Divide the memory of both the normal world and the safe world into corresponding stage 2 page tables so that the memory address translation stage 2 can map the intermediate physical address to the actual physical address and modify the corresponding bits of the specified register (such as the VTCR_EL2 register) according to the format of the stage 2 page table.

[0048] Step S103. Set the last bit of the HCR_EL2 register to enable memory address translation stage 2.

[0049] The last bit in the HCR_EL2 register (i.e., HCR_EL2.VM) controls whether to enable stage 2 memory address translation. When this bit is set, two-stage address translation is allowed in the virtualization environment.

[0050] In a specific application embodiment, memory is first allocated for the stage 2 page table. A block of memory is allocated in the device tree to store the stage 2 page table, and the memory starting address of the stage 2 page table is stored in the VTTBR_EL2 register. Then, the page table is created for stage 2, and the memory of both the normal world and the secure world is allocated into corresponding stage 2 page tables, so that stage 2 can map the intermediate physical address IPA to the actual physical address PA. The corresponding bits of the VTCR_EL2 register are modified according to the format of the stage 2 page table. Finally, the last bit of the HCR_EL2 register is set to enable memory address translation stage 2.

[0051] After enabling memory address translation phase 2, the address translation process in the system is as follows: Figure 2 As shown, the Stage 1 memory management unit translates the virtual address into an intermediate physical address and provides it to the Stage 2 memory management unit. The Stage 2 memory management unit then maps the intermediate physical address to the actual physical address based on the virtual address. The four exception levels EL0 to EL3 are, in order, EL0-User Mode / APP, EL1-Kernel, EL2-Hypervisor, and EL3-Secure Monitor. Each level has different privileges, functions, and access permissions.

[0052] Step S02. Construct a memory protection mechanism. The memory protection mechanism maps intermediate physical addresses to actual physical addresses according to the stage 2 page table and modifies the descriptors in the stage 2 page table to set the access permissions of the corresponding protected memory, thereby realizing memory protection.

[0053] This embodiment maps the intermediate physical address IPA to the actual physical address PA according to the stage 2 page table, and modifies the stage 2 page table to implement read and write permission control of protected memory, ensuring that untrusted programs cannot access protected memory. Memory protection function can be achieved by utilizing the page table descriptor content in the stage 2 page table.

[0054] In this embodiment, the stage 2 page table consists of multiple page table entries. Each page table entry describes the mapping relationship between virtual pages and physical pages, and includes mapping status, access permissions, and other relevant information. The descriptive attribute bits in each page table entry describe the mapping attributes of the virtual page, including access permissions, caching strategies, and memory types. These attribute bits control the read, write, and execute permissions of pages, as well as memory access optimization strategies. Each bit in the page table descriptor content of the stage 2 page table corresponds to different control content. By modifying the stage 2 page table descriptor content, the access permissions of the physical address mapped to the virtual address can be modified, thereby achieving memory protection.

[0055] As an optional implementation, mapping intermediate physical addresses to actual physical addresses according to the stage 2 page table can be achieved through the following steps:

[0056] Step S201. Page lookup: Locate the corresponding page table entry based on the first-level index of the virtual address.

[0057] Specifically, we can first look up the first-level page table using the first-level index to obtain the base address of the second-level page table. Then, we look up the corresponding second-level page table entry using the second-level index, and so on until we reach the last-level page table (for example, the last-level page table can be the third-level page table).

[0058] Step S202. Attribute Check: Check the attribute bits of the page table entries in the stage 2 page table to verify access permissions.

[0059] Specifically, check the attribute bits of the page table entry to verify access permissions and other restrictions, such as checking read and write permissions and whether execution is allowed.

[0060] Step S203. Address translation: Calculate the corresponding physical address based on the physical page address and offset recorded in the page table entry of the page table in stage 2.

[0061] Optionally, additional access permission checks can be performed before accessing the physical address to ensure compliance with access rules and security policies.

[0062] In this memory protection mechanism, stage 2 maps the intermediate physical address IPA to the actual physical address PA through the stage 2 page table. Modifying the stage 2 page table requires read / write permissions for the protected memory, thus preventing applications in EL0 from accessing this protected memory (critical memory). Figure 3 As shown, even if the operating system has been maliciously hijacked by an attacker and become untrustworthy, the mapping relationship of the stage 2 page table will not be tampered with, and untrusted programs still cannot access the protected memory, thereby effectively achieving the security protection of memory data.

[0063] Step S03. Allocate a first critical memory block in the memory space to store the required critical data. Store the required critical data in the first critical memory. Use the memory protection mechanism to set access permissions for the first critical memory and check the access to the first critical memory to protect the critical data.

[0064] This embodiment allocates a block of memory (first critical memory) in the memory space to store critical data. Then, it uses the memory protection mechanism in step S02 to isolate the memory storing critical data and protect the critical memory. Combined with critical memory access control checks, permission and mode attribute checks are performed during address translation. The critical data is accessed through trusted means, and the page table exception handling function is modified to redirect EL2 permission level instructions to access the critical data. This can effectively protect the critical data and greatly improve the protection of critical data in the distribution network terminal.

[0065] Understandably, key data can be various control data, configuration data, etc. that require attention, and can be selected and configured according to actual needs.

[0066] As an optional implementation, during address translation, checking access to the first critical memory to verify access control includes:

[0067] Step S301. Page table entry descriptor check: Check whether the read, write and execute permissions specified by the page table entry descriptor attribute bits are consistent with the current operation. If they are inconsistent, trigger a permission exception and block access.

[0068] Step S302. Access mode check: Check whether the current access mode matches the mode attribute of the page table. If they do not match, trigger a mode exception and block access.

[0069] Step S303. Accessing critical data through trusted means: After the access control check is completed, modify the page table exception handling function to redirect the instruction at the EL2 permission level to access the critical data, and return the critical data to the trusted application along with the page table exception handling function.

[0070] By following the steps above, permission exceptions can be triggered promptly and access blocked when the current operation does not meet the read, write, and execute permissions specified by the page table entry descriptor attribute bits. Similarly, mode exceptions can be triggered promptly and access blocked when the current access mode does not meet the page table's mode attribute. Figure 4 As shown, critical data can also be accessed through trusted means. If an untrusted program tries to access critical data, the processor will promptly trigger a relevant exception to prevent unauthorized access, thus fully utilizing memory access control to achieve critical data protection.

[0071] Step S04. Allocate a second critical memory block in the memory space to store peripheral registers, map the peripheral registers to the second critical memory, and check the access to the second critical memory to realize the peripheral protection function.

[0072] This embodiment allocates a block of memory (second critical memory) in the memory space to store peripheral registers. The peripheral registers are mapped to this critical memory using memory mapping, requiring access to the peripheral registers via a phase 2 mechanism. The memory protection mechanism in step S02 sets access permissions for the critical memory containing the peripheral registers to ensure peripheral security. Access control is verified during peripheral register access, and access to the peripheral is ensured through trusted means. If an untrusted program accesses the critical memory containing the peripheral registers, a relevant processor exception is triggered to prevent unauthorized access. Figure 5 As shown, it can effectively realize the peripheral protection function.

[0073] As an optional implementation, checking access to the second critical memory includes:

[0074] Step S401. Check whether the read, write, and execute permissions specified by the page table entry descriptor attribute bits match the current operation. If they do not match, trigger a permission exception and block access.

[0075] Step S402. Check if the current access mode matches the mode attribute of the page table. If they do not match, trigger a mode exception and block access.

[0076] In this embodiment, the step of accessing the peripheral device through trusted means includes:

[0077] If an untrusted program accesses critical memory in a peripheral register, it triggers a processor exception to prevent the access.

[0078] If a trusted program is accessing critical memory for peripheral registers, then the page table exception handling function can be modified to allow access to peripheral registers at the EL2 privilege level.

[0079] In this embodiment, the data transmitted and written by the peripheral device is also encrypted and decrypted. This encryption and decryption process is completed when accessing the critical memory of the peripheral device register, so as to ensure that the data is not stolen or tampered with during transmission, and further ensure the security of the data.

[0080] This invention, taking into account the hardware conditions of the distribution network terminal, introduces trusted execution environment technology and uses memory access control to protect critical data of the distribution network terminal. The memory address translation stage 2 provides higher memory access control privileges than the operating system, ensuring data security even when the operating system is attacked. This provides an additional layer of protection for the critical memory, critical data, and peripherals of the distribution network terminal, effectively improving system security and reliability without adversely affecting the normal operation of the operating system. It also provides flexibility and scalability while ensuring system security and reliability.

[0081] This embodiment further provides a computer device, including a processor and a memory, the memory being used to store a computer program, and the processor being used to execute the computer program to perform the method as described above.

[0082] It is understood that the method described in this embodiment can be executed by a single device, such as a computer or server, or it can be applied to a distributed scenario where multiple devices cooperate to complete the task. In a distributed scenario, one of the multiple devices may execute only one or more steps of the method described in this embodiment, and the multiple devices interact to complete the method. The processor can be implemented using a general-purpose CPU, microprocessor, application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the method described in this embodiment. The memory can be implemented using read-only memory (ROM), random access memory (RAM), static storage devices, and dynamic storage devices. The memory can store the operating system and other applications. When the method described in this embodiment is implemented through software or firmware, the relevant program code is stored in the memory and called and executed by the processor.

[0083] This embodiment further provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described above.

[0084] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create an implementation for the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0085] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A power distribution network terminal data protection method based on memory access control, characterized by the steps of The application comprises the following steps: S01. Dividing memory for stage 2 page table and creating page table, and enabling memory address translation stage 2, which is a stage for mapping intermediate physical address to actual physical address in the process of realizing memory access control by using address translation; the stage 2 page table is a page table for storing memory address translation stage 2; S02. Building memory protection mechanism, which is a mechanism for mapping intermediate physical address to actual physical address according to the stage 2 page table, and modifying descriptors in the stage 2 page table to set access permissions of corresponding protected memory, thereby realizing memory protection; S03. Dividing a first critical memory in memory space for storing required critical data, storing the required critical data in the first critical memory, setting access permissions of the first critical memory by using the memory protection mechanism, and checking access to the first critical memory, thereby realizing protection of critical data; S04. Dividing a second critical memory in memory space for storing peripheral registers, mapping registers of peripherals to the second critical memory, setting access permissions of the second critical memory by using the memory protection mechanism, and checking access to the second critical memory, thereby realizing peripheral protection function; The step S01 comprises: S101. Dividing a piece of memory for storing the stage 2 page table, and storing the first address of the memory of the stage 2 page table in a designated register; S102. Dividing corresponding stage 2 page tables for memories of normal world and secure world respectively, so as to map intermediate physical address to actual physical address in the memory address translation stage 2, and modifying corresponding bits of the designated register according to the format of the stage 2 page table; S103. Setting the last bit of the HCR_EL2 register to enable the memory address translation stage 2; Each page table entry in the stage 2 page table comprises mapping state and access permission, and the description attribute bit in each page table entry is used for describing mapping attributes of a virtual page, and the description attribute bit comprises access permission, cache strategy and memory type; In the step S04, the step of accessing peripherals by trusted means comprises: If a non-trusted program accesses the second critical memory of peripheral registers, triggering relevant exception blocking of the processor to prevent very access; If a trusted program accesses the second critical memory of peripheral registers, modifying a page table exception processing function to realize access to registers of peripherals by using EL2 permission level.

2. The memory access control based power distribution network terminal data protection method of claim 1, wherein, In the step S02, the step of mapping intermediate physical address to actual physical address according to the stage 2 page table comprises: S201. Page lookup: looking up a corresponding page table entry according to a first index of a virtual address; S202. Attribute checking: checking attribute bits of a page table entry in the stage 2 page table to verify access permission; S203. Address conversion: calculating a corresponding physical address according to a physical page address and an offset recorded in the page table entry in the stage 2 page table.

3. The memory access control based power grid terminal data protection method of claim 1, wherein, In step S03, checking the access to the first critical memory includes: Step S301. Check whether the read, write, and execute permissions specified by the page table entry descriptor attribute bits match the current operation. If they do not match, trigger a permission exception and block access. Step S302. Check if the current access mode matches the mode attribute of the page table. If they do not match, trigger a mode exception and block access. Step S303. After the access control check is completed, modify the page table exception handling function to redirect the EL2 permission level instruction to access the required critical data, and return the required critical data to the trusted application along with the page table exception handling function.

4. The method of claim 1-3, wherein, In step S04, the check on access to the second critical memory includes: Step S401. Check whether the read, write, and execute permissions specified by the page table entry descriptor attribute bits match the current operation. If they do not match, trigger a permission exception and block access. Step S402. Check if the current access mode matches the mode attribute of the page table. If they do not match, trigger a mode exception and block access.

5. The method of claim 1-3, wherein, Step S04 also includes encrypting and decrypting the data transmitted and written by the peripheral device.

6. A computer apparatus comprising a processor and a memory for storing a computer program, characterised in that, The processor is used to execute the computer program to perform the method as described in any one of claims 1 to 5.

7. A computer readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 5.

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