A design method of FPGA adjoint accelerator for fast reverse design

By designing a companion accelerator with a fully pipelined structure on the FPGA platform, the challenges of computing and memory requirements in traditional reverse design are solved, and efficient reverse design computing performance and good scalability are achieved.

CN119623216BActive Publication Date: 2025-04-18JIMEI UNIV
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Patent Information

Application Number
CN202510169604.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-02-17
Publication Date
2025-04-18
Estimated Expiration
2045-02-17

AI Technical Summary

Technical Problem

Traditional accompanying computing has challenges in reverse designs with computing and memory requirements, especially in fine simulation or multi-step systems, resulting in memory bottlenecks and additional computing burdens.

Method used

A FPGA companion method accelerator for fast reverse design was designed. By optimizing the companion method calculation efficiency through the full pipeline structure, the parallel characteristics of FPGA hardware are used to achieve efficient handling of large-scale reverse design problems and good scalability.

Benefits of technology

It significantly reduces the number of accesses to off-chip memory, optimizes resource utilization, improves overall computing performance, and achieves efficient full pipeline acceleration.

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Abstract

The present invention discloses a FPGA adjoint method accelerator design method for rapid reverse design, comprising: simulating the material space to be optimized; setting the optimization target; establishing the optimization model; solving the optimization model, and using the adjoint method to iteratively optimize the material for different material spaces and optimization targets according to the solving process to meet the final ideal requirements; designing the data structure required by the accelerator to encapsulate the field elements to be updated; designing the update architecture, and updating the field elements according to the update architecture; designing the accelerator based on the update architecture; performing forward and reverse simulation and material optimization based on the accelerator; and testing the designed accelerator. The present invention realizes efficient processing of large-scale reverse design problems and good scalability.
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Description

Technical Field

[0001] The invention relates to the technical field of material optimization design and hardware acceleration, and in particular to a FPGA adjoint method accelerator design method for rapid reverse design. Background Art

[0002] Accelerated research on inverse design methods is underway, a powerful computational method for optimizing system configurations to meet target performance requirements, which is widely used in fields such as materials science, nanophotonics, and seismology. Unlike the forward prediction of traditional design methods, inverse design starts with setting target performance and uses advanced algorithms to automatically explore potential solutions in a large design structure. This method is usually formulated as an optimization problem constrained by partial differential equations (PDEs), with the goal of minimizing the difference between the predicted and target performance or maximizing a specific performance indicator.

[0003] In a PDE-constrained environment, traditional intuition-based forward design methods are inefficient and require repeated trial and error to explore the design space. Especially in complex systems such as fluid mechanics, electromagnetism, and structural mechanics, the computation is large and time-consuming. Inverse design uses a goal-oriented approach and the introduction of machine learning (ML) and deep neural networks (DNNs) to effectively use algorithms to classify and optimize large and complex data sets. Another powerful algorithm is the Adjoint Method (AM), which is widely used in PDE-constrained optimization and can efficiently calculate gradients, thereby achieving design optimization through parameter adjustment. AM uses the duality of forward and backward calculations to solve the PDE problem only twice in the optimization iteration, greatly reducing the cost of gradient calculations and making it suitable for large-scale design tasks with thousands of variables.

[0004] Although AM has obvious advantages in efficiency, it also faces challenges in terms of computational and memory requirements, especially the need to store all intermediate states in reverse calculations. This memory bottleneck is particularly prominent in sophisticated simulations or multi-step systems. To address this problem, researchers introduced recalculation technology to selectively recalculate intermediate states during accompanying calculations to reduce memory usage. However, this technology introduces additional computational burden and requires a trade-off between memory savings and computational costs.

[0005] Some previous studies have attempted to optimize the adjoint algorithm on GPU and FPGA platforms to accelerate reverse design, but they still have shortcomings in computational efficiency and scalability. Summary of the invention

[0006] In view of this, the purpose of this invention is to propose an FPGA adjoint method accelerator design method for fast reverse design, and propose the first comprehensive FPGA accelerator design scheme that optimizes the computational efficiency of the adjoint method through a fully pipelined structure. By utilizing the parallel characteristics of FPGA hardware, the design aims to overcome the bottleneck in traditional adjoint computing and achieve efficient processing and good scalability of large-scale reverse design problems.

[0007] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0008] The present invention provides a FPGA adjoint method accelerator design method for rapid reverse design, comprising the following steps:

[0009] Step 1: simulate the material space that needs to be optimized;

[0010] Step 2: setting an optimization target for optimizing the material configuration of the material space;

[0011] Step 3: Establish an optimization model;

[0012] Step 4: Solve the optimization model, and use the adjoint method to iteratively optimize the material for different material spaces and optimization targets according to the solution process to meet the final ideal requirements;

[0013] Step 5: Design the data structure required by the accelerator to encapsulate the field elements that need to be updated;

[0014] Step 6: Design an update architecture and update the field elements according to the update architecture;

[0015] Step 7: Design an accelerator based on the updated architecture;

[0016] Step 8: Perform forward and reverse simulation and material optimization based on the accelerator;

[0017] Step 9: Test the designed accelerator.

[0018] Furthermore, the step 1 specifically includes:

[0019] Step 11, simulating the material space to be optimized by Matlab software, wherein the material space is a two-dimensional planar waveguide with a certain set space;

[0020] Step 12: dividing the material space into a plurality of two-dimensional space grid points with minimum spatial resolution;

[0021] Step 13: In the two-dimensional planar waveguide region, according to design requirements, select a two-dimensional space grid point as the input source point, and select another two-dimensional space grid point as the observation point of the observation signal.

[0022] Furthermore, the step 2 is specifically as follows:

[0023] Set the optimization goal of optimizing the material configuration of the two-dimensional slab waveguide. The optimization goal is to achieve input at the source point by optimizing the material properties. When the signal is signal; among them, is the amplitude value of the signal, indicating the strength and size of the signal. and is the maximum value of the signal, is the frequency of the signal, is the time variable, Indicates delay.

[0024] Furthermore, the step 3 specifically includes:

[0025] Step 31: Use the adjoint method as the time step update function to perform the numerical solution of the partial differential equation. The specific expression is:

[0026] ;

[0027] Where n represents the nth time step, is the matrix of the entire spatial domain state at the nth time step, is the matrix composed of the entire spatial domain state at the n-1th time step, is the external source matrix of the nth time step; is a matrix operator containing training parameters, which acts on the entire spatial domain state of the current time step to update the entire state. Its value is given by Decide; Parameters representing the material, which need to be iteratively updated;

[0028] Step 32: Establish a loss function J according to the optimization objective, and use the Lagrangian function to combine the time step update function and the loss function into an objective function constrained by a partial differential equation:

[0029] ;

[0030] in, is the accompanying variable, represents the kth time step, and 1≤k Represents the transpose of a matrix; is the matrix of the entire spatial domain state at the kth time step, is the matrix of the entire spatial domain state at the k-1th time step, is the external source matrix of the kth time step;

[0031] Step 33: For the optimal solution in the entire space domain, the KKT condition must be satisfied, that is, L for all states The partial derivatives of are all zero, and we can further conclude that:

[0032] ;

[0033] ;

[0034] ;

[0035] ;

[0036] This shows is inferred from the reverse state corresponding to the concept of time reversal, Contains information about the loss, which is also The input source;

[0037] Step 34 and Relative to The gradient of is calculated by the following formula:

[0038] .

[0039] Furthermore, the step 4 specifically includes:

[0040] Step 41: According to Maxwell's equations, we obtain:

[0041] ;

[0042] In the formula, is the magnitude of the two-dimensional electric field, which is a function of time and space; represents the speed of light, which depends on the properties of the propagation medium, and t represents the time variable;

[0043] Step 42: For the two-dimensional case, Simplified to For variables in two-dimensional space The second-order partial derivative of , the above formula is written as:

[0044] ;

[0045] Step 43: For iterative calculation The numerical solution of Discretize and omit variables The subsequent expression is:

[0046] ;

[0047] in, and are the smallest discrete units in the space domain and time domain respectively. Indicates time step, Indicates The spatial step length; Represent the different speeds of light at different locations or spatial grids in a discrete manner;

[0048] Step 44: To solve , rewrite the above formula into recursive form:

[0049] ;

[0050] This formula shows that is defined by the state of the last two time steps, i.e. and ;

[0051] Step 45: and is a constant, and the term Combined into a new training variable ,Will and Bundle and vectorize into two vectors in space, namely and ; After the above two steps, the corresponding matrix is ​​obtained:

[0052] ;

[0053] Among them, the vector The dimension is M×1, is the M-dimensional identity matrix, is a shape of M×M about The matrix of The values ​​are as follows:

[0054] ;

[0055] Step 46: Based on the above formula, derive the recursive formula of the accompanying variable λ:

[0056] ;

[0057] Or written in matrix form:

[0058] ;

[0059] Step 47: Based on the above solution process, for different material spaces and optimization objectives, the adjoint method is used to iteratively optimize the material to meet the final ideal requirements.

[0060] Further, the step 5 comprises:

[0061] Step 51, design a data structure called a cell to encapsulate the field elements that need to be updated;

[0062] Step 52, the structure of the cell is that the field element name, the symbol corresponding to the field element name and the bit width are set in the first row, and the field element name, the symbol corresponding to the field element name and the specific parameters of the bit width are recorded in the corresponding positions starting from the second row; different field element names include original wave state, updated wave state, original accompanying variable, updated accompanying variable, raw material property, updated material property, gradient and navigation mask; wherein, the navigation mask has two functions: the first function is to specify the propagation direction; the second function is to specify the two-dimensional space position where the source is injected.

[0063] Furthermore, the step 6 specifically includes:

[0064] Step 61, the wave propagation engine responsible for updating the field elements adopts a row buffer structure, and the cells are sequentially input from the off-chip memory into the row buffer structure;

[0065] Step 62, after the specific parameters of each row in the cell are transmitted to the row buffer of the row buffer structure, the calculation kernel in the wave propagation engine calculates the output according to the cell stored in the trigger, and sends the processed cells in sequence;

[0066] Step 63, output the processed cells back to the off-chip memory or directly to the next wave propagation engine;

[0067] Step 64: In the forward propagation stage, the wave propagation engine updates the original wave state in each cell. After completing the forward propagation, the wave propagation engine performs backward propagation and updates the original wave state and the original accompanying variables at the same time. In addition, multiple wave propagation engines are fully pipelined and process update operations in parallel.

[0068] Furthermore, the step 7 specifically includes:

[0069] Step 71, designing a fully pipelined FPGA accelerator based on an updated architecture to speed up reverse design;

[0070] Step 72, the architecture of the accelerator is composed of a memory scheduler and N cascaded wave propagation engines, the memory scheduler interacts with the off-chip memory, and bridges the off-chip memory and the wave propagation engine;

[0071] Step 73, the wave propagation engine simultaneously updates the cells at different time steps and optimizes the material properties;

[0072] Step 74, the memory scheduler first performs a memory mapping to stream operation, reads data from the off-chip memory, and sends the cells and sources as a stream to the wave propagation engine. When the cell is updated by the final wave propagation engine, the memory scheduler performs a stream to memory mapping operation and writes the updated cell back to the off-chip memory.

[0073] Furthermore, the step 8 specifically includes:

[0074] Step 81, the wave propagation engine processes the cell flow through the memory scheduler and executes different propagation equations using the navigation mask;

[0075] Step 82, in the wave update kernel, each wave propagation engine includes a forward module and a backward module for different propagation equations, which are used to update the state of the wave; the updated cell flow enters the source injection kernel, and the source injection kernel selects the corresponding calculation path by the navigation mask; if the calculation path is a forward calculation, then in the forward propagation process, the wave propagation engine only performs the forward source injection operation; if the calculation path is a backward calculation, then in the backward propagation process, it is necessary to perform both the backward source injection operation and the forward source injection operation;

[0076] Step 83, the updated cell stream is passed to the property update kernel for updating material properties;

[0077] Step 84, multiple wave propagation engines are cascaded in a fully pipelined manner, and each wave propagation engine is responsible for propagation calculation of a set time step;

[0078] Step 85, each wave propagation engine is equipped with a source allocation kernel, the source allocation kernel sequentially reads source data through the memory scheduler, and marks each source data stream with a counter, the counter ranges from 1 to the total number of wave propagation engines;

[0079] Step 86, pass the source data stream to each level of wave propagation engines in turn and end at the stream terminator; the wave propagation engine reads the source data only when the counter value matches the current level wave propagation engine, and at the same time reduces the corresponding value of the counter and forwards the source data stream to the next wave propagation engine.

[0080] Furthermore, the step 9 specifically includes:

[0081] Step 91, setting the experimental parameters: the accelerator uses s cascaded wave propagation engines, and the number of s is set by the user according to the actual situation; the system clock frequency is set to the set frequency, and multiple actual physical parameters are introduced in the modeling process;

[0082] Step 92, setting the design space of the experiment to be consistent with the two-dimensional slab waveguide;

[0083] Step 93, the experiment adopts a training process to iteratively adjust and optimize the distribution of materials in the two-dimensional planar waveguide;

[0084] Step 94: Test the designed accelerator through a specific embodiment to obtain test results; the test results include the design space before training, the design space after training, and the waveform diagram at the observation point.

[0085] By adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0086] The hardware architecture of the present invention realizes efficient full-pipeline acceleration by cascading multiple wave propagation engines. Through the high bandwidth and line buffer structure of the off-chip memory, the number of accesses to the off-chip memory is significantly reduced, resource utilization is optimized, and overall computing performance is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0088] Figure 1 The present invention provides an execution flow chart of an FPGA companion method accelerator design method for rapid reverse design.

[0089] Figure 2 Schematic diagram of material space in an embodiment of the present invention.

[0090] Figure 3 It is a diagram of the design architecture of the row buffer in an embodiment of the present invention.

[0091] Figure 4 1 is a diagram showing the overall structure of an accelerator in an embodiment of the present invention.

[0092] Figure 5 Detailed architecture diagram of the wave propagation engine of the accelerator in the embodiment of the present invention.

[0093] Figure 6 It is a training effect diagram in an embodiment of the present invention. DETAILED DESCRIPTION

[0094] The present invention will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present invention, but are not intended to limit the scope of the present invention. Similarly, the following examples are only partial embodiments of the present invention rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0095] In terms of theory, the present invention first constructs a mathematical model suitable for complex system optimization based on the adjoint method. The adjoint method transforms the system optimization problem controlled by partial differential equations into the solution of a set of adjoint equations by introducing adjoint variables. Taking Maxwell's equations as an example, the main set of equations describes the changes in the electric and magnetic fields during electromagnetic wave propagation, and expresses its evolution in time and space in the form of partial differential equations. Using the Lagrange multiplier method, the optimization problem is constructed as a Lagrangian function, so that the optimization target can be obtained by solving a set of adjoint equations. In this way, sensitivity information can be obtained during the optimization process of the electromagnetic system, and then used for gradient descent optimization to improve the optimization efficiency and accuracy. The adjoint method has therefore become an efficient means in the optimization design of complex electromagnetic systems, and is particularly suitable for high-complexity design scenarios that require precise control, such as photonic device design.

[0096] See also Figure 1 The AM accelerator based on FPGA of the present invention can provide a fast and effective solution for reverse design. The method specifically comprises the following steps:

[0097] Step 1: simulate the material space that needs to be optimized;

[0098] In this embodiment, the step 1 specifically includes:

[0099] Step 11, simulating the material space to be optimized by Matlab software, wherein the material space is a two-dimensional planar waveguide with a certain set space;

[0100] Step 12: dividing the material space into a plurality of two-dimensional space grid points with minimum spatial resolution;

[0101] Step 13: In the two-dimensional planar waveguide region, according to design requirements, select a two-dimensional space grid point as the input source point, and select another two-dimensional space grid point as the observation point of the observation signal.

[0102] like Figure 2 As shown, in this embodiment, the material space is Further, the space is The minimum spatial resolution is divided into In the two-dimensional planar waveguide area, according to the design requirements, select a point as the "source point" for input, such as the red circle, and select a point as the "observation point" for observing the signal, such as the green circle.

[0103] Step 2: setting an optimization target for optimizing the material configuration of the material space;

[0104] In this embodiment, the step 2 is specifically as follows:

[0105] Set the optimization goal of optimizing the material configuration of the two-dimensional slab waveguide. The optimization goal is to achieve input at the source point by optimizing the material properties. When the signal is signal; among them, is the amplitude value of the signal, indicating the strength and size of the signal. and is the maximum value of the signal, is the frequency of the signal, is the time variable, Indicates delay.

[0106] By optimizing the material properties, the two-dimensional planar waveguide can achieve efficient light propagation under specific waveform conditions.

[0107] Step 3: Establish an optimization model;

[0108] In this embodiment, step 3 specifically includes:

[0109] Step 31: Use the adjoint method as the time step update function to perform the numerical solution of the partial differential equation. The specific expression is:

[0110] ;

[0111] Where n represents the nth time step, is the matrix of the entire spatial domain state at the nth time step, is the matrix composed of the entire spatial domain state at the n-1th time step, is the external source matrix of the nth time step; is a matrix operator containing training parameters, which acts on the entire spatial domain state of the current time step to update the entire state. Its value is given by Decide; Parameters representing the material, which need to be iteratively updated;

[0112] Step 32: Establish a loss function J according to the optimization objective to quantify the system loss; and use the Lagrangian function to combine the time step update function and the loss function into an objective function constrained by a partial differential equation:

[0113] ;

[0114] in, is the accompanying variable, represents the kth time step, and 1≤k Represents the transpose of a matrix; is the matrix of the entire spatial domain state at the kth time step, is the matrix of the entire spatial domain state at the k-1th time step, is the external source matrix of the kth time step;

[0115] Step 33: For the optimal solution in the entire space domain, the KKT (Karush-Kuhn-Tucker) condition must be satisfied, that is, L for all states The partial derivatives of are all zero, and we can further conclude that:

[0116] ;

[0117] ;

[0118] ;

[0119] ;

[0120] This shows is inferred from the reverse state corresponding to the concept of time reversal, Contains information about the loss, which is also The input source;

[0121] Step 34 and Relative to The gradient of is calculated by the following formula:

[0122] .

[0123] Step 4: Solve the optimization model, and use the adjoint method to iteratively optimize the material for different material spaces and optimization targets according to the solution process to meet the final ideal requirements;

[0124] In this embodiment, step 4 specifically includes:

[0125] Step 41, using the two-dimensional electric field as a demonstration, and excluding the external input source due to its independent characteristics. First, according to Maxwell's equations, we get:

[0126] ;

[0127] In the formula, is the magnitude of the two-dimensional electric field, which is a function of time and space; represents the speed of light, which depends on the properties of the propagation medium, and t represents the time variable;

[0128] Step 42: For the two-dimensional case, Simplified to For variables in two-dimensional space The second-order partial derivative of , the above formula is written as:

[0129] ;

[0130] Step 43: For iterative calculation The numerical solution of Discretize and omit variables The subsequent expression is:

[0131] ;

[0132] in, and are the smallest discrete units in the space domain and time domain respectively. Indicates time step, Indicates spatial step; due to the inhomogeneity of the material, Represent the different speeds of light at different locations or spatial grids in a discrete manner;

[0133] Step 44: To solve , rewrite the above formula into recursive form:

[0134] ;

[0135] This formula shows that is defined by the state of the last two time steps, i.e. and ;

[0136] Step 45: and is a constant, and the term Combined into a new training variable ,Will and Bundle and vectorize into two vectors in space, namely and ; After the above two steps, the corresponding matrix is ​​obtained:

[0137] ;

[0138] Among them, the vector The dimension is M×1, is the M-dimensional identity matrix, is a shape of M×M about The matrix of The values ​​are as follows:

[0139] ;

[0140] Step 46: Based on the above formula, derive the recursive formula of the accompanying variable λ:

[0141] ;

[0142] Or written in matrix form:

[0143] ;

[0144] Step 47. Based on the above solution process, the adjoint method is used to iteratively optimize the material for different material spaces and optimization targets to meet the ultimate ideal requirements. The algorithm achieves precise adjustment of the material distribution by effectively evaluating the sensitivity of the objective function to the design variables. Through this iterative optimization process, it can be ensured that the optical transmission efficiency and signal quality are maximized while meeting specific performance indicators, and ultimately the expected optical performance of the design is achieved. This method not only improves the efficiency of optimization, but also ensures the reliability of the design results, providing solid theoretical support and practical basis for further hardware acceleration.

[0145] Step 1 to step 4 are software simulation processes. In the software simulation stage, the present invention uses the finite difference time domain (FDTD) method to simulate the propagation characteristics of electromagnetic waves, and verifies the effectiveness of the adjoint method and the hardware accelerator architecture through numerical simulation. The simulation process first sets the geometric structure, material properties and boundary conditions to describe the basic scenario of the optimization problem. Then, the spatial distribution of the electromagnetic field is calculated through forward simulation, and this result is input into the adjoint equation for backward propagation to obtain the gradient of the objective function relative to the design parameters. After each round of iterative updating of the design parameters, the optimization algorithm is used to continuously approach the optimal solution to achieve the optimization goal. Through numerical simulation, the correctness of the theoretical model can be verified, and a reliable performance benchmark can be provided for the implementation of the hardware accelerator.

[0146] Step 5: Design the data structure required by the accelerator to encapsulate the field elements that need to be updated;

[0147] In this embodiment, step 5 comprises:

[0148] Step 51, design a data structure called a cell to encapsulate the field elements that need to be updated;

[0149] Step 52, the structure of the cell is that the field element name, the symbol corresponding to the field element name and the bit width are set in the first row, and the field element name, the symbol corresponding to the field element name and the specific parameters of the bit width are recorded in the corresponding positions starting from the second row; different field element names include original wave state, updated wave state, original accompanying variable, updated accompanying variable, raw material property, updated material property, gradient and navigation mask; wherein, the navigation mask has two functions: the first function is to specify the propagation direction; the second function is to specify the two-dimensional space position where the source is injected.

[0150] Consider updating a single field element (in the forward pass , in the backward pass and ) requires information from the element itself and four adjacent elements: above, below, left and right, so the present invention designs a data structure called a cell to encapsulate the information required for the update. The following table describes the construction of a cell in detail:

[0151]

[0152] Step 6: Design an update architecture and update the field elements according to the update architecture;

[0153] In this embodiment, step 6 specifically includes:

[0154] Step 61, the wave propagation engine responsible for updating the field elements adopts a row buffer structure, such as Figure 3 As shown; the cells are sequentially input from the off-chip memory into the row buffer structure;

[0155] Step 62, after the specific parameters of each row in the cell are transmitted to the row buffer of the row buffer structure, the calculation kernel in the wave propagation engine calculates the output according to the cell stored in the trigger, and sends the processed cells in sequence;

[0156] Step 63, output returns the processed cells to off-chip memory or directly to the next wave propagation engine; therefore, the wave propagation engine can start processing before the cells of the entire wave field are loaded into the row buffer. This approach allows the wave propagation engine to store only the necessary cells, thereby reducing the resource consumption of the row buffer. In addition, there is a significant difference between the image processing kernel and the wave propagation engine: the image processing kernel only depends on the input image, but the wave propagation engine needs to merge the source into the spatial domain for updating, so the wave propagation engine is better.

[0157] Step 64: In the forward propagation stage, the wave propagation engine updates the original wave state in each cell. After completing the forward propagation, the wave propagation engine performs backward propagation, updates the original wave state and the original adjoint variable at the same time, and multiple wave propagation engines are fully pipelined to process update operations in parallel. The multi-stage pipeline structure of the wave propagation engine supports high parallelism, and each stage handles propagation tasks of different time steps. For example, the first-stage wave propagation engine is responsible for updating the 1st step, the (N+1)th step, and the (2N+1)th step, and the second-stage wave propagation engine is responsible for the 2nd step, the (N+2)th step, and so on. By cascading multiple wave propagation engines, propagation of different time steps can be processed simultaneously, achieving efficient full-pipeline acceleration. Through the high bandwidth and row buffer structure of HBM, the number of accesses to the off-chip memory is significantly reduced, resource utilization is optimized, and overall computing performance is improved.

[0158] In the forward propagation process, the wave propagation engine completes the forward simulation of the propagation variables, while in the backward propagation process, the wave propagation engine performs reverse simulation and updates the propagation variables and the accompanying variables at the same time. In order to support the bidirectional calculation process, the present invention introduces a navigation mask, which is used to determine the propagation direction and to indicate the injection position of the source. Through the cascade structure of the multi-layer wave propagation engine, a fully pipelined process can be achieved, which greatly shortens the processing time of data update.

[0159] Step 7, design an accelerator based on the update architecture; in terms of hardware implementation, the present invention achieves the acceleration of reverse design by designing an efficient accelerator architecture suitable for adjoint method optimization. The core of the accelerator architecture is the Wave Propagation Engine, which uses the row buffer structure in image processing to improve computing efficiency. In this design, the row buffer of each wave propagation engine is composed of a number of flip-flops (FFs) and a First-In-First-Out (FIFO) buffer as local storage. FFs can quickly access the current cell, and FIFO temporarily stores the received cells, thereby achieving efficient data stream processing.

[0160] In this embodiment, step 7 specifically includes:

[0161] Step 71, designing a fully pipelined FPGA accelerator based on an updated architecture to speed up reverse design;

[0162] Step 72 Figure 4 An architecture diagram of the accelerator is provided. The architecture of the accelerator consists of a memory scheduler and N cascaded wave propagation engines. The memory scheduler interacts with the off-chip memory and bridges the off-chip memory and the wave propagation engine. The memory scheduler uses the Advanced eXtensible Interface (AXI) to interact with the off-chip memory (especially the high-bandwidth off-chip memory (HBM) used for FPGA accelerators).

[0163] Step 73, the wave propagation engine simultaneously updates the cells at different time steps and optimizes the material properties;

[0164] Step 74, the memory scheduler first performs a memory-mapped to stream (MM2S) operation to read data from the off-chip memory (HBM) through the AXI4 bus, and sends the cells and sources as a stream to the wave propagation engine through the AXI-Stream bus. When the cell is updated by the final wave propagation engine, the memory scheduler performs a stream-to-memory mapping (S2MM) operation to write the updated cell back to the off-chip memory through the AXI4 bus.

[0165] In the entire architecture, the memory scheduler is responsible for data interaction with the off-chip memory (High-Bandwidth Memory, HBM). The memory scheduler implements data stream reading (MM2S) from the off-chip memory through the Advanced eXtensibleInterface (AXI) protocol, and transmits the cells and source data to the wave propagation engine in the form of data streams. After the data update is completed, the storage scheduler performs a data stream to memory mapping (S2MM) operation to write the processed cells back to the HBM. In this way, the storage scheduler realizes the data bridge between the off-chip memory and the wave propagation engine, ensuring efficient data transmission of the entire system. The high bandwidth performance of the HBM off-chip memory significantly improves the data throughput of the wave propagation engine. Taking the AMD Alveo U280 FPGA as an example, its configured HBM provides a total bandwidth of 460 GB / s and is divided into 32 pseudo channels, with a bandwidth of 14.375 GB / s for each channel. In the current design, the bandwidth requirement of the cell structure is 16 bytes (128 bits). Assuming the clock frequency is 300 MHz, the total bandwidth requirement for a single read and write is 9.6 GB / s, which is well within the bandwidth range of HBM and effectively supports high-speed data access requirements.

[0166] Step 8: Perform forward and reverse simulation and material optimization based on the accelerator;

[0167] In this embodiment, step 8 specifically includes:

[0168] Step 81 Figure 5 The detailed architecture of the wave propagation engine is presented, which processes the cell flow through a memory scheduler and executes different propagation equations using navigation masks;

[0169] Step 82, in the wave update kernel, each wave propagation engine includes a forward module and a backward module for different propagation equations, which are used to update the state of the wave; the updated cell flow enters the source injection kernel, and the source injection kernel selects the corresponding calculation path by the navigation mask; if the calculation path is forward calculation, then in the forward propagation process, the wave propagation engine only performs the forward source injection operation; if the calculation path is backward calculation, then in the backward propagation process, it is necessary to perform the backward source injection operation and the forward source injection operation at the same time; the backward source injection is used to calculate the backward wave field, and the forward source injection is used to update the propagation variables and the accompanying variables. These two injection operations can be performed in parallel in the backward (reverse) process, thereby maximizing the use of resources and significantly saving computing time.

[0170] Step 83, the updated cell stream is passed to the property update kernel for updating material properties;

[0171] Step 84. Multiple wave propagation engines are cascaded in a fully pipelined manner, and each wave propagation engine is responsible for the propagation calculation of a set time step; thereby achieving high parallelism, each wave propagation engine is responsible for the propagation calculation of a specific time step, for example, the first engine processes the propagation of step 1, step (N+1), and step (2N+1), the second engine processes step 2, step (N+2), and step (2N+2), and so on.

[0172] Step 85, in order to manage the source data flow, each wave propagation engine is equipped with a source allocation kernel, which can effectively manage the source data flow; the source allocation kernel sequentially reads the source data through the memory scheduler and marks each source data flow with a counter, and the counter ranges from 1 to the total number of wave propagation engines;

[0173] Step 86: Pass the source data stream to each level of wave propagation engines in sequence and end at the stream terminator; the wave propagation engine reads the source data only when the counter value matches the wave propagation engine of the current level, and forwards the source data stream to the next wave propagation engine after reducing the corresponding value of the counter. For example: the wave propagation engine processes the source data when the counter value is 1, and passes the source data stream to the next wave propagation engine after reducing the counter by 1. This mechanism ensures that the source data stream can correctly pass through each wave propagation engine in sequence, ensuring the efficient transmission of the source data stream. When the source data stream reaches the corresponding wave propagation engine, the source injection kernel can read and inject the corresponding source data, and receive the corresponding cell data for further operation when the navigation mask arrives, thereby ensuring the synchronous update of the source data in the forward (forward) and reverse (backward) propagation process. The entire design realizes efficient parallel processing, optimizes resource utilization, and significantly improves computing performance.

[0174] Step 9: Test the designed accelerator.

[0175] In this embodiment, step 9 specifically includes:

[0176] Step 91, setting the experimental parameters: the accelerator uses s cascaded wave propagation engines, and the number of s is set by the user according to the actual situation; the system clock frequency is set to the set frequency, and multiple actual physical parameters are introduced in the modeling process;

[0177] In this embodiment, the accelerator uses 30 cascaded wave propagation engines, and the system clock frequency is set to 250MHz. In addition, in order to ensure that the experiment can accurately simulate the real physical scene, the actual physical parameters are introduced in the modeling process. This method ensures the reliability and relevance of the performance evaluation under real conditions, thereby improving the validity and credibility of the results. The parameters used in the experiment are listed in the following table:

[0178]

[0179] Step 92, setting the design space of the experiment to be consistent with the two-dimensional slab waveguide;

[0180] Step 93, the experiment adopts a training process to iteratively adjust and optimize the distribution of materials in the two-dimensional planar waveguide;

[0181] A 2D slab waveguide is an optical waveguide designed to confine and guide light through a high refractive index material surrounded by a low refractive index region. The purpose of the experiment is to optimize the configuration of materials in the waveguide to improve its light guiding performance. The main goal of the experiment is to optimize the waveguide structure to meet a specific objective function. In this case, the goal is to achieve efficient light transmission within the waveguide while maintaining the desired waveform at the output. The initial waveguide has the basic ability to guide light, but its default configuration is not sufficient to meet the strict requirements of the target output. Therefore, the experiment uses a training process to iteratively adjust and optimize the distribution of materials within the waveguide to enhance its functionality. Throughout the training process, the system gradually optimizes the internal configuration of the waveguide based on performance feedback, thereby improving its efficiency in transmitting light and achieving the target waveform.

[0182] Step 94: Test the designed accelerator through a specific embodiment to obtain test results; the test results include the design space before training, the design space after training, and the waveform diagram at the observation point. Figure 6 As shown in Figure 2, Figure (a) is the design space before training, Figure (b) is the design space after training, and Figure (c) is the waveform diagram at the observation point.

[0183] The above descriptions are only some embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent device or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for designing an FPGA adjoint accelerator for rapid reverse design, characterized in that: The steps include: Step 1: simulate the material space that needs to be optimized; Step 2: setting an optimization target for optimizing the material configuration of the material space; Step 3: Establish an optimization model; Step 4: Solve the optimization model, and use the adjoint method to iteratively optimize the material for different material spaces and optimization targets according to the solution process to meet the final ideal requirements; Step 5: Design the data structure required by the accelerator to encapsulate the field elements that need to be updated; specifically, including: Step 51, design a data structure called a cell to encapsulate the field elements that need to be updated; Step 52, the structure of the cell is that the field element name, the symbol corresponding to the field element name and the bit width are set in the first row, and the field element name, the symbol corresponding to the field element name and the specific parameters of the bit width are recorded in the corresponding position starting from the second row; different field element names include original wave state, updated wave state, original accompanying variable, updated accompanying variable, raw material property, updated material property, gradient and navigation mask; wherein, the navigation mask has two functions: the first function is to specify the propagation direction; the second function is to specify the two-dimensional space position where the source is injected; Step 6: Design an update architecture and update field elements according to the update architecture; specifically: Step 61, the wave propagation engine responsible for updating the field elements adopts a row buffer structure, and the cells are sequentially input from the off-chip memory into the row buffer structure; Step 62, after the specific parameters of each row in the cell are transmitted to the row buffer of the row buffer structure, the calculation kernel in the wave propagation engine calculates the output according to the cell stored in the trigger, and sends the processed cells in sequence; Step 63, output the processed cells back to the off-chip memory or directly to the next wave propagation engine; Step 64, in the forward propagation stage, the wave propagation engine updates the original wave state in each cell. After completing the forward propagation, the wave propagation engine performs backward propagation, updating the original wave state and the original adjoint variable at the same time, and multiple wave propagation engines are fully pipelined to process the update operation in parallel; Step 7: Design an accelerator based on the updated architecture; specifically including: Step 71, designing a fully pipelined FPGA accelerator based on an updated architecture to speed up reverse design; Step 72, the architecture of the accelerator is composed of a memory scheduler and N cascaded wave propagation engines, the memory scheduler interacts with the off-chip memory, and bridges the off-chip memory and the wave propagation engine; Step 73, the wave propagation engine simultaneously updates the cells at different time steps and optimizes the material properties; Step 74, the memory scheduler first performs a memory mapping to stream operation, reads data from the off-chip memory, and sends the cell and source as a stream to the wave propagation engine. When the cell is updated by the final wave propagation engine, the memory scheduler performs a stream to memory mapping operation to write the updated cell back to the off-chip memory; Step 8: Perform forward and reverse simulation and material optimization based on the accelerator; Step 9: Test the designed accelerator.

2. The FPGA companion method accelerator design method for rapid reverse design according to claim 1, characterized in that: The step 1 specifically includes: Step 11, simulating the material space to be optimized by Matlab software, wherein the material space is a two-dimensional planar waveguide with a certain set space; Step 12: dividing the material space into a plurality of two-dimensional space grid points with minimum spatial resolution; Step 13: In the two-dimensional planar waveguide region, according to design requirements, select a two-dimensional space grid point as the input source point, and select another two-dimensional space grid point as the observation point of the observation signal.

3. The FPGA companion method accelerator design method for rapid reverse design according to claim 2, characterized in that: The step 2 is specifically as follows: Set the optimization goal of optimizing the material configuration of the two-dimensional slab waveguide. The optimization goal is to achieve input at the source point by optimizing the material properties. When the signal is signal; among them, is the amplitude value of the signal, indicating the strength and size of the signal. and is the maximum value of the signal, is the frequency of the signal, is the time variable, Indicates delay.

4. The FPGA companion method accelerator design method for rapid reverse design according to claim 1, characterized in that: The step 3 specifically includes: Step 31: Use the adjoint method as the time step update function to perform the numerical solution of the partial differential equation. The specific expression is: Where n represents the nth time step, is the matrix of the entire spatial domain state at the nth time step, is the matrix composed of the entire spatial domain state at the n-1th time step, is the external source matrix of the nth time step; is a matrix operator containing training parameters, which acts on the entire spatial domain state of the current time step to update the entire state. Its value is given by Decide; Parameters representing the material, which need to be iteratively updated; Step 32: Establish a loss function J according to the optimization objective, and use the Lagrangian function to combine the time step update function and the loss function into an objective function constrained by a partial differential equation: in, is the accompanying variable, represents the kth time step, and 1≤k Represents the transpose of a matrix; is the matrix of the entire spatial domain state at the kth time step, is the matrix of the entire spatial domain state at the k-1th time step, is the external source matrix of the kth time step; Step 33: For the optimal solution in the entire space domain, the KKT condition must be satisfied, that is, L for all states The partial derivatives of are all zero, and we can further conclude that: This shows is inferred from the reverse state corresponding to the concept of time reversal, Contains information about the loss, which is also The input source; Step 34 and Relative to The gradient of is calculated by the following formula: 。 5. The FPGA companion method accelerator design method for rapid reverse design according to claim 4, characterized in that: The step 4 specifically includes: Step 41: According to Maxwell's equations, we get: In the formula, is the magnitude of the two-dimensional electric field, which is a function of time and space; represents the speed of light, which depends on the properties of the propagation medium, and t represents the time variable; Step 42: For the two-dimensional case, Simplified to For variables in two-dimensional space The second-order partial derivative of , the above formula is written as: Step 43: For iterative calculation The numerical solution of Discretize and omit variables The subsequent expression is: in, and are the smallest discrete units in the space domain and time domain respectively. Indicates time step, Indicates The spatial step length; Represent the different speeds of light at different locations or spatial grids in a discrete manner; Step 44: To solve , rewrite the above formula into recursive form: This formula shows that is defined by the state of the last two time steps, i.e. and ; Step 45: and is a constant, and the term Combined into a new training variable ,Will and Bundle and vectorize into two vectors in space, namely and ; After the above two steps, the corresponding matrix is ​​obtained: Among them, the vector The dimension is M×1, is the M-dimensional identity matrix, is a shape of M×M about The matrix of The values ​​are as follows: Step 46: Based on the above formula, derive the recursive formula of the accompanying variable λ: Or written in matrix form: Step 47: Based on the above solution process, for different material spaces and optimization objectives, the adjoint method is used to iteratively optimize the material to meet the final ideal requirements.

6. The FPGA companion method accelerator design method for rapid reverse design according to claim 1, characterized in that: The step 8 specifically includes: Step 81, the wave propagation engine processes the cell flow through the memory scheduler and executes different propagation equations using the navigation mask; Step 82, in the wave update kernel, each wave propagation engine includes a forward module and a backward module for different propagation equations, which are used to update the state of the wave; the updated cell flow enters the source injection kernel, and the source injection kernel selects the corresponding calculation path by the navigation mask; if the calculation path is a forward calculation, then in the forward propagation process, the wave propagation engine only performs the forward source injection operation; if the calculation path is a backward calculation, then in the backward propagation process, it is necessary to perform both the backward source injection operation and the forward source injection operation; Step 83, the updated cell stream is passed to the property update kernel for updating material properties; Step 84, multiple wave propagation engines are cascaded in a fully pipelined manner, and each wave propagation engine is responsible for propagation calculation of a set time step; Step 85, each wave propagation engine is equipped with a source allocation kernel, the source allocation kernel sequentially reads source data through the memory scheduler, and marks each source data stream with a counter, the counter ranges from 1 to the total number of wave propagation engines; Step 86, pass the source data stream to each level of wave propagation engines in turn and end at the stream terminator; the wave propagation engine reads the source data only when the counter value matches the current level wave propagation engine, and at the same time reduces the corresponding value of the counter and forwards the source data stream to the next wave propagation engine.

7. The FPGA companion method accelerator design method for rapid reverse design according to claim 1, characterized in that: The step 9 specifically includes: Step 91, setting the experimental parameters: the accelerator uses s cascaded wave propagation engines, and the number of s is set by the user according to the actual situation; the system clock frequency is set to the set frequency, and multiple actual physical parameters are introduced in the modeling process; Step 92, setting the design space of the experiment to be consistent with the two-dimensional slab waveguide; Step 93, the experiment adopts a training process to iteratively adjust and optimize the distribution of materials in the two-dimensional planar waveguide; Step 94: Test the designed accelerator through a specific embodiment to obtain test results; the test results include the design space before training, the design space after training, and the waveform diagram at the observation point.

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