A dual-phase lightweight asynchronous circuit based on time borrowing and a control method thereof

Abstract

The application discloses a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof. The circuit comprises a control path and a data path. The control path comprises a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller. The data path comprises a storage unit and a combination logic unit. The method comprises: performing asynchronous processing on a register circuit to obtain an asynchronous register circuit; performing division processing on the asynchronous register circuit based on timing constraints to obtain a divided register circuit; introducing the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller to perform margin-aware asynchronous control processing on the divided register circuit to generate a timing pulse control signal. The embodiment of the application can match the control signal with different pulse widths with the requirement of a latch, thereby improving the execution efficiency of instructions and optimizing the power consumption and area of the asynchronous circuit. The application can be widely applied to the technical field of integrated circuit design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof. BACKGROUND

[0002] With the continuous expansion of the scale of integrated circuits, the power consumption of complex global clock networks limits the development of synchronous circuits. Asynchronous circuits use handshake logic to replace global clock and have been proven to have the advantage of low power consumption. Among different types of asynchronous circuits, 2-phase data bundling has a more extensive application due to its lower area overhead. Compared with registers, latches have also been proven to have the advantage of low power consumption. In addition, latches have the characteristics of timing borrowing, so they have the potential to improve the operating frequency of the circuit. Latches have more stringent requirements for their control signals. If the pulse width is too high, the latch will face a greater risk of hold time violation. If the pulse width is too low, the latch will have difficulty in fully utilizing the advantages of timing borrowing. However, the asynchronous circuit design methods in the related art are mostly for registers, and the control signals generated by the controllers at each level cannot be properly controlled, that is, it is difficult to control the pulse width of each latch, which makes it difficult to ensure the normal operation of the latch and makes it more difficult to fully utilize the low power consumption advantage and timing borrowing characteristics of the latch. Moreover, the asynchronous control method cannot completely eliminate the adverse effects of phase skew caused by asynchronous handshake logic. Phase skew will exacerbate the impact of the critical path on the performance of the circuit.

[0003] In summary, the technical problems in the related art need to be improved. SUMMARY

[0004] The main purpose of the embodiments of the present application is to provide a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof, which can match the needs of latches through two control signals with different pulse widths, thereby optimizing the power consumption and area of the asynchronous circuit.

[0005] To achieve the above purpose, one aspect of the embodiments of the present application provides a dual-phase lightweight asynchronous circuit based on timing borrowing, which comprises a control path and a data path, the output end of the control path is connected with the input end of the data path, wherein:

[0006] The control path comprises a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller, the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller are connected through an asynchronous control chain, and the control path is used to generate a first asynchronous control signal and a second asynchronous control signal.

[0007] The data path includes storage units and combinational logic units, the storage units are connected through the combinational logic units, the storage units include normal latches, key latches and memories, the data path is used for calculation and storage, and timing borrowing occurs under the control of the first asynchronous control signal and the second asynchronous control signal.

[0008] In some embodiments, the dual-phase lightweight asynchronous controller includes a multiplexer, an exclusive NOR gate, a first exclusive OR gate, a second exclusive OR gate, a first pulse control module and a second pulse control module, a first input end of the multiplexer obtains an input request signal, a second input end of the multiplexer is connected with an output end of the exclusive NOR gate, a first output end of the multiplexer, a first input end of the exclusive NOR gate, a first end of the first pulse control module, a second input end of the first exclusive OR gate, a second output end of the multiplexer, a second end of the second pulse control module and a first input end of the second exclusive OR gate are connected, a second end of the first pulse control module is connected with a first input end of the first exclusive OR gate, a first end of the second pulse control module is connected with a second input end of the second exclusive OR gate, the first output end of the multiplexer outputs an output request signal, the second output end of the multiplexer outputs an output response signal, and a second input end of the exclusive NOR gate obtains an input response signal, wherein:

[0009] The multiplexer is used for initializing a handshake signal and transmitting the output request signal.

[0010] The exclusive NOR gate is used for judging the phase of the output request signal and the phase of the input response signal.

[0011] The first exclusive OR gate is used for generating the first asynchronous control signal.

[0012] The second exclusive OR gate is used for generating the second asynchronous control signal.

[0013] The first pulse control module is used for adjusting the clock pulse width of the first asynchronous control signal.

[0014] The second pulse control module is used for adjusting the clock pulse width of the second asynchronous control signal.

[0015] In some embodiments, the control path further includes a delay unit, and the delay unit is used for controlling the phase difference between the first asynchronous control signal and the second asynchronous control signal.

[0016] In some embodiments, the clock pulse width of the first asynchronous control signal is greater than the clock pulse width of the second asynchronous control signal.

[0017] In some embodiments, the timing margin of the normal latch is greater than the timing margin of the critical latch.

[0018] In some embodiments, the first asynchronous control signal is used to control the operation of the critical latch, and the second asynchronous control signal is used to control the operation of the normal latch and the memory.

[0019] To achieve the above object, another aspect of the embodiment of the present application proposes a control method of a dual-phase lightweight asynchronous circuit based on timing borrowing, which comprises the following steps:

[0020] Asynchronous processing is performed on the register circuit to obtain an asynchronous register circuit;

[0021] The asynchronous register circuit is distinguished based on timing constraints to obtain a distinguished register circuit, which comprises a normal latch, a critical latch, and a memory.

[0022] A dual-phase lightweight asynchronous controller and a lightweight asynchronous controller are introduced to perform margin-aware asynchronous control processing on the distinguished register circuit to generate a timing pulse control signal.

[0023] In some embodiments, the distinguishing of the asynchronous register circuit based on timing constraints to obtain a distinguished register circuit comprises:

[0024] A time threshold is set;

[0025] A timing length of a timing path corresponding to a data path is obtained by a timing constraint analysis tool;

[0026] If the timing length of the timing path corresponding to the data path is less than the time threshold, the storage unit is distinguished as a normal latch and a memory;

[0027] If the timing length of the timing path corresponding to the data path is greater than the time threshold, the storage unit is distinguished as a critical latch;

[0028] The normal latch, the memory, and the critical latch are integrated to obtain the distinguished register circuit.

[0029] In some embodiments, the introduction of the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller to perform margin-aware asynchronous control processing on the distinguished register circuit to generate a timing pulse control signal comprises:

[0030] The dual-phase lightweight asynchronous controller and the lightweight asynchronous controller are introduced;

[0031] The first asynchronous control signal and the second asynchronous control signal are generated by the dual-phase lightweight asynchronous controller, and the lightweight asynchronous controller generates the second asynchronous control signal;

[0032] The operation of the key latch is controlled by the first asynchronous control signal, and the operation of the general latch and the memory is controlled by the second asynchronous control signal, and the timing pulse control signal is generated.

[0033] In some embodiments, the dual-phase lightweight asynchronous controller controls the phase difference between the first asynchronous control signal and the second asynchronous control signal by introducing a delay unit.

[0034] The embodiments of the present application at least have the following beneficial effects: the present application provides a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof, which generates a first asynchronous control signal and a second asynchronous control signal by introducing a dual-phase lightweight asynchronous controller, further divides storage units into general latches, key latches and memories according to timing margins, controls the key latches by the first asynchronous control signal, and controls the general latches and the memories by the second asynchronous control signal, without introducing a complex clock network, optimizes the power consumption and area of the asynchronous circuit, matches the requirements of the latches by two control signals with different pulse widths, avoids the phase skew generated by the asynchronous handshake logic, improves the execution efficiency of instructions, and fully plays the low-power advantage and timing borrowing characteristics of the latches. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram of a dual-phase lightweight asynchronous circuit based on timing borrowing provided by the embodiments of the present application;

[0036] Figure 2 is a step flowchart of a control method of a dual-phase lightweight asynchronous circuit based on timing borrowing provided by the embodiments of the present application;

[0037] Figure 3 is a pulse width requirement diagram of a latch provided by the embodiments of the present application;

[0038] Figure 4 is a structural schematic diagram of a dual-phase lightweight asynchronous controller provided by the embodiments of the present application;

[0039] Figure 5 is a pulse control logic diagram of a pulse control unit provided by the embodiments of the present application;

[0040] Figure 6 is a logic diagram of an asynchronous control method based on timing borrowing provided by the embodiments of the present application;

[0041] Figure 7 is a register-based synchronous circuit structure schematic diagram provided by an embodiment of the present application;

[0042] Figure 8 is a register-based asynchronous circuit structure schematic diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description relates to the drawings, the same numerals in different drawings represent the same or similar elements unless otherwise indicated. The implementation described in the following exemplary embodiments does not represent all the implementations consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0044] It can be understood that the terms "first", "second", and the like used in the present application can be used herein to describe various concepts, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determining".

[0045] The terms "at least one", "multiple", "each", "any" and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0047] In the related art, the latch has more stringent requirements for its control signal. If the pulse width is too high, the latch faces a greater risk of hold time violation. If the pulse width is too low, the latch has difficulty in fully utilizing the advantages of timing borrowing, such as Figure 3The requirements of the control signals for the latches at different positions in the circuit are different, and therefore, for the design of the latches, the asynchronous circuit capable of providing flexible control signals is more suitable than the synchronous circuit using a global clock network. However, most of the existing asynchronous circuit design methods are register-oriented, and the control signals generated by the controllers at different levels cannot be properly controlled, and it is difficult to ensure the normal operation of the latches, and it is even more difficult to fully exert the low-power consumption advantage and the timing borrowing characteristics of the latches.

[0048] In the related art, the conversion from the synchronous circuit to the 2-phase data-bundling asynchronous circuit is realized by using an automated script, but some of them are not applicable to the design of the latches, and for those applicable to the design of the latches, the design process does not have flexibility and cannot fully exert the timing borrowing characteristics of the latches. The existing asynchronous controllers such as the click controller and the lightweight asynchronous controller cannot control the pulse width of each latch in a targeted manner, and therefore, the timing borrowing and low-power consumption characteristics of the latches cannot be fully exerted, and the asynchronous control method cannot completely eliminate the adverse effects of the phase skew generated by the asynchronous handshake logic and the performance of the asynchronous circuit is still limited by the critical path.

[0049] Therefore, in the embodiments of the present application, a two-phase lightweight asynchronous circuit based on timing borrowing is provided, which reduces the limitation of the critical path on the performance of the circuit by utilizing the timing borrowing characteristics of the latches, and further makes the performance of the circuit approach the average performance, and further, the asynchronous control method proposed eliminates the adverse effects of the phase skew, so that each latch in the circuit works at a suitable pulse width, and the timing borrowing and low-power consumption characteristics can be fully exerted.

[0050] Reference Figure 1 , Figure 1 The structure diagram of the two-phase lightweight asynchronous circuit based on timing borrowing provided in the embodiments of the present application is shown in FIG. 1. Figure 1 The circuit includes a control path and a data path, and the output end of the control path is connected with the input end of the data path, wherein:

[0051] The control path includes a two-phase lightweight asynchronous controller and a lightweight asynchronous controller, and the two-phase lightweight asynchronous controller and the lightweight asynchronous controller are connected through an asynchronous control chain, and the control path is used to generate a first asynchronous control signal and a second asynchronous control signal.

[0052] Further, it needs to be explained that the dual-phase lightweight asynchronous controller comprises a multiplexer M1, an XNOR gate U1, a first XOR gate U2, a second XOR gate U3, a first pulse control module PCM1 and a second pulse control module PCM2, the first input end of the multiplexer acquires the input request signal, the second input end of the multiplexer is connected with the output end of the XNOR gate, the first output end of the multiplexer, the first input end of the XNOR gate, the first end of the first pulse control module, the second input end of the first XOR gate, the second output end of the multiplexer, the second end of the second pulse control module and the first input end of the second XOR gate are connected, the second end of the first pulse control module is connected with the first input end of the first XOR gate, the first end of the second pulse control module is connected with the second input end of the second XOR gate, the first output end of the multiplexer outputs the output request signal, the second output end of the multiplexer outputs the output response signal, and the second input end of the XNOR gate acquires the input response signal, wherein the multiplexer is used for initializing the handshake signal and transmitting the output request signal; the XNOR gate is used for judging the phase of the output request signal and the phase of the input response signal; the first XOR gate is used for generating the first asynchronous control signal; the second XOR gate is used for generating the second asynchronous control signal; the first pulse control module is used for adjusting the clock pulse width of the first asynchronous control signal; and the second pulse control module is used for adjusting the clock pulse width of the second asynchronous control signal.

[0053] In the embodiment, in order to fully exert the low power consumption and the time borrowing characteristics of the latch, the latch is divided into two categories in the embodiment, one category is the latch on the longer time sequence path, which is called the key latch in the embodiment; the other category is the latch on the shorter time sequence path, which has more time sequence margin, and is called the ordinary latch in the embodiment. In order to distinguish the two kinds of latches from the design, the embodiment sets a time threshold in the time sequence constraint through the "set_max_delay" instruction, and the tool automatically analyzes the time sequence path exceeding the threshold, and then screens the key latch on the longer path.

[0054] Further, the time sequence paths of the key latch and the ordinary latch are explained, the key latch is on the longer time sequence path, and thus has less risk of causing the hold time violation, and needs to strive for more time sequence margin as possible. Therefore, the key latch is suitable for wider pulse width, that is, the time sequence borrowing characteristics can be used to a great extent to reduce the time sequence pressure. The ordinary latch is on the shorter time sequence path, has more time sequence margin, and has greater risk of causing the hold time violation. Therefore, the ordinary latch is more suitable for narrower pulse width, that is, the time sequence borrowing is not needed to reduce the setup time pressure, and the narrower pulse width can minimize the risk of the hold time violation.

[0055] In order to realize flexible control of the dual-phase latch, an embodiment of the present application designs a dual-phase lightweight asynchronous controller (DPLAC), as shown in Figure 4 . The asynchronous handshake logic is composed of an XOR gate and a 3-1 multiplexer. Compared with other conventional asynchronous controllers, the DPLAC has a simpler structure, and can minimize the power consumption and area overhead of the asynchronous control chain while ensuring the correctness of the handshake logic.

[0056] Further, the dual-phase lightweight asynchronous controller is described as shown in Figure 4 . The two different phase control signals generated by the dual-phase asynchronous controller are a first asynchronous pulse and a second asynchronous pulse, and the two control signals will control the critical latch and the ordinary latch respectively. The effect that can be finally achieved is that the control signal pulse width of the critical latch is larger, that is, there is more timing margin for other timing paths to borrow, while the control signal pulse width of the ordinary latch is smaller, that is, the cost paid for the hold time violation is small.

[0057] In addition, the meanings of other signals in Figure 4 are explained as follows:

[0058] The reset signal is used for the initialization of the system when the circuit starts, that is, resetting all signals to 0;

[0059] The input request signal and the output response signal are used for handshake with the previous asynchronous controller, receiving the request of the previous circuit, and returning the response signal to the previous circuit;

[0060] The output request signal and the input response signal are used for handshake with the next asynchronous controller, sending the request signal to the next circuit, and receiving the response signal sent by the next circuit.

[0061] The components in Figure 4 are explained as follows:

[0062] The multiplexer M1 is used for initializing the handshake signal, transmitting the output request signal or keeping the handshake signal state unchanged;

[0063] The XOR gate U1 is used for judging whether the phase of the output request signal is consistent with the phase of the response signal;

[0064] The XOR gate U2 is used for generating the first asynchronous pulse;

[0065] The XOR gate U2 is used for generating the second asynchronous pulse;

[0066] The first pulse control module PCM1 and the second pulse control module PCM2 are used for adjusting the clock pulse width.

[0067] Finally, the adjustment principle of the first pulse control module PCM1 and the second pulse control module PCM2 is described. In addition to the handshake logic, each dual-phase lightweight asynchronous controller has a pulse control unit (PCM) and an XOR gate to flexibly control the two different pulse widths required by the dual-phase latch. The implementation method of the pulse control unit is as shown in Figure 5 As shown in the figure, in the synthesis and implementation stage of digital integrated circuit design, through the three steps of constraint, check and correction, the pulse width of the control signal is flexibly and accurately controlled.

[0068] 1) Pulse width constraint: after the latch-based asynchronous circuit is imported into the synthesis tool (such as Design Compiler) in the form of a gate-level netlist, “Set_min_pulse_width” is used to set the minimum pulse width of the control signal of one or a batch of latches;

[0069] 2) Pulse width detection: next, in the clock tree synthesis stage (a step in layout and routing, which needs to be completed in the layout and routing tool, such as IC Compiler), “Report_min_pulse_width” is used to check the pulse width of the latch constrained in the pulse width constraint. If the actual pulse width does not meet the constraint in the pulse width constraint, the tool will report a violation, and how much the constraint is different;

[0070] 3) Pulse width correction: if the pulse width does not meet the requirement of the pulse width constraint in the pulse width detection, if the pulse width is too small, “Insert_buffer” will be used to insert a delay unit to expand the pulse width; if the pulse width is too large, “remove_buffer” will be used to shorten the pulse width. Finally, whether the timing borrowing occurs as expected and whether there are still timing violations in the circuit are checked through the timing report given by the analysis tool. If it is successful, waveform checking is performed to complete the design.

[0071] Further, it should be noted that the control path also includes a delay unit, which is used to control the phase difference between the first asynchronous control signal and the second asynchronous control signal.

[0072] Among them, the clock pulse width of the first asynchronous control signal is greater than the clock pulse width of the second asynchronous control signal.

[0073] The data path includes storage units and combinational logic units, and the storage units are connected through the combinational logic units. The storage units include ordinary latches, key latches and memories. The data path is used for calculation and storage, and timing borrowing occurs under the control of the first asynchronous control signal and the second asynchronous control signal.

[0074] In particular, the timing margin of the normal latch is greater than that of the critical latch, and more particularly, the first asynchronous control signal is used to control the operation of the critical latch, and the second asynchronous control signal is used to control the operation of the normal latch and the memory.

[0075] In summary, in the timing analysis of the synthesis tool, the "report_timing" instruction and the like are used to perceive the timing margin of each timing path. Assuming that the Nth stage of the circuit has a longer timing path, a dual-phase lightweight asynchronous controller needs to be applied to control the latch of the Nth stage. In addition, the memory is generally regarded as a register in the timing analysis, and the control signal of the memory generally needs a wider pulse width to ensure its normal operation. Therefore, for the stage including storage in the circuit, a dual-phase lightweight asynchronous controller also needs to be applied to generate two different pulse control signals. For the stages with relatively loose timing in the pipeline, in order to reduce the hardware overhead of the asynchronous control chain as much as possible, only the normal LAC controller needs to be selected.

[0076] Further to the embodiment of the present application Figure 1 is described and illustrated, Figure 4 As shown, it is a part of an asynchronous pipeline, which includes three stages in total, assuming that it is the N-1th stage, the Nth stage and the N+1th stage. The asynchronous circuit mainly includes two parts, one part is a control path, and the other part is a data path.

[0077] The control path is mainly composed of an asynchronous control chain of DPLAC and LAC, that is, a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller. First, the input request signal and the output response signal are used to handshake with the previous stage circuit; the output request signal and the input response signal are used to handshake with the next stage circuit. The delay unit in the control path is used to control the phase difference between different asynchronous control signals. The DPLAC or LAC will provide asynchronous control signals for controlling one or a batch of storage units.

[0078] The data path is mainly composed of storage units and combinational logic. In the embodiment of the present application, the latch is the main storage unit in the data path, in addition, there is also a memory in the circuit, and the memory is also a storage unit in the data path. Moreover, the latch will be divided into critical latches and normal latches.

[0079] In addition, the longer timing path in the circuit often passes through some specific circuit modules. Therefore, in order to reduce the adverse effects of the phase skew caused by the asynchronous handshake, the asynchronous start signal (Async_Start) is set in the stage where the complex circuit modules are concentrated, such as Figure 1 As shown, in this start mode, the adverse effects of the phase skew on the circuit will be alleviated.

[0080] Referring to Figure 2 The embodiment of the present application also provides a control method of the dual-phase lightweight asynchronous circuit based on timing borrowing, which can realize the above-mentioned dual-phase lightweight asynchronous circuit based on timing borrowing. The method comprises the following steps:

[0081] S100, performing asynchronous processing based on a register circuit to obtain an asynchronous register circuit;

[0082] S200, performing division processing on the asynchronous register circuit based on timing constraints to obtain a divided register circuit, wherein the divided register circuit comprises a normal latch, a critical latch and a memory;

[0083] It should be noted that in some embodiments, the step S200 can comprise: S210, setting a time threshold; S220, obtaining the timing length of the timing path corresponding to the data path by using a timing constraint analysis tool; S230, if the timing length of the timing path corresponding to the data path is less than the time threshold, then the storage unit is divided into a normal latch and a memory; S240, if the timing length of the timing path corresponding to the data path is greater than the time threshold, then the storage unit is divided into a critical latch; S250, integrating the normal latch, the memory and the critical latch to obtain the divided register circuit.

[0084] S300, introducing a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller to perform margin-aware asynchronous control processing on the divided register circuit to generate a timing pulse control signal;

[0085] It should be noted that in some embodiments, the step S300 can comprise: S310, introducing a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller; S320, generating a first asynchronous control signal and a second asynchronous control signal by using the dual-phase lightweight asynchronous controller, and generating a second asynchronous control signal by using the lightweight asynchronous controller; S330, controlling the operation of the critical latch by using the first asynchronous control signal, and controlling the operation of the normal latch and the memory by using the second asynchronous control signal to generate a timing pulse control signal.

[0086] In some specific embodiments, the dual-phase lightweight asynchronous controller controls the phase difference between the first asynchronous control signal and the second asynchronous control signal by introducing a delay unit.

[0087] In summary, the control method of the dual-phase lightweight asynchronous circuit of the embodiment of the present application can be automatically realized by a commercial EDA tool. Furthermore, referring to Figure 6 Firstly, for a mainstream register-based circuit design (the control path is composed of a global clock, and the data path is composed of a combination logic and a register), such asFigure 7 As shown, the need for first asynchronous, asynchronous circuit as shown Figure 8 As shown (data path still consists of combinational logic and registers, while the control path becomes a two-phase single-track Click control chain).

[0088] Subsequently, under the appropriate timing constraints, the synthesis tool (e.g. Design Compiler) generates a gate-level netlist. Subsequently, the tool will generate a timing report based on the timing constraints to distinguish between the longer and shorter paths in the circuit, which is also the basis for subsequent distinction between critical latches and ordinary latches.

[0089] Further application of the DPLAC mentioned in the method and the margin-aware asynchronous control method; TCL scripts will automatically implement the conversion from registers to latches, and the control end of the DPLAC will accurately control every latch in the circuit. The timing constraints of the appropriate latches will be used to complete the second synthesis, and instructions such as "set_multicycle_path" will ensure the correct timing check of the latches. Finally, after pulse width control and layout, the tool will output the final circuit netlist.

[0090] Therefore, compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0091] 1) Lower power consumption and area overhead: Compared with registers, latches have lower power consumption and area overhead. However, latches have a higher risk of hold time violation, and repairing hold time violations requires hardware overhead. In the asynchronous control method involved in the present application, due to the classification of latches and the dual-phase control of the present application, the risk of hold time violation is minimized. Therefore, compared with register design, the embodiments of the present application can bring lower power consumption and area overhead. In addition, compared with the complex clock network of traditional synchronous circuits or the Click control chain of traditional asynchronous circuits, the asynchronous circuit involved in the embodiments of the present application uses a lighter asynchronous control, further optimizing the power consumption and area of the circuit.

[0092] 2) Higher speed, i.e. higher operating frequency of the circuit: The highest operating frequency of existing register-based synchronous circuits or asynchronous circuits will be limited by the critical path. Using the timing borrowing method involved in the embodiments of the present application, the timing requirements of the critical path will be reduced, which means that the main frequency of the circuit will be significantly improved.

[0093] In summary, the asynchronous processor constructed by the embodiments of the present application has a speed improvement of 1.58x while reducing power consumption by 28.71% compared with the synchronous processor.

[0094] It can be understood that the contents in the method embodiments described above are applicable to the circuit embodiments, the circuit embodiments specifically implement the functions of the method embodiments, and achieve the beneficial effects same as those of the method embodiments.

[0095] The preferred embodiments of the application are described above with reference to the accompanying drawings, and are not intended to limit the scope of the application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the application should be within the scope of the application.

Claims

1. A two-phase lightweight asynchronous circuit based on timing borrowing, characterized in that, The circuit includes a control path and a data path, wherein the output terminal of the control path is connected to the input terminal of the data path, and: The control path includes a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller, which are connected through an asynchronous control chain. The control path is used to generate a first asynchronous control signal and a second asynchronous control signal. The data path includes storage units and combinational logic units, and the storage units are connected to each other through the combinational logic units. Each storage unit includes a general-purpose latch, a critical latch, and a memory. The data path is used for calculation and storage, and timing borrowing occurs under the control of the first asynchronous control signal and the second asynchronous control signal. The timing margin of the general-purpose latch is greater than the timing margin of the critical latch. The dual-phase lightweight asynchronous controller includes a multiplexer, an XOR gate, a first XOR gate, a second XOR gate, a first pulse control module, and a second pulse control module. The first input of the multiplexer acquires an input request signal. The second input of the multiplexer is connected to the output of the XOR gate. The first output of the multiplexer, the first input of the XOR gate, the first terminal of the first pulse control module, the second input of the first XOR gate, the second output of the multiplexer, and the second terminal of the second pulse control module are all connected to the first input of the second XOR gate. The second terminal of the first pulse control module is connected to the first input of the first XOR gate. The first terminal of the second pulse control module is connected to the second input of the second XOR gate. The first output of the multiplexer outputs a request signal, and the second output of the multiplexer outputs an acknowledgement signal. The second input of the XOR gate acquires an input acknowledgement signal. The multiplexer is used to initialize the handshake signal and transmit the output request signal; The XNOR gate is used to determine the phase of the output request signal and the phase of the input response signal; The first XOR gate is used to generate the first asynchronous control signal; The second XOR gate is used to generate the second asynchronous control signal; The first pulse control module is used to adjust the clock pulse width of the first asynchronous control signal; The second pulse control module is used to adjust the clock pulse width of the second asynchronous control signal.

2. The circuit according to claim 1, characterized in that, The control path further includes a delay unit, which is used to control the phase difference between the first asynchronous control signal and the second asynchronous control signal.

3. The circuit according to claim 1, characterized in that, The clock pulse width of the first asynchronous control signal is greater than the clock pulse width of the second asynchronous control signal.

4. The circuit according to claim 1, characterized in that, The first asynchronous control signal is used to control the operation of the critical latch, and the second asynchronous control signal is used to control the operation of the general latch and the memory.

5. A control method for a two-phase lightweight asynchronous circuit based on timing borrowing as described in any one of claims 1-4, characterized in that, The method includes the following steps: Asynchronous processing is performed on the register circuit to obtain the asynchronous register circuit; The asynchronous register circuit is differentiated based on timing constraints to obtain a differentiated register circuit, which includes a general latch, a critical latch, and a memory. A dual-phase lightweight asynchronous controller and a lightweight asynchronous controller are introduced to perform margin-sensing asynchronous control processing on the differentiated register circuit to generate timing pulse control signals.

6. The method according to claim 5, characterized in that, The process of differentiating the asynchronous register circuit based on timing constraints to obtain the differentiated register circuit includes: Set a time threshold; The timing lengths of the corresponding timing paths for several data paths are obtained using timing constraint analysis tools. If the timing length of the timing path corresponding to the data path is less than the time threshold, then the storage unit is divided into a general latch and a memory. If the timing length of the timing path corresponding to the data path is greater than the time threshold, then the storage unit is classified as a critical latch; By integrating the general latch, the memory, and the key latch, the differentiated register circuit is obtained.

7. The method according to claim 5, characterized in that, The introduction of a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller to perform margin-aware asynchronous control processing on the differentiated register circuit, generating timing pulse control signals, includes: The dual-phase lightweight asynchronous controller and the lightweight asynchronous controller are introduced; The dual-phase lightweight asynchronous controller generates a first asynchronous control signal and a second asynchronous control signal, wherein the lightweight asynchronous controller generates the second asynchronous control signal; The operation of the key latch is controlled by the first asynchronous control signal, and the operation of the ordinary latch and the memory is controlled by the second asynchronous control signal, thereby generating the timing pulse control signal.

8. The method according to claim 5, characterized in that, The dual-phase lightweight asynchronous controller controls the phase difference between the first asynchronous control signal and the second asynchronous control signal by introducing a delay unit.

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