A network layout design method based on Samsung 4nm

Abstract

The present invention discloses a network layout design method based on Samsung 4nm, and relates to the field of semiconductor layout design technology. It includes selecting two layers of topmetal to construct a power ground network; overlapping the power layer and the ground layer, the power layer is connected to the power supply to form a low-impedance power network, and the ground layer is connected to the ground to form a low-impedance ground network; forming a uniformly distributed power ground stabilizing capacitor between the power layer and the ground layer, and the ground layer is connected to the ground network; the present invention forms a uniformly distributed low-impedance power ground network and stabilizing capacitor through the designed two layers of topmetal overlapping setting, provides a low-impedance groundshielding network, and effectively reduces noise interference; constructs a power ground network with lower impedance, provides a higher quality power ground, and better suppresses electromagnetic interference through a large number of uniformly distributed shielding networks, protecting the circuit from external electromagnetic interference.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor layout design, and in particular to a network layout design method based on Samsung 4nm. Background Art

[0002] In the field of high-speed and high-performance chip design, the design quality of the power and ground (PG) layout plays a vital role in the overall performance of the chip. Poor power and ground layout may cause a series of problems, which will not only affect the working stability of the chip, but also reduce its performance and even cause functional failure. Specifically, noise on the power line, such as voltage fluctuations, glitches, and ripples, may cause signal integrity problems, which in turn may lead to data errors or communication failures. These problems usually originate from impedance mismatch of the power network, distributed inductance effects, or insufficient coupling between the power line and the ground line. In addition, ground bounce occurs when multiple high-current devices switch states at the same time, causing the ground line voltage to increase instantaneously. This is usually because the impedance of the ground line is not sufficient to cope with transient large currents, especially when multiple pins are switched at the same time. Poor power ground layout will also increase electromagnetic interference (EMI), affecting the performance of the chip itself and may also interfere with the normal operation of other electronic devices. This is because long power or ground traces may radiate electromagnetic energy like antennas, and without sufficient shielding or decoupling measures, these radiations cannot be effectively suppressed. Finally, poor power ground layout may cause local hot spots, affecting the thermal performance of the chip, and even causing thermal damage. This is usually because the power ground layer does not effectively dissipate heat, or the power line path design is unreasonable, resulting in abnormally high current density in certain areas. Summary of the invention

[0003] The purpose of the present invention is to provide a network layout design method based on Samsung 4nm, which solves the noise, ground bounce, electromagnetic interference (EMI) and thermal management problems on the power line, not only improves the signal integrity and stability of the circuit, but also optimizes the wiring efficiency and chip space utilization.

[0004] This application provides a network layout design method based on Samsung 4nm, including the following steps:

[0005] Select two layers of topmetal to build a power ground network, wherein the two layers of topmetal include a power layer and a ground layer;

[0006] The power layer and the ground layer are overlapped, the power layer is connected to the power source to form a low-impedance power network, and the ground layer is grounded to form a low-impedance ground network;

[0007] Forming evenly distributed power-to-ground voltage-stabilizing capacitors between the power layer and the ground layer, the ground layer being connected to the ground network;

[0008] Connect any cell of the power layer directly downward to the device through a through-hole to form a ground network, and then connect the ground layer downward to the device through a customized through-hole cell to form a power network.

[0009] Furthermore, after the ground layer is connected to the ground network, it includes: adopting noise isolation technology, setting an isolation area between the IP circuit and the internal logic block, and arranging metal filling in the isolation area to absorb and attenuate noise signals.

[0010] Furthermore, the noise isolation technology is used to set an isolation area between the IP circuit and the internal logic block, and metal filling is arranged in the isolation area, specifically including:

[0011] Obtain the connection request between the ground layer and the ground network, determine whether noise isolation processing is required, and if so, perform the following steps; otherwise, directly establish a network connection;

[0012] According to the preset noise isolation rules, determine the location and size of the isolation area between the IP circuit and the internal logic block, and store the parameter information of the isolation area in the isolation area configuration database;

[0013] Obtain characteristic parameters of various types of metal filling materials from the metal filling material database, and select metal filling materials by comparing the noise absorption and signal attenuation capabilities of the materials;

[0014] Matching the parameter information of the selected metal filling material with the isolation zone parameters in the isolation zone configuration database to generate a detailed design plan for the isolation zone; constructing the isolation zone at a designated location between the IP circuit and the internal logic block according to the detailed design plan for the isolation zone, and filling the isolation zone with the selected metal material to form a complete noise isolation structure;

[0015] After the connection between the stratum and the ground network is established, the intensity of the noise signal is monitored in real time, and the monitoring data is transmitted to the noise analysis module for analysis to determine the isolation effect of the noise isolation structure; when the noise isolation effect does not reach the preset noise reduction threshold, the isolation area optimization mechanism is triggered.

[0016] Furthermore, after setting an isolation area between the IP circuit and the internal logic block, it also includes: adopting a layered power network and a layered ground network design, building multiple power layers and ground layers on different metal layers, and setting a shielding layer between the power layer and the ground layer.

[0017] Furthermore, a hierarchical power supply network and a hierarchical ground network design are adopted, specifically including:

[0018] According to the layout of IP circuits and internal logic blocks, determine the location and size of the isolation area, mark the range of the isolation area in the layout diagram, determine the number and arrangement of metal layers for the layered power network and layered ground network, analyze the network equivalent resistance and impedance characteristics under different arrangements through simulation tools, and select the metal layer arrangement scheme;

[0019] Divide the power layer and ground layer areas in the layout, determine the area and position of each area according to the power consumption and noise characteristics of the circuit, analyze the voltage drop and current density distribution of the power layer and ground layer through circuit simulation tools, and optimize the wiring topology and line width;

[0020] Insert a shielding layer between the power layer and the ground layer, analyze the isolation effect of the shielding layer through electromagnetic field simulation, and optimize the geometric parameters and wiring method of the shielding layer;

[0021] At the interface between the IP circuit and the internal logic block, a dedicated isolation power layer and isolation ground layer are set up, and the layout of the isolation power layer and isolation ground layer is optimized according to the location and number of the interfaces.

[0022] Furthermore, the power layer and the ground layer are overlapped, and further comprising: arranging a metal shielding grid between the power layer and the ground layer to form a uniformly distributed shielding structure, and determining the size and spacing parameters of the metal shielding grid by a multi-objective optimization method;

[0023] The method for determining the size and spacing parameters of a metal shielding grid includes: obtaining layout information of a power layer and a ground layer, and determining the vertical spacing between the two layers; establishing a three-dimensional model of a metal shielding grid according to the vertical spacing between the power layer and the ground layer, and initializing the grid size and grid spacing parameters; using an electromagnetic field simulation method to analyze the shielding effect under different grid sizes and grid spacings, and obtaining a relationship curve between the shielding effect and the grid parameters; obtaining the relationship between the wiring resource occupancy rate and the grid size and the grid spacing, and establishing a mathematical model of the wiring resource occupancy rate; performing multi-objective optimization on the shielding effect relationship curve and the wiring resource occupancy rate model, and solving the optimal grid size and grid spacing parameters; updating the three-dimensional model of the metal shielding grid according to the optimal grid parameters to form a uniformly distributed shielding structure; and embedding the optimized metal shielding grid model between the power layer and the ground layer to complete the overlapping setting of the two layers.

[0024] Furthermore, a network layout design method based on Samsung 4nm also includes: using an intelligent through-hole connection method to adaptively adjust the layout and number of through-holes according to the location and connection requirements of the device.

[0025] Furthermore, the adaptively adjusting the layout and quantity of the through holes specifically includes:

[0026] According to the location information of the devices in the network layout, the connection requirements between the devices are determined, the location coordinates of each device connection are obtained, and the through-hole layout is preliminarily determined according to the preset rules;

[0027] Using intelligent optimization algorithms, under the premise of satisfying device connection, the optimal through-hole layout scheme is found through iterative calculation, and the specific position coordinates of each through-hole are optimized according to the through-hole layout scheme to obtain a refined through-hole layout;

[0028] According to the detailed through-hole layout and combined with the process requirements, the size parameters of each through-hole are determined. Based on the through-hole layout and size parameters, the introduced parasitic parameters are calculated to determine whether the design indicators are met;

[0029] Among them, if the parasitic parameters exceed the design indicators, the intelligent optimization algorithm is re-executed until the requirements are met, and finally the optimized through-hole layout design is output.

[0030] Furthermore, after adaptively adjusting the layout and number of through-holes according to the location and connection requirements of the device, it also includes: using adaptive through-hole compensation technology, analyzing the power integrity simulation results, and then using EMIR analysis tools to verify the simulation results, and selecting and replacing reasonable PG subcells according to the simulation results to optimize the power network, identify areas with excessive voltage drop, and increase through-holes to balance the voltage distribution.

[0031] Furthermore, by analyzing the power integrity simulation results, areas with excessive voltage drops are identified, including:

[0032] Obtain IC layout design drawings and device layout information to determine the location coordinates of each device, pin connection relationships, and power and ground connection requirements;

[0033] Based on the device layout information, an adaptive algorithm is used to preliminarily plan the distribution of through holes, and necessary through holes are arranged near the device pins to meet the connection requirements of the device. Then, power integrity simulation analysis is performed to obtain the voltage drop distribution in each area and identify the area where the voltage drop exceeds the threshold.

[0034] For areas with excessive voltage drop, determine whether the density of nearby through holes is sufficient. If the density of through holes is insufficient, add through holes nearby.

[0035] Through iterative optimization algorithms, the location and number of through holes are optimized to make the voltage drop distribution in each area as balanced as possible;

[0036] The optimized through-hole layout scheme is simulated and verified for power integrity to determine whether the voltage drop meets the design requirements. If not, the iterative optimization algorithm is returned to generate the IC layout wiring diagram based on the final optimized through-hole layout scheme, connect all device pins and power ground to the corresponding through-holes, and complete the IC layout design.

[0037] The beneficial effects of the present invention are:

[0038] The present invention forms a low-impedance power and ground network and evenly distributed power ground stabilizing capacitors by selecting two layers of topmetal and overlapping them, which not only reduces the impact of noise generated by high-speed and high-performance IP on internal logic blocks, but also uses the ground layer as a shielding layer to reduce noise and electromagnetic interference, ensuring signal integrity and circuit stability; adopts noise isolation technology, sets an isolation area between the IP circuit and the internal logic block, and arranges metal filling in the isolation area to absorb and attenuate noise signals, reducing interference to the internal logic block, and at the same time ensures that the noise isolation structure reaches a preset noise reduction threshold by real-time monitoring and optimizing the design of the isolation area;

[0039] Adopting the layered power network and layered ground network design, multiple power layers and ground layers are constructed on different metal layers, which reduces the equivalent resistance of the network, reduces the network impedance, and sets a shielding layer between the power layer and the ground layer to block the noise conduction path; through the multi-objective optimization method, a metal shielding grid is arranged between PG_Tlayer and PG_Blayer, and the optimal metal shielding grid size and spacing parameters are determined, which minimizes the occupation of wiring resources while ensuring the shielding effect;

[0040] By adopting intelligent through-hole connection mode and adaptive through-hole compensation technology, the layout and number of through-holes are adaptively adjusted according to the location and connection requirements of the device, reducing the introduction of parasitic parameters, and by analyzing the power integrity simulation results, areas with excessive voltage drop are identified, and through-holes are added near these areas to balance the voltage distribution and ensure power integrity. The present invention effectively solves the noise, ground bounce, electromagnetic interference (EMI) and thermal management problems on the power line, which not only improves the signal integrity and stability of the circuit, but also optimizes the wiring efficiency and chip space utilization, improves the economic benefits of the overall design, ensures the reliability and stability of the entire chip, and achieves high shielding effect and minimum wiring resource occupancy. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0042] Figure 1A flowchart of a network layout design method based on Samsung 4nm provided for this application;

[0043] Figure 2 A schematic diagram of the process of arranging metal filling in an isolation area based on a network layout design method of Samsung 4nm provided in this application;

[0044] Figure 3 A schematic diagram of a flow chart of a network layout design method based on Samsung 4nm for adaptively adjusting the layout and number of through holes provided in this application. DETAILED DESCRIPTION

[0045] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0046] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0047] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0048] See also Figure 1-Figure 3 This embodiment provides a network layout design method based on Samsung 4nm, including the following steps:

[0049] S1. Select two layers of topmetal to build a power ground network. The two layers of topmetal include PG_Tlayer and PG_Blayer, which are also the IA layer and IB layer of Samsung's 4nm process.

[0050] S2, PG_Tlayer and PG_Blayer are overlapped, the PG_Tlayer is connected to the power supply to form a low impedance power network, and the PG_Blayer is grounded to form a low impedance ground network;

[0051] S3, form a uniformly distributed power ground stabilizing capacitor between PG_Tlayer and PG_Blayer, the PG_Blayer is connected to the ground network, used to reduce the noise on the power network caused by high-speed and high-performance IP and conduct it to the internal block. Reasonable use can play a shielding role;

[0052] S4. Connect any cell of PG_Tlayer directly downward to the device through a through hole to form a ground network, and then connect PG_Blayer downward to the device through a customized through-hole cell to form a power network.

[0053] Among them, PG_Tlayer represents the power layer, PG_Blayer represents the ground layer, noise represents the noise generated by external factors or high-speed, high-performance IP inside the circuit, block represents the logic block, and shielding represents shielding, which means protecting the signal line from noise and interference through specific layout and connection methods.

[0054] Specifically, the network layout design method based on Samsung's 4nm process realizes a low-impedance network for power and ground by carefully selecting and configuring two layers of topmetal (IA layer as the PG_Tlayer power layer and IB layer as the PG_Blayer ground layer). By overlapping them, evenly distributed power and ground stabilizing capacitors are formed, which effectively reduces the impact of noise generated by high-speed and high-performance IP on internal logic blocks. At the same time, the ground layer is used as a shielding layer to reduce noise and electromagnetic interference, ensuring signal integrity and circuit stability.

[0055] Furthermore, after PG_Blayer is connected to the ground network, it includes: using noise isolation technology, setting an isolation area between the IP circuit and the internal logic block, and arranging metal filling in the isolation area to absorb and attenuate noise signals and reduce interference to the internal logic block.

[0056] Furthermore, the noise isolation technology is used to set an isolation area between the IP circuit and the internal logic block, and metal filling is arranged in the isolation area, specifically including:

[0057] S11, obtain the connection request of PG_Blayer and ground network, determine whether noise isolation processing is required, if necessary, perform the following steps; otherwise, directly establish a network connection;

[0058] S12, according to the preset noise isolation rule, determine the location and size of the isolation area between the IP circuit and the internal logic block, and store the parameter information of the isolation area in the isolation area configuration database;

[0059] S13, obtaining characteristic parameters of various types of metal filling materials from a metal filling material database, and selecting the optimal metal filling material by comparing the noise absorption ability and signal attenuation ability of the materials;

[0060] S14, matching the parameter information of the selected metal filling material with the isolation zone parameters in the isolation zone configuration database, generating a detailed design scheme of the isolation zone, including the layout and thickness of the metal filling, etc.; according to the detailed design scheme of the isolation zone, constructing the isolation zone at a designated position between the IP circuit and the internal logic block, and filling the selected metal material inside the isolation zone to form a complete noise isolation structure;

[0061] S15. After PG_Blayer establishes a connection with the ground network, it monitors the intensity of the noise signal in real time, and transmits the monitoring data to the noise analysis module for analysis to determine the isolation effect of the noise isolation structure; if the noise isolation effect does not reach the preset noise reduction threshold, the isolation area optimization mechanism is triggered to further improve the isolation area's ability to absorb and attenuate noise by adjusting the layout and thickness of the metal filling material until the noise reduction target is achieved.

[0062] Specifically, after PG_Blayer is connected to the ground network, noise isolation technology is used to set an isolation area between the IP circuit and the internal logic block, and metal filling is arranged in the isolation area to effectively absorb and attenuate noise signals and reduce interference to the internal logic block. At the same time, through real-time monitoring and optimization of the design of the isolation area, it is ensured that the noise isolation structure reaches the preset noise reduction threshold, thereby improving the signal integrity and stability of the entire circuit.

[0063] Furthermore, after setting an isolation area between the IP circuit and the internal logic block, it also includes: adopting a layered power network and a layered ground network design, building multiple power layers and ground layers on different metal layers, reducing the equivalent resistance of the network, reducing the network impedance, and setting a shielding layer between the power layer and the ground layer to block the noise conduction path.

[0064] Furthermore, a hierarchical power supply network and a hierarchical ground network design are adopted, specifically including:

[0065] According to the layout of IP circuits and internal logic blocks, determine the location and size of the isolation area, mark the range of the isolation area in the layout diagram, determine the number and arrangement of metal layers for the layered power network and layered ground network, analyze the network equivalent resistance and impedance characteristics under different arrangements through simulation tools, and select the appropriate metal layer arrangement scheme;

[0066] Divide the power layer and ground layer in the layout, determine the area and position of each area according to the power consumption and noise characteristics of the circuit, ensure the integrity and continuity of the power layer and ground layer, analyze the voltage drop and current density distribution of the power layer and ground layer through circuit simulation tools, optimize the wiring topology and line width, and reduce the network equivalent resistance and impedance;

[0067] Insert a shielding layer between the power layer and the ground layer, and use staggered wiring to reduce the coupling of power supply noise and ground bounce noise. Through electromagnetic field simulation, analyze the isolation effect of the shielding layer, and optimize the geometric parameters and wiring method of the shielding layer.

[0068] At the interface between the IP circuit and the internal logic block, set up a dedicated isolation power layer and isolation ground layer to avoid noise interference between different modules. According to the location and number of interfaces, optimize the layout of the isolation power layer and isolation ground layer.

[0069] Globally optimize the power network and ground network of the entire chip, balance the voltage drop and current density in each area, eliminate local hot spots and electromigration risks, and verify the optimized design through power integrity analysis and signal integrity analysis to ensure the reliability and stability of the chip.

[0070] Specifically, by adopting a hierarchical power network and a hierarchical ground network design and setting an isolation area between the IP circuit and the internal logic block, this method effectively reduces the equivalent resistance and impedance of the network, blocks the noise conduction path, optimizes the voltage drop and current density distribution, reduces the coupling of power noise and ground bounce noise, avoids noise interference between different modules, and eliminates local hot spots and electromigration risks. Finally, the optimized design scheme is verified through power integrity and signal integrity analysis to ensure the reliability and stability of the entire chip.

[0071] Furthermore, the PG_Tlayer and PG_Blayer are overlapped, and further include: arranging a metal shielding grid between the PG_Tlayer and the PG_Blayer to form a uniformly distributed shielding structure, and determining the optimal metal shielding grid size and spacing parameters through a multi-objective optimization method to minimize the occupation of wiring resources while ensuring the shielding effect;

[0072] The method for determining the optimal metal shielding grid size and spacing parameters includes: obtaining layout information of PG_Tlayer and PG_Blayer to determine the vertical spacing between the two layers; establishing a three-dimensional model of the metal shielding grid according to the vertical spacing between the power layer and the ground layer, and initializing the grid size and grid spacing parameters; using an electromagnetic field simulation method to analyze the shielding effect under different grid sizes and grid spacings, and obtaining a relationship curve between the shielding effect and the grid parameters; obtaining the relationship between the wiring resource occupancy rate and the grid size and grid spacing, and establishing a mathematical model of the wiring resource occupancy rate; performing multi-objective optimization on the shielding effect relationship curve and the wiring resource occupancy rate model to solve the optimal grid size and grid spacing parameters; updating the three-dimensional model of the metal shielding grid according to the optimal grid parameters to form a uniformly distributed shielding structure; embedding the optimized metal shielding grid model between PG_Tlayer and PG_Blayer to complete the overlapping setting of the two layers, thereby achieving a high shielding effect and minimum wiring resource occupancy.

[0073] Specifically, by arranging a metal shielding grid between PG_Tlayer and PG_Blayer and using a multi-objective optimization method to determine the optimal grid size and spacing parameters, the design not only forms a uniformly distributed shielding structure to achieve an efficient electromagnetic shielding effect, but also minimizes the occupation of wiring resources. While ensuring circuit performance and reducing interference, it optimizes wiring efficiency and chip space utilization, thereby improving the economic benefits of the overall design and circuit reliability.

[0074] Furthermore, a network layout design method based on Samsung's 4nm also includes: using an intelligent through-hole connection method to adaptively adjust the layout and number of through-holes according to the location and connection requirements of the device, and through an optimization algorithm, minimize the number of through-holes and reduce the introduction of parasitic parameters while satisfying the device connection.

[0075] Furthermore, the adaptively adjusting the layout and quantity of the through holes specifically includes:

[0076] S21, according to the location information of the devices in the network layout, determine the connection requirements between the devices, obtain the location coordinates of each device connection, and preliminarily determine the through-hole layout according to the preset rules;

[0077] S22, using an intelligent optimization algorithm, under the premise of satisfying device connection, finding the optimal through-hole layout solution through iterative calculation, optimizing the specific position coordinates of each through-hole according to the optimal through-hole layout solution, and obtaining a refined through-hole layout;

[0078] S23, according to the detailed through-hole layout and in combination with the process requirements, determine the size parameters of each through-hole, calculate the introduced parasitic parameters based on the through-hole layout and the size parameters, and determine whether the design indicators are met;

[0079] Among them, if the parasitic parameters exceed the design indicators, the intelligent optimization algorithm is re-executed until the requirements are met, and finally the optimized through-hole layout design is output.

[0080] Specifically, the network layout design method based on Samsung's 4nm adopts an intelligent through-hole connection method, which can adaptively adjust the layout and number of through-holes according to the location and connection requirements of the device, and use optimization algorithms to minimize the use of through-holes while ensuring that the device connection requirements are met, thereby reducing the introduction of parasitic parameters, optimizing signal integrity, improving circuit performance, and ensuring that the design meets process requirements and design indicators.

[0081] Furthermore, after adaptively adjusting the layout and number of vias according to the location and connection requirements of the device, it also includes: using adaptive via compensation technology, analyzing the power integrity simulation results, and then using EMIR, perc and other analysis tools to verify the simulation results, and selecting and replacing reasonable PG subcells according to the simulation results to optimize the power network, identify areas with excessive voltage drop, and add vias near these areas to balance the voltage distribution and ensure power integrity. Solve the problem of excessive voltage drop in local areas caused by uneven distribution of vias connecting devices to the power layer and the ground layer.

[0082] Among them, PG subcell refers to the basic unit used to build a power network in integrated circuit (IC) design. These subcells include power and ground connection points, through-holes, and possible decoupling capacitors, which are used to form the power distribution network (PDN) of the entire chip. In Samsung's 4nm process, the design of PG subcell is crucial to ensuring the power integrity and signal integrity of the chip.

[0083] Furthermore, by analyzing the power integrity simulation results, areas with excessive voltage drops are identified, including:

[0084] Obtain IC layout design drawings and device layout information to determine the location coordinates of each device, pin connection relationships, and power and ground connection requirements;

[0085] Based on the device layout information, an adaptive algorithm is used to preliminarily plan the distribution of through holes, and necessary through holes are arranged near the device pins to meet the connection requirements of the device. Then, power integrity simulation analysis is performed to obtain the voltage drop distribution in each area and identify the area where the voltage drop exceeds the threshold.

[0086] For areas with excessive voltage drop, determine whether the density of nearby through holes is sufficient. If the density of through holes is insufficient, add through holes near the area.

[0087] By using an iterative optimization algorithm, such as a genetic algorithm or a simulated annealing algorithm, the location and number of through holes are optimized so that the voltage drop distribution in each area is as balanced as possible;

[0088] The optimized through-hole layout scheme is simulated and verified for power integrity to determine whether the voltage drop meets the design requirements. If not, the iterative optimization algorithm is returned to generate the IC layout wiring diagram based on the final optimized through-hole layout scheme, and all device pins and power grounds are connected to the corresponding through-holes to complete the IC layout design.

[0089] Among them, IC layout, that is, integrated circuit layout design, refers to the process of converting the logic diagram of the circuit design into a physical layout on the silicon wafer, including the precise placement of transistors, resistors, capacitors and other components, and the routing of metal wires to achieve electrical connections, while considering factors such as signal integrity, power integrity, electromagnetic compatibility and thermal management to ensure that the circuit's performance, power consumption, reliability and manufacturing cost meet the design requirements.

[0090] Specifically, by adopting adaptive via compensation technology, this design method can analyze the power integrity simulation results, accurately identify areas with excessive voltage drop, and intelligently add vias near these areas to balance the voltage distribution. It effectively solves the problem of excessive voltage drop in local areas caused by uneven distribution of vias connecting devices to the power layer and the ground layer, ensures power integrity, and further optimizes the via layout through an iterative optimization algorithm, ultimately achieving balanced voltage drops in various regions, meeting design requirements, and improving circuit performance and reliability.

[0091] This embodiment forms a uniformly distributed low-impedance power ground network and voltage-stabilizing capacitors through the carefully designed two-layer topmetal (PG_Tlayer and PG_Blayer) overlap setting, which provides a relatively uniform low-impedance groundshielding network for the underlying logic block, effectively reducing noise interference and ensuring clear signal transmission;

[0092] Secondly, a very strong power ground network with low impedance is built, which is crucial for high-speed, high-performance logic block products. It can provide a higher quality power ground network to ensure the stability of the circuit under high frequency and high load changes, thereby improving the reliability and performance of the entire system;

[0093] Finally, through a large number of evenly distributed shielding networks, electromagnetic interference is better suppressed and the circuit is protected from external electromagnetic interference. At the same time, the large-scale use of evenly distributed metal networks has a positive impact on the heat dissipation and stress distribution of the chip, improving the thermal management and structural stability of the chip, and further enhancing the durability and long-term reliability of the chip.

[0094] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A network layout design method based on Samsung 4nm, characterized by: The steps include: Select two layers of topmetal to build a power ground network, wherein the two layers of topmetal include a power layer and a ground layer; The power layer and the ground layer are overlapped, the power layer is connected to the power source to form a low-impedance power network, and the ground layer is grounded to form a low-impedance ground network; Forming evenly distributed power-to-ground voltage-stabilizing capacitors between the power layer and the ground layer, the ground layer being connected to the ground network; Connect any cell of the power layer directly downward to the device through a through hole to form a ground network, and then connect the ground layer downward to the device through a customized through-hole cell to form a power network; After the ground layer is connected to the ground network, it includes: using noise isolation technology to set up an isolation area between the IP circuit and the internal logic block, and arranging metal filling in the isolation area to absorb and attenuate noise signals; The noise isolation technology is used to set an isolation area between the IP circuit and the internal logic block, and arrange metal filling in the isolation area, specifically including: Obtain the connection request between the ground layer and the ground network, and determine whether noise isolation processing is required. If necessary, perform the following steps; otherwise, directly establish a network connection; According to the preset noise isolation rules, determine the location and size of the isolation area between the IP circuit and the internal logic block, and store the parameter information of the isolation area in the isolation area configuration database; Obtain characteristic parameters of various types of metal filling materials from the metal filling material database, and select metal filling materials by comparing the noise absorption and signal attenuation capabilities of the materials; Matching the parameter information of the selected metal filling material with the isolation zone parameters in the isolation zone configuration database to generate a detailed design plan for the isolation zone; constructing the isolation zone at a designated location between the IP circuit and the internal logic block according to the detailed design plan for the isolation zone, and filling the isolation zone with the selected metal material to form a complete noise isolation structure; After the connection between the stratum and the ground network is established, the intensity of the noise signal is monitored in real time, and the monitoring data is transmitted to the noise analysis module for analysis to determine the isolation effect of the noise isolation structure; when the noise isolation effect does not reach the preset noise reduction threshold, the isolation area optimization mechanism is triggered.

2. A network layout design method based on Samsung 4nm according to claim 1, characterized in that: After setting up an isolation area between the IP circuit and the internal logic block, it also includes: adopting a layered power network and a layered ground network design, building multiple power layers and ground layers on different metal layers, and setting a shielding layer between the power layer and the ground layer.

3. A network layout design method based on Samsung 4nm according to claim 2, characterized in that: Adopt hierarchical power network and hierarchical ground network design, including: According to the layout of IP circuits and internal logic blocks, determine the location and size of the isolation area, mark the range of the isolation area in the layout diagram, determine the number and arrangement of metal layers for the layered power network and layered ground network, analyze the network equivalent resistance and impedance characteristics under different arrangements through simulation tools, and select the metal layer arrangement scheme; Divide the power layer and ground layer areas in the layout, determine the area and position of each area according to the power consumption and noise characteristics of the circuit, analyze the voltage drop and current density distribution of the power layer and ground layer through circuit simulation tools, and optimize the wiring topology and line width; Insert a shielding layer between the power layer and the ground layer, analyze the isolation effect of the shielding layer through electromagnetic field simulation, and optimize the geometric parameters and wiring method of the shielding layer; At the interface between the IP circuit and the internal logic block, a dedicated isolation power layer and isolation ground layer are set up, and the layout of the isolation power layer and isolation ground layer is optimized according to the location and number of the interfaces.

4. A network layout design method based on Samsung 4nm according to claim 1, characterized in that: The power layer and the ground layer are overlapped, and further comprising: arranging a metal shielding grid between the power layer and the ground layer to form a uniformly distributed shielding structure, and determining the size and spacing parameters of the metal shielding grid by a multi-objective optimization method; The method for determining the size and spacing parameters of a metal shielding grid includes: obtaining layout information of a power layer and a ground layer, and determining the vertical spacing between the two layers; establishing a three-dimensional model of a metal shielding grid according to the vertical spacing between the power layer and the ground layer, and initializing the grid size and grid spacing parameters; using an electromagnetic field simulation method to analyze the shielding effect under different grid sizes and grid spacings, and obtaining a relationship curve between the shielding effect and the grid parameters; obtaining the relationship between the wiring resource occupancy rate and the grid size and the grid spacing, and establishing a mathematical model of the wiring resource occupancy rate; performing multi-objective optimization on the shielding effect relationship curve and the wiring resource occupancy rate model, and solving the grid size and grid spacing parameters; updating the three-dimensional model of the metal shielding grid according to the grid parameters to form a uniformly distributed shielding structure; and embedding the optimized metal shielding grid model between the power layer and the ground layer to complete the overlapping setting of the two layers.

5. The network layout design method based on Samsung 4nm according to claim 1, characterized in that: Also includes: An intelligent through-hole connection method is adopted to adaptively adjust the layout and number of through-holes according to the location and connection requirements of the device.

6. A network layout design method based on Samsung 4nm according to claim 5, characterized in that: The adaptively adjusting the layout and quantity of the through holes specifically includes: According to the location information of the devices in the network layout, the connection requirements between the devices are determined, the location coordinates of each device connection are obtained, and the through-hole layout is preliminarily determined according to the preset rules; Using intelligent optimization algorithms, under the premise of satisfying device connection, through iterative calculation, a through-hole layout solution is found, and the specific position coordinates of each through-hole are optimized according to the through-hole layout solution to obtain a refined through-hole layout; According to the detailed through-hole layout and combined with the process requirements, the size parameters of each through-hole are determined. Based on the through-hole layout and size parameters, the introduced parasitic parameters are calculated to determine whether the design indicators are met; Among them, if the parasitic parameters exceed the design indicators, the intelligent optimization algorithm is re-executed until the requirements are met, and then the optimized through-hole layout design is output.

7. A network layout design method based on Samsung 4nm according to claim 5, characterized in that: After adaptively adjusting the layout and number of vias according to the device location and connection requirements, it also includes: using adaptive via compensation technology, analyzing the power integrity simulation results, and then using EMIR analysis tools to verify the simulation results, and selecting and replacing reasonable PG subcells based on the simulation results to optimize the power network, identify areas with excessive voltage drop, and increase vias to balance the voltage distribution.

8. A network layout design method based on Samsung 4nm according to claim 7, characterized in that: Analyze power integrity simulation results to identify areas of excessive voltage drop, including: Obtain IC layout design drawings and device layout information to determine the location coordinates of each device, pin connection relationships, and power and ground connection requirements; Based on the device layout information, an adaptive algorithm is used to preliminarily plan the distribution of through holes, and necessary through holes are arranged near the device pins to meet the connection requirements of the device. Then, power integrity simulation analysis is performed to obtain the voltage drop distribution in each area and identify the area where the voltage drop exceeds the threshold. For areas with excessive voltage drop, determine whether the density of nearby through holes is sufficient. If the density of through holes is insufficient, add through holes nearby. Through iterative optimization algorithms, the location and number of through holes are optimized to make the voltage drop distribution in each area as balanced as possible; The optimized through-hole layout scheme is simulated and verified for power integrity to determine whether the voltage drop meets the design requirements. If not, the iterative optimization algorithm is returned to generate the IC layout wiring diagram based on the optimized through-hole layout scheme, connect all device pins and power ground to the corresponding through-holes, and complete the IC layout design.

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