A JBIG Arithmetic Coding and Decoding Method and System

Abstract

The present invention relates to a JBIG arithmetic coding and decoding method and system. The method is implemented based on the architecture of a QM encoder and a decoder. The QM encoder includes an adaptive coding module and a coding unit, and the decoder includes an adaptive decoding module and a decoding unit. The method includes: step 1) generating context CX, step 2) JBIG arithmetic coding process, and step 3) JBIG arithmetic decoding process. The JBIG arithmetic coding and decoding method and system of the present invention improve the throughput of the engine, solve the problem of data dependence conflicts in the pipeline, can process images at a rate close to 1 pixel per clock cycle, have a fast processing speed, the performance can be improved by about 40%, improve the efficiency of image compression and processing, have strong compatibility, and can interact and communicate with other JBIG-compatible devices.

Description

Technical Field

[0001] The present invention relates to the technical field of image encoding and decoding in computers, and particularly relates to a JBIG arithmetic encoding and decoding method and system. Background Art

[0002] The basic principle of data compression is to decompose a data set into a set of independent events, and then represent these events with as few symbols as possible. Compression is achieved if shorter codewords can be used to represent more likely events and longer codewords can be used to represent less likely events. Given a source, a set of independent events A is output from the data set S, and the average number of bits required to encode the output of the source is: H(S)=-∑P(A i )log P(A i ), where P(Aj) is the probability that event A occurs, and the quantity H is called the entropy of s. Shannon proved that for lossless compression, the minimum average number of bits that an algorithm can use to encode the output of a source is equal to the entropy of the source. Arithmetic coding is a commonly used method for generating variable-length codes, which can encode data at a rate arbitrarily close to the entropy; when dealing with sources with highly skewed probabilities, arithmetic coding provides a better compression ratio than other coding methods (such as Huffman coding); arithmetic coding can also be used in combination with an adaptive model that provides probability estimates for events based on the statistical history of the source; these characteristics make arithmetic coding very suitable as an encoder for image compression.

[0003] In arithmetic coding, a unique identifier or codeword is assigned to the data sequence to be encoded, and the codeword is selected from the unit interval [0,1); since there are an infinite number of available codewords in this interval, any data sequence can be uniquely identified, and longer sequences are more precise and thus represented by longer fractions; when encoding a data sequence, first use the cumulative distribution function of the random variable associated with the source to divide the unit interval into subintervals, and the size of the subintervals is proportional to the probability of the symbol appearing; the algorithm selects the corresponding interval as the current interval according to the first symbol in the sequence; the current interval is divided into subintervals again using the same method, and the next symbol in the sequence indicates which subinterval to select; this process is repeated continuously until the end of the sequence is reached.

[0004] In 1993, the Joint Bi-level Image Experts Group (JBIG) of the International Organization for Standardization (ISO), the International Electrotechnical Commission (IEC), and the Consultative Committee for International Telegraph and Telephone (CCITT) developed a set of standard bi-level image coding standards, which is informally referred to as JBIG or JBIG1. The JBIG standard is a lossless compression method based on arithmetic coding and context CX modeling; this method has adaptive image characteristics and is highly robust to different types of images such as scanned images, printed characters, and halftone images. JBIG provides performance improvements over algorithms based on Huffman coding. Although designed for binary images, the JBIG standard can also be used to compress grayscale and color images by independently encoding each pixel, as if each pixel were a separate binary image. The compression engine defined in the JBIG standard is called the QM encoder, and the QM encoder is a finite-precision implementation of a binary adaptive algorithm encoder. Arithmetic coding represents a data sequence by sequentially dividing intervals into sub-intervals, where the size of the sub-intervals is proportional to the occurrence probability of each symbol in the sequence, and then selects a sub-interval based on the occurrence of each symbol in the sequence.

[0005] The QM encoder (QM-Encoder in the encoding engine and QM-Decoder in the decoding engine) performs all arithmetic processing in the JBIG image compression algorithm. As the most complex unit in the JBIG image compression algorithm, the design of the QM encoder is crucial for the performance of the engine. Since the QM encoder is a hardware implementation of the QM encoder algorithms provided by JBIG, these algorithms have been carefully studied to utilize as much parallelism as possible to obtain optimal performance. Summary of the Invention

[0006] In view of the problems in the prior art, on the one hand, the present invention provides a JBIG arithmetic coding and decoding method, which is implemented based on the architecture of a QM encoder and a decoder. The QM encoder includes an adaptive coding module and a coding unit, and the decoder includes an adaptive decoding module and a decoding unit;

[0007] The method includes: Step 1) generating context CX, Step 2) the JBIG arithmetic coding process, and Step 3) the JBIG arithmetic decoding process; Step 2) consists of Step S2-1: the processing flow of the adaptive coding module and Step S2-2: the processing flow of the coding unit, and Step 3) consists of Step S3-1: the processing flow of the adaptive decoding module and Step S3-2: the processing flow of the decoding unit;

[0008] Step 1) generating context CX includes: the context CX construction module reads pixels in the image strip from the memory to generate a 12-bit context CX and the pixel to be encoded D;

[0009] In step 2), step S2-1: the processing flow of the adaptive coding module includes:

[0010] After the adaptive coding module receives a request to encode a pixel, it reads an address in decimal from the context CX and stores it in the first context CX memory; then it performs a simplified read to generate a 7-bit valid context CX, generates an index value Index based on the decimal value corresponding to the valid context CX, and stores the context CX, the valid context CX, and the index value Index in the first context CX memory using the index value Index as the write address.

[0011] The first selector reads the index value Index and the most probable symbol MPS corresponding to the given context CX from the lookup table in the first context CX memory. The first selector determines whether to update the index value Index according to the first decision rule and then outputs the updated or unupdated new index value Index, and selects the new most probable symbol MPS corresponding to the new index value Index, and outputs the new index value Index, the new most probable symbol MPS, and the probability table Qe; then it is determined by the second selector and fed back to the encoding unit for the index value Index, the most probable symbol MPS, and the probability table Qe for arithmetic coding.

[0012] The first decision rule is: determine whether the target pixel is the most probable symbol; if the target pixel is the most probable symbol, then do not update the index value Index and directly output the index value Index; if the target pixel is not the most probable symbol, then update the index value Index and output the new index value Index.

[0013] In step 2), step S2-1: the processing flow of the encoding unit includes:

[0014] The pixel D to be encoded, the most probable symbol MPS, the index value Index, and the probability table Qe delivered by the adaptive coding module are subjected to arithmetic coding.

[0015] Secondly, determine whether the first register A and the first register C need to perform renormalization. The probability table Qe assigns A to the first register A, and A corresponds to the least probable symbol LPS; and when A = A << 1, the renormalization stage is executed; in the renormalization stage, the values of the first register C and the first register A are doubled until A is greater than 0x8000.

[0016] Next, perform the arithmetic coding. The arithmetic coding includes: the probability table Qe is doubled by shifting left through a 1-bit shifter, and the first register A and the first register C perform arithmetic operations and logical operations, and then are updated to the first register A and the first register C; finally, after encoding all the pixels in the strip, the QM encoder executes the FLUSH process to output the compressed pixel SCD;

[0017] The precisions of the first register C and the first register A are 28 bits and 16 bits respectively. The first register C is divided into two parts, Clow and Chigh, where Clow represents the lower 16 bits of the first register C, and Chigh represents the higher 12 bits of the first register C;

[0018] At the end of the arithmetic coding of each strip, the flush of the first register C executed includes a CLEARBITS process that clears the trailing bits in the compressed data stream to zero. The CLEARBITS process is: calculate TEMP = (A - 1 + C) & 0xffff0000 = A - 1 + Clow, compare TEMP < C, and check the carry of the calculation; if the comparison TEMP < C is true, the carry is 0; if the comparison TEMP < C is false, the carry is 1 or Clow = 0;

[0019] Where A is the assignment of the first register A, and C is the assignment of the first register C.

[0020] In the present invention, the most probable symbol MPS is a 1-bit value representing the more probable color in the pixel, and the index value Index is a 7-bit value used to index the probability table Qe containing the numerical values required for encoding.

[0021] Furthermore, in the JBIG arithmetic coding and decoding method of the present invention, in the arithmetic coding, the arithmetic operations and logical operations performed by the first register C and the first register A are as follows:

[0022] A temp = A - Qe(1)

[0023] C temp = C + A temp (2)

[0024] A temp < Qe(3)

[0025] A < 2 * Qe(4)

[0026] Where the implementation of formula (4) takes precedence over formula (3), and the addition operation in formula (2) is implemented as a carry-select adder.

[0027] Further, in the JBIG arithmetic coding and decoding method of the present invention, in step 3), in step S3-1: the processing flow of the adaptive decoding module includes: reading the first 8 bits of the context CX from the context CX register as an address, and decoding the pixel value corresponding to the 9th bit in the context CX; when decoding the last bit of the context CX, there are two index values Index0 and Index1, corresponding to two most-probable symbols MPS0 and MPS1 respectively, which are converted into two probability tables Qe running in parallel.

[0028] The two index values Index0 and Index1, the two most-probable symbols MPS0 and MPS1, as well as the pixel to be decoded SCD and the decoding unit feedback signal jointly output a new index value Index and a new most-probable symbol MPS through a multiplexer; the two probability tables Qe running in parallel, and the pixel to be decoded SCD and the decoding unit feedback signal jointly output a new probability table Qe through another multiplexer; at the same time, the context CX of the context CX register is updated.

[0029] In step 3), in step S3-2: the processing flow of the decoding unit includes: the pixel to be decoded SCD, the new most-probable symbol MPS and the new probability table Qe are subjected to renormalization or arithmetic decoding.

[0030] The precisions of the second register C and the second register A in the decoding unit are 24 bits and 16 bits respectively. The second register C is divided into Clow -2 and Chigh -2 two parts, and Clow -2 represents the lower 8 bits of the second register C, and Chigh -2 represents the higher 16 bits of the second register C; and Clow -2 is only used to read the incoming compressed data stream and is shifted to the high position during renormalization.

[0031] In the arithmetic decoding, the new probability table Qe is shifted left to double, and the second register A is shifted left to perform arithmetic and logical operations; an 8-bit shift is performed when initializing the second register C at the beginning of each strip, and only Chigh -2 in the second register C performs arithmetic and logical operations; finally, the original pixel D is restored.

[0032] Further, in the arithmetic decoding unit of the JBIG arithmetic coding and decoding method of the present invention, the arithmetic and logical operations performed by the second register A and the second register C are as follows:

[0033] A temp = A - Qe (1)

[0034] A < 2 * Qe (4)

[0035] C high -A temp <0 (7)

[0036] C high_temp =C high -A temp (6)

[0037] Wherein, A is the assignment value of the second register A, and C high is Chigh -2 .

[0038] Furthermore, in the JBIG arithmetic coding and decoding method of the present invention, the implementation manner of updating the index value Index and the output probability value Qe is as follows:

[0039] Based on the input old index value Index, NLPS-I lookup table, NMPS-I lookup table, NLPS-Qe lookup table, and NMPS-Q lookup table are combined and created;

[0040] Through the NLPS-I lookup table and NMPS-I lookup table, a new index value Index is output;

[0041] Through the NLPS-Qe lookup table and NMPS-Q lookup table, a 16-bit probability value Qe corresponding to the next low probability symbol LPS and the next high probability symbol MPS defined in the original table is output, and then the final probability value Qe is obtained through two multiplexers.

[0042] In the present invention, the NLPS-I lookup table, NMPS-I lookup table, NLPS-Qe lookup table, and NMPS-Qe lookup table can be obtained by combining the NLPS and ST columns, NMPS and ST columns, NLPS and LSZ columns, and NMPS and LSZ columns in the PET table of the standard ITU-T T.82 to obtain the NLPS-I lookup table, NMPS-I lookup table, NLPS-Qe lookup table, and NMPS-Qe lookup table.

[0043] Furthermore, in the JBIG arithmetic coding and decoding method of the present invention, the first context CX memory is configured with a width of 32 bits and a depth of 256 bits; data is read in an asynchronous manner or written into the first context CX memory in a synchronous manner.

[0044] Furthermore, in the JBIG arithmetic coding and decoding method of the present invention, the coding unit uses a multiplexer to select the final assignment values allocated to the first register A and the first register C.

[0045] Further, in the JBIG arithmetic coding and decoding method of the present invention, in the arithmetic coding, in the carry-select adder, the 16-bit addition Clow + A temp determines the lower 16 bits of C temp , and the selection value Chigh or Chigh + 1 of the carry-select adder is used as the upper 12 bits of C temp .

[0046] On the other hand, the present invention provides a JBIG arithmetic coding and decoding system, which is a system based on the JBIG arithmetic coding and decoding method described in any one of the above. The system includes: a context CX construction module, a QM encoder, and a decoder. The QM encoder includes an adaptive coding module and a coding unit, and the decoder includes an adaptive decoding module and a decoding unit;

[0047] The adaptive coding module is configured with a first context CX register, a first context CX memory, a first selector, and a second selector. The coding unit is configured with a first register A and a first register C. The adaptive decoding module is configured with a context CX register and two multiplexers. The decoding unit is configured with a second register A and a second register C.

[0048] Further, in the JBIG arithmetic coding and decoding system of the present invention, the context CX construction module is configured to: tell the QM encoder to execute the INITENC process at the start of each strip; after INITENC is completed, the context CX construction module prepares to generate a context CX and a pixel D for the first pixel of the image and tells the QM encoder to execute the ENCODE process; after all the pixels in the stripe are encoded, the context CX construction module instructs the QM encoder to execute the FLUSH process; when the FLUSH process ends, the encoding of the strip is completed, and the compressed pixel SCD is obtained.

[0049] In the present invention, the context CX construction module can be configured to support the generation of context CX for three-line and two-line templates, and the reused context CX for encoding typical predicted pseudo-pixels in different templates is mapped to the same value, improving the encoding flexibility and consistency.

[0050] Compared with the prior art, the present invention has the following beneficial technical effects:

[0051] (1) The JBIG arithmetic coding and decoding method and system of the present invention adopts a pipeline architecture to design the QM-Coder Unit, divides the processing of each pixel into multiple stages, improves the throughput of the engine, and achieves the goal of processing nearly 1 pixel per clock cycle. The data forwarding mechanism is used to solve the data dependence conflict problem in the pipeline, and the rearrangement stage is optimized to reduce the impact of pipeline resource conflicts. In the QM-Encoder Unit, according to the characteristics of register A when encoding the most probable symbol MPS, a 1-bit shift logic is added, which reduces the extra cycles required for frequent single-bit shifts without significantly increasing the cycle time of the engine.

[0052] (2) The JBIG arithmetic coding and decoding method and system of the present invention can process images at a rate close to 1 pixel per clock cycle, with a fast processing speed. When the typical prediction option is enabled, the performance can be improved by about 40%, which improves the efficiency of image compression and processing. It conforms to the JBIG standard, has strong compatibility, and can interact and communicate with other JBIG-compatible devices. It can be applied to various fields such as fax devices, digital printing and copying devices, etc., to meet the image processing needs of different scenarios. Through reasonable hardware resource allocation and algorithm optimization, the utilization rate of resources is improved, and the cost and power consumption of the system are reduced. Brief Description of the Drawings

[0053] Figure 1 It is a schematic diagram of the arithmetic coding adaptive module in the specific embodiment of the present invention;

[0054] Figure 2 It is a schematic diagram of the arithmetic coding unit in the specific embodiment of the present invention;

[0055] Figure 3 It is a schematic diagram of the arithmetic decoding adaptive module in the specific embodiment of the present invention;

[0056] Figure 4 It is a schematic diagram of the arithmetic decoding unit in the specific embodiment of the present invention;

[0057] Figure 5 It is a schematic diagram of the processing flow of QM-coder in the specific embodiment of the present invention;

[0058] Figure 6 It is a schematic diagram of updating the index value I and the probability Qe value in the specific embodiment of the present invention;

[0059] Figure 7 It is a schematic diagram of the context CX three-line template in the specific embodiment of the present invention;

[0060] Figure 8 It is a schematic diagram of the context CX two-line template in the specific embodiment of the present invention;

[0061] Figure 9 It is a schematic diagram of a three-line template of context CX containing virtual pixels in the specific implementation manner of the present invention.

[0062] Figure 10 It is a schematic diagram of a two-line template of context CX containing virtual pixels in the specific implementation manner of the present invention. Specific implementation manner

[0063] For a clearer understanding of the technical features, objectives, and effects of the present invention, the specific implementation manner of the present invention will now be described in detail with reference to the accompanying drawings. The described specific implementation manner is only a part of the specific implementation manners of the present invention, rather than all of the specific implementation manners. Based on the specific implementation manner of the present invention, all other specific implementation manners obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. For those not specified in the specific implementation manner, they are carried out according to conventional conditions or conditions recommended by the manufacturer.

[0064] When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. For example, the probability Qe in the drawings represents the value of the probability Qe; to distinguish between the decoding and encoding process registers, a part of the registers and memories in the encoding process are all defined as "first", and a part of the registers and memories in the decoding process are all defined as "second". The following exemplary described implementation manners do not represent all implementation manners consistent with the present disclosure. On the contrary, they are only examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims. The terms used in the present disclosure are only for the purpose of describing specific specific implementation manners, and are not intended to limit the present disclosure. Specific implementation manner one:

[0066] A JBIG arithmetic coding and decoding method of the present invention, the above method is implemented based on the architecture of a QM encoder and decoder. The above QM encoder includes an adaptive coding module and a coding unit, and the above decoder includes an adaptive decoding module and a decoding unit;

[0067] The above method includes: Step 1) generating context CX, Step 2) JBIG arithmetic coding process, and Step 3) JBIG arithmetic decoding process; the above Step 2) consists of Step S2-1: the processing flow of the adaptive coding module and Step S2-2: the processing flow of the coding unit, and the above Step 3) consists of Step S3-1: the processing flow of the adaptive decoding module and Step S3-2: the processing flow of the decoding unit;

[0068] The above Step 1) generating context CX includes: the context CX construction module reads the pixels in the image strip from the memory to generate a 12-bit context CX and the pixel D to be encoded;

[0069] In step 2) above, step S2-1: the processing flow of the adaptive coding module includes:

[0070] After the above adaptive coding module receives a request to encode a pixel, it reads the address in decimal from the above context CX and stores it in the first context CX memory; then it performs simplified reading to generate a 7-bit valid context CX, generates an index value Index with the decimal value corresponding to the valid context CX, and stores the context CX, the valid context CX, and the index value Index in the first context CX memory with the index value Index as the write address;

[0071] In this embodiment, the input context CX is 12 bits. According to the 2^12 = 4096 possible cases that the template pixel points may generate, using the corresponding decimal value as the read address, the 4096 possible context CXs are stored in the context CX register RAM; by simplifying the 4096 possible cases, the last seven bits are read and temporarily stored effectively, that is, &0x7f, to generate a 7-bit valid context CX, generate an index value Index with the decimal value corresponding to the valid context CX, and store Index and CX in the ROM with the index value Index as the write address.

[0072] The first selector reads the index value Index and the most probable symbol MPS corresponding to the given context CX from the lookup table of the first context CX memory. The first selector determines whether to update the index value Index according to the first decision rule and then outputs the updated or unupdated new index value Index, and selects the new most probable symbol MPS corresponding to the new index value Index, and outputs the new index value Index, the new most probable symbol MPS, and the probability table Qe; then it is determined by the second selector and fed back to the above encoding unit for the index value Index, the most probable symbol MPS, and the probability table Qe for arithmetic coding;

[0073] The above first decision rule is: determine whether the target pixel is the most probable symbol; if the target pixel is the most probable symbol, then do not update the index value Index and directly output the index value Index; if the target pixel is not the most probable symbol, then update the index value Index and output the new index value Index;

[0074] In step 2) above, step S2-1: the processing flow of the encoding unit includes:

[0075] The to-be-encoded pixel D, the most probable symbol MPS, the index value Index, and the probability table Qe delivered by the above adaptive coding module are subjected to arithmetic coding;

[0076] Secondly, determine whether the first register A and the first register C need to perform renormalization. The probability table Qe assigns the value A to the first register A, and the above A corresponds to the low probability symbol LPS; and when A = A << 1, the renormalization stage is executed; in the above renormalization stage, the values of the first register C and the first register A are doubled until A is greater than 0x8000;

[0077] Thirdly, perform the arithmetic coding. The arithmetic coding includes: the probability table Qe is doubled by shifting left through a 1-bit shifter, and the first register A and the first register C perform arithmetic operations and logical operations, and then are updated to the first register A and the first register C; finally, after encoding all the pixels in the strip, the above QM encoder executes the FLUSH process to output the compressed pixel SCD;

[0078] The precisions of the above first register C and the first register A are 28 bits and 16 bits respectively. The first register C is divided into two parts, Clow and Chigh, and Clow represents the lower 16 bits of the first register C, and Chigh represents the higher 12 bits of the first register C;

[0079] At the end of each strip arithmetic coding, the refresh of the first register C executed includes a CLEARBITS process that clears the trailing bits in the compressed data stream to zero. The above CLEARBITS process is: calculate TEMP = (A - 1 + C) & 0xffff0000 = A - 1 + Clow, compare TEMP < C, and check the carry of the calculation; if the comparison TEMP < C is true, the carry is 0; if the comparison TEMP < C is false, the carry is 1 or Clow = 0;

[0080] Wherein, A is the assignment of the above first register A, and C is the assignment of the above first register C.

[0081] The above high probability symbol MPS is a 1-bit value representing the more likely color in the pixel, and the above index value Index is a 7-bit value used to index the probability table Qe containing the numerical values required for encoding.

[0082] In the present invention, during the execution of the CLEARBITS process, the selection part in the carry-select adder is reused to select the high value high. However, the logic for determining how to make the selection is different from the logic used in the encoding process. The encoder uses an in-line 1-bit shifter to handle the unit renormalization of the C and A registers without the need for additional clock cycles. This creates many possibilities when assigning the next value to the C and A registers. The possible assignments of the A register are: Clow = 0

[0083] In some embodiments, such as Figure 1As shown, after receiving a request to encode a pixel, the QM encoder first reads from memory the most probable symbol MPS and the index value Index of the probability corresponding to the given context CX. The most probable symbol MPS is a 1-bit value, and the most probable symbol MPS represents the color of the more probable symbol in the pixel; the index value Index is a 7-bit value used to index the probability table Qe containing the numerical values required for encoding. The most probable symbol MPS and the index value Index together capture the probability table Qe of the adaptive probability estimation associated with the specific context CX. Using the index value Index as an index, the adaptive encoding module and the adaptive decoding module read information such as the values Qe, NMPS, NLPS, and the SW index value IndexTCH from the internal ROM table. Qe is the size of the LPS sub-interval; NLPS indicates that the next probability estimation state is the less probable symbol, NMPS indicates that the next probability estimation state is the most probable symbol, and when renormalization is required, it is the estimation state of the LPS and the most probable symbol MPS observations; finally, the SW index value IndexTCH indicates whether the value of the most probable symbol MPS should be inverted when the index value Index given by NLPS changes. After reading from the ROM table, the encoding module and the decoding module perform the arithmetic encoding, arithmetic decoding, and logical operations required to process the specific pixel, and update the value registers and memory as needed. Depending on the results of the arithmetic and logical operations, it may be necessary to renormalize registers A and C. When pixel processing needs to be completed, the JB index value IndexG encoder renormalizes the appropriate registers and updates the values. A multi-stage pipeline is designed to increase the throughput of the JB index value IndexG encoder, and thus continuous pixel overlap can be processed.

[0084] The renormalization operation cannot run in parallel with the stage code. Both stages operate on the values in registers A and C, resulting in a resource conflict. Before the processing of the transformation stage of the previous pixel is completed, the processing of the encoding stage of the subsequent pixel cannot start immediately. When entering the renormalization stage, the pipeline process will stop temporarily.

[0085] As Figure 1As shown, the adaptive module in the arithmetic coding process, where the input is the 12-bit context CX. According to the 2^12 = 4096 possible cases that the template pixel points may generate, using their corresponding decimal values as read addresses, the 4096 possible contexts CX are stored. By simplifying the 4096 possible cases, the last seven bits are taken for reading and effectively stored, i.e., &0x7f, to generate a 7-bit effective context CX. Using the decimal value corresponding to the effective context CX to generate an index value Index, and using the index value Index as the write address to store the index value Index and CX. The context CX register is configured as a ROM with a 32-bit width and a depth of 256. In some other embodiments, the same configuration needs to be maintained in the decoder so that four pairs of index values Index and most probable symbols MPS in the adaptive memory can be accessed at one time. For design consistency, the same configuration is maintained in the encoder. The data is read asynchronously and written to the context CX register synchronously. The adapter reads CX and D inputs from the context CX construction module and provides the probability Qe value, the most probable symbol MPS, and D associated with the same pixel for processing to the encoder. In addition, the self-adaptive module updates the context CX register and internal registers using the results of the encoder. The two bits in the context CX corresponding to the two pixels immediately before the target pixel are not generated in time to become part of the memory address. By only using the available 7 bits of the context CX as the address, the adaptive module reads the index value Index and the most probable symbol MPS value of all four possible values of CX. When decoding the last two bits of the context CX, a fast multiplexer can be used to select the appropriate pair.

[0086] In some embodiments, the simple process is as follows: passing through a selector, which is controlled by the feedback of the encoder core unit, to decide whether to use the new index value Index. Through the updated index value Index, select the value of the current most probable symbol MPS, output to the probability table Qe, and a selector controlled by the feedback value of the encoder core unit to decide whether to send the current index value Index and the most probable symbol MPS to the encoder core unit for arithmetic coding. The probability Qe value corresponding to the output current index value Index is also controlled by the selector of the feedback value of the encoder core unit to decide whether to send the current Qe to the encoder for arithmetic coding.

[0087] As Figure 1As shown, the feedback value of the encoder core unit also acts on four parts: to generate the next index value next index value Index and the next most probable symbol NMPS. The next index value Index and NMPS will be used for the pre-stage selection values of data memories A and B, and act on the selector controlled by the feedback of the encoder core unit. For one selector, it selects to write the value in data memory B and the next index value Index into the context CX memory. For two selectors, one is the pre-stage selection value of data memory A, and the other is the pre-stage selection value of data memory B.

[0088] As Figure 1 shown, Qe, the index value Index, the most probable symbol MPS output by the adaptive module in the arithmetic coding process, and the unprocessed pixel D to be encoded are simultaneously sent to the arithmetic coding core unit for arithmetic coding.

[0089] As Figure 2 shown, the renormalization stage doubles the values of the first register C and the first register A until A is greater than 0x8000. In hardware design, this means shifting the first register C and the first register A to the left until the 15th bit of register A becomes 1. By implementing a shift and a circuit to detect the number of leading 0s in register A, the renormalization stage can be easily combined with the code stage to eliminate resource conflicts in the pipeline. However, the additional hardware significantly increases the delay of the engine critical path, thus slowing down the clock speed. A compromise solution involves recognizing that when encoding the most probable symbol MPS, the first register A only needs to be doubled at most once to make its value greater than 0x8000.

[0090] In some embodiments, as Figure 2 shown, in the above arithmetic coding, the arithmetic operations and logical operations performed by the above first register C and the above first register A are as follows:

[0091] A temp = A - Qe (1)

[0092] C temp = C + A temp (2)

[0093] A temp < Qe (3)

[0094] A < 2 * Qe (4)

[0095] Wherein, A is the value assigned to the first register A, and C is the value assigned to the first register C; the implementation of the above formula (4) takes precedence over the above formula (3), and the addition operation in the above formula (2) is implemented as a carry selection adder. In the present invention, the hardware implementation of the above formula (4) is better than that of formula (3) because the comparison can be made without waiting for the result of formula (1). Moreover, the implementation of formula (4) does not require more hardware than formula (3) because the doubling of Qe can be achieved by a left shift operation. Due to the difference in precision between the first register C and the above first register A, the addition operation in formula (2) is implemented as a carry selection adder to reduce the delay of the carry ripple.

[0096] In some embodiments, since the assignment of the probability estimate Qe to the first register A corresponds to the encoding of the LPS, this assignment is always followed by renormalization. The assignment A=A<<1 is only used to perform the renormalization phase when multi-bit renormalization is required. The possible assignments of the C register are:

[0097] C=(C+A temp )<<1

[0098] C=C<<1

[0099] C=(temp+0x8000)<<1

[0100] C=temp<<1

[0101] The encoder uses a multiplexer to select the final value assigned to the first register C and the first register A.

[0102] In some embodiments, the high bit and the low bit are selected and assigned respectively because a carry select adder is used when calculating the next value of the assignment C of the first register C. The decision logic in the encoder determines how the encoder selects the correct values ​​for the first register C and the first register A, and whether the adapter needs to update the data in the first context CX register memory.

[0103] In some embodiments, Figure 2 As shown, the pixel D to be encoded and the high probability symbol MPS are determined through an XOR gate whether to perform low probability encoding. The specific rule is: D^MPS=1, low probability encoding; D^MPS=0, high probability encoding. The decision maker is used to decide whether to update the probability Qe value of the context dynamic probability table Qe, and whether to perform high probability encoding. Part of the output of the decision maker is sent to the previous level context probability update adaptive module, and the other part is sent to the current level module, which are used for the renormalization stage and processing all buffer 0xff byte overflows. Register B is used to temporarily store the high-order value of the new register C. Its output is simply spliced ​​to obtain the correct SCD.

[0104] The decision maker in the present invention plays a key decision-making and regulatory role throughout the encoding process.

[0105] The decision maker receives a series of data related to the pixel D to be encoded, including the most probable symbol MPS, the probability table Qe after being shifted left by one bit, etc. Its core function is to precisely compare and analyze these input data.

[0106] By performing arithmetic operations such as subtraction, the decision maker can determine the numerical relationship and degree of difference between the input data. Based on preset rules and logic, as well as interactions with the adaptive module, the decision maker makes key decisions.

[0107] For example, according to the comparison result of the probability Qe with other values, the decision maker decides whether to send the data to the adaptive module for further processing, or trigger other related operations, such as control instructions for the first register A, the first register C, etc.

[0108] At the same time, the decision maker continuously monitors the stability and rationality of the input data to ensure the accuracy and reliability of the encoding process.

[0109] In some embodiments, in step 3) above, the above-mentioned step S3-1: the processing flow of the adaptive decoding module includes: reading the first 8 bits of the context CX from the context CX register as an address, and decoding the pixel value corresponding to the 9th bit in the context CX; when decoding the last bit of the context CX, there are two index values Index0 and Index1, corresponding to two most probable symbols MPS0 and MPS1 respectively, and converting them into two probability tables Qe running in parallel.

[0110] The above two index values Index0 and Index1, the two most probable symbols MPS0 and MPS1, as well as the pixel SCD to be decoded and the decoding unit feedback signal jointly output a new index value Index and a new most probable symbol MPS through a multiplexer; the two probability tables Qe running in parallel, as well as the pixel SCD to be decoded and the decoding unit feedback signal jointly output a new probability table Qe through another multiplexer; at the same time, the first context CX register CX is updated.

[0111] In step 3) above, the above-mentioned step S3-2: the processing flow of the above-mentioned decoding unit includes: the pixel SCD to be decoded, the new most probable symbol MPS and the new probability table Qe are subjected to renormalization or arithmetic decoding.

[0112] The precisions of the second register C and the second register A in the above-mentioned decoding unit are 24 bits and 16 bits respectively, and the second register C is divided into Clow -2 and Chigh -2 two parts, and Clow-2 represents the lower 8 bits of the second register C, Chigh -2 represents the upper 16 bits of the second register C; and Clow -2 is only used to read the incoming compressed data stream and is shifted to the high position during renormalization;

[0113] In the above arithmetic decoding, the left shift of the above new probability table Qe realizes doubling, and the left shift of the second register A performs arithmetic and logical operations; an 8-bit shift is performed when initializing the second register C at the beginning of each strip, and only Chigh in the second register C -2 performs arithmetic and logical operations; finally, the original pixel D is restored.

[0114] In some other embodiments, such as Figure 3 shown, the processing flow of the adaptive decoding module of the decoder is the same as that of the adaptive arithmetic coding process. The difference is that the selector of the adaptive decoding module is a complex multiplexer, and the index value Index and the most probable symbol MPS are jointly selected through the feedback signal of the decoding unit and the pixel D to be decoded. The data in the context CX memory is stored in both data memory 1 and data memory 2 at the same time.

[0115] In some other embodiments, such as Figure 4 shown, the second register A in the decoding unit has the same 16-bit width as the first register A in the encoding module. The second register C only needs 24-bit width, and all arithmetic operations in the decoding unit are 16-bit arithmetic operations because the arithmetic operations on the second register C only involve the highest 16 bits of the second register C. The lower 8 bits of the second register C are only used to read the incoming compressed data stream and are shifted to the high position of the new second register C during renormalization.

[0116] In some other embodiments, during decoding, the adaptive decoding module performs reading context CX data by reading data from the context CX register using the first 8 bits of the context CX as an address. Meanwhile, the decoder decodes the pixel value corresponding to the 9th bit in the context CX. Once the value of the pixel is known, the number of possibilities in the context CX is reduced to two. The adaptive decoding module stores the upper 16 bits or the lower 16 bits of the context CX register data into an internal register, depending on whether the decoded bit is 1 or 0. During the stage of reading context CX data, when decoding the last bit of the context CX, the adapter converts the two stored indexes into a probability table Qe using two lookup tables running in parallel. Once the decoder decodes the pixel, the final values of the probability table Qe, Index, and the most probable symbol MPS are selected and stored into registers. The adaptive decoding module provides these values to the decoding unit for decoding the current pixel during the decoding stage. Similar to the encoder, the adaptive decoding module updates the context CX second register CX and the internal register when necessary.

[0117] In some embodiments, as Figure 4 shown, in the arithmetic decoding unit, the arithmetic operations and logical operations performed by the second register A and the second register C are as follows:

[0118] A temp = A - Qe (1)

[0119] A < 2 * Qe (4)

[0120] C high -A temp < 0 (7)

[0121] C high_temp = C high -A temp (6)

[0122] where A is the assignment of the second register A as described above, and C high is Chigh -2 .

[0123] In some embodiments, as Figure 4 shown, decompression is a reversible process of compression. Since it is binary image compression and its values have only two possibilities, 0 and 1, the restored pixel value is obtained by selecting the most probable symbol MPS of the process value and its non-value. The outputs of the decision maker are respectively used to select the restoration of the pixel and the selection output of the relevant register values during the processing of the value probability Qe of the probability table Qe and SCD in this stage module.

[0124] The decision maker receives input data from multiple modules, including the probability Qe value that has undergone specific processing (such as shifting left by one bit) and various numerical values from other relevant modules. Its core function is to precisely compare and comprehensively analyze these input data.

[0125] By performing arithmetic operations such as taking the difference, the decision maker can determine the numerical differences and relationships between different data. According to the preset rules and logic, the decision maker makes key decisions based on these comparison and operation results.

[0126] For example, if the probability Qe value meets specific conditions after taking the difference and comparison with a certain threshold, the decision maker will trigger a series of instructions to transfer the data to a specific module (such as the adaptive module), thereby adjusting the subsequent operation mode and parameters of the system.

[0127] In some other embodiments, when re-normalizing in combination with an inline 1-bit shifter, A is the assignment of the second register A, and the possible results of the new value of the second register A are:

[0128] A = A temp

[0129] A = A temp << 1

[0130] A = Qe << 1

[0131] A = A << 1

[0132] The high bit Chigh of the second register C -2 is assigned C high , Chigh -2 may have new values:

[0133] C high = C high << 1

[0134] C high = C high_temp << 1

[0135] C high = C high << 8

[0136] Since Clow -2 and Chigh -2 represent different parts of the second register C, when performing the left shift operation, the most significant bit in Clow -2 is shifted to Chigh -2The least significant bit. The 8-bit shift operation is only used when initializing the second register C at the beginning of each stripe. In addition to determining the appropriate selection for the new value assignment in the second register C and the second register A, the decision logic in the decoder also specifies the color of the target pixel and whether the data in the context CX memory is updated.

[0137] In some embodiments, the above-mentioned update of the index value Index and the output probability value Qe is implemented as follows: Based on the input old index value Index, NLPS-I lookup tables, NMPS-I lookup tables, NLPS-Qe lookup tables, and NMPS-Q lookup tables are combined and created;

[0138] Through the above NLPS-I lookup table and NMPS-I lookup table, a new index value Index is output;

[0139] Through the above NLPS-Qe lookup table and NMPS-Q lookup table, a 16-bit probability value Qe corresponding to the next low-probability symbol LPS and the next high-probability symbol MPS defined in the original table is output, and then the final probability value Qe is obtained by selecting through two multiplexers.

[0140] In some embodiments, the above-mentioned first context CX memory is configured to be 32 bits wide and 256 bits deep; data is read asynchronously or written synchronously into the above-mentioned first context CX memory.

[0141] In some embodiments, the context CX construction module allows the use of three-row and two-row templates to generate the context CX.

[0142] In some other embodiments, as Figure 5 shown, the JBIG arithmetic coding process in step 2) has four stages: reading RAM, reading ROM, arithmetic coding, and renormalization. The resources used in the first three stages do not conflict, and the operations can overlap. That is, while the engine is executing the code stage of pixel n, it can also simultaneously execute the ROM reading stage of pixel n + 1 and the RAM reading stage of pixel n + 2; if the context CX of consecutive pixels is the same, data dependency conflicts may occur because the processing of previous pixels may change the values of the index value Index and the high-probability symbol MPS used for processing subsequent pixels. Introducing a data forwarding mechanism between different stages solves this problem because the engine can replace the outdated data in the external memory with the updated data inside the engine.

[0143] In some other embodiments, Figure 6Shows a method of updating the index value Index and the probability Qe value, which effectively combines NLPS-I, NMPS-I, NLPS-Qe, and NMPS-Qe by creating four new tables. Taking the old index value I as the input, it outputs the probability Qe values corresponding to the next least probable symbol NLPS and the next most probable symbol NMPS defined in the original table. Then, the same logic used to select the new index value I can be used to select the final value of the probability Qe value. By using a larger area, the longer delay between the original input old index value I and the final output new probability value Qe and new index value I is eliminated. Each newly defined table returns a 16-bit probability Qe value, so its size is twice that of the original probability Qe value table. In addition, two additional multiplexers are required to select the final value of the probability Qe value.

[0144] In some embodiments, the NLPS-I lookup table, NMPS-I lookup table, NLPS-Qe lookup table, and NMPS-Qe lookup table are four groups of lookup tables obtained by combining the NLPS and ST columns, NMPS and ST columns, NLPS and LSZ columns, and NMPS and LSZ columns in the PET table of the standard ITU-T T.82.

[0145] In some embodiments, the CX construction unit supports the generation of contexts for three-line and two-line templates, and the reused contexts for encoding typical prediction pseudo-pixels in different templates are mapped to the same value, improving the flexibility and consistency of encoding.

[0146] In some embodiments, as Figure 7 shown, the bit assignment of context CX in the three-line and two-line templates in the context CX construction module, where the numbers in each template box identify the number of bits assigned in context CX; for the convenience of selecting the memory address when accessing the context CX memory, the two least significant bits in context CX are assigned to two pixels in the template immediately before the target pixel, and the second bit of context CX is assigned to the adaptive pixel.

[0147] In some embodiments, as Figure 8 shown, the adaptive pixel at the default position, but the assignment of the second bit in context CX follows the movement of the adaptive pixel in the template, and the difference between the two templates affects the minimum number of bits in context CX. When converting between the three-line and two-line templates, this unit only changes the assignment of bits 7 to 9 in context CX.

[0148] In some embodiments, as Figure 9 and Figure 10As shown, in the two templates, the reuse context CX for encoding typical prediction pseudo-pixels must be mapped to the same value 0011100101. The context CX construction module implements three buffers for storing pixels; these three buffers represent three rows in the three-row template and only store the active part of the image; since the full rows are not stored, most of the pixels in the image are read into the module multiple times; to minimize memory access, when using a two-row template, one of the buffers is inactive. When encoding a strip, the context CX construction module first reads 16 pixels of each row in the template into the buffer, and then, as the template moves over each pixel in the image, it moves the pixels through the buffer; additional pixels are read into the buffer as necessary. To simplify the design, the context CX construction module synchronizes all read requests. The reference row buffer is 19 and 21 bits long. The current row buffer is 22 bits long in the encoder and 128 bits long in the decoder. The current row buffer length in the decoder is necessary for the movement of adaptive pixels. In addition to serving as a template, the current row buffer in the decoder also serves as the output buffer of the engine. The context CX construction module writes data to memory after every 16 pixels are decoded. Two 16-bit counters track the current X and Y positions of the strip and are updated after processing each pixel in the strip.

[0149] In some embodiments, the above encoding unit uses a multiplexer to select the final assignments allocated to the above first register A and the above first register C.

[0150] In some embodiments, in the above arithmetic coding, in the carry-select adder, the 16-bit addition Clow + A temp determines the lower 16 bits of C temp and the select value Chigh or Chigh + 1 of the carry-select adder is used as the upper 12 bits of C temp

[0151] ​In some other embodiments, the context CX construction process under typical prediction enabling: The reused context for encoding typical prediction pseudo-pixels must be mapped to the same value 0011100101; The context CX construction module implements three buffers for storing pixels. These three buffers represent three rows in the three-row template and only store the active part of the image; Most pixels in the image are read into the module multiple times without storing the complete row; To minimize memory access, when using a two-row template, one of the buffers is inactive; When encoding a strip, the context CX construction module first reads 16 pixels of each row in the template into the buffer. Pixels are moved through the buffer. Additional pixels are read into the buffer when necessary; The unit synchronizes all read requests. The reference row buffer is 19 and 21 bits long, and the current row buffer in the encoder is 22 bits long and 128 bits long in the decoder; The current row buffer length in the decoder is necessary for the movement of adaptive pixels; In addition to acting as a template, the current row buffer in the decoder also acts as the output buffer of the engine; The context CX construction module writes data to the memory after every 16 pixels are decoded. Two 16-bit counters track the current X and Y positions of the strip and are updated after each pixel in the strip is processed. Specific Embodiment 2:

[0153] A JBIG arithmetic coding and decoding system of the present invention. The above system is a system based on the JBIG arithmetic coding and decoding method in the above Specific Embodiment 1. The above system includes: a context CX construction module, a QM encoder, and a decoder. The above QM encoder includes an adaptive coding module and a coding unit. The above decoder includes an adaptive decoding module and a decoding unit;

[0154] The above adaptive coding module is configured with a first context CX register, a first context CX memory, a first selector, and a second selector. The above coding unit is configured with a first register A and a first register C. The above adaptive decoding module is configured with a context CX register and two multiplexers. The above decoding unit is configured with a second register A and a second register C.

[0155] In some embodiments, the above context CX construction module is configured to: tell the above QM encoder to execute the INITENC process at the start of each strip; When INITENC is completed, the context CX construction module is ready to generate context CX and pixel D for the first pixel of the image and tell the above QM encoder to execute the ENCODE process; After encoding all the pixels in the stripe, the context CX construction module instructs the QM encoder to execute the FLUSH process; When the FLUSH process ends, the encoding of the strip is completed, and the compressed pixel SCD is obtained.

[0156] The present invention is described through the above specific embodiments and specific implementation manners. Those skilled in the art should understand that various transformations and equivalent substitutions can be made to the present invention without departing from the scope of the present invention. The parts not detailed in the specification of the present invention are well-known technologies to those skilled in the art. Additionally, various modifications can be made to the present invention for specific situations or circumstances without departing from the scope of the present utility model. Therefore, the present invention is not limited to the disclosed specific embodiments, but should include all embodiments falling within the scope of the claims of the present invention.

Claims

1. A JBIG arithmetic coding and decoding method, characterized in that: The method is implemented based on the architecture of a QM encoder and a decoder, wherein the QM encoder includes an adaptive encoding module and an encoding unit, and the decoder includes an adaptive decoding module and a decoding unit; The method comprises: step 1) generating context CX, step 2) JBIG arithmetic coding process and step 3) JBIG arithmetic decoding process; the step 2) is composed of step S2-1: processing flow of adaptive coding module and step S2-2: processing flow of coding unit, and the step 3) is composed of step S3-1 processing flow of adaptive decoding module and step S3-2 processing flow of decoding unit; The step 1) generates a context CX, including: a context CX construction module reads pixels in an image strip from a memory to generate a 12-bit context CX and a pixel to be encoded D; In the step 2), the step S2-1: adaptive coding module processing flow includes: After receiving the request for pixel encoding, the adaptive coding module reads the address from the context CX with a decimal value and stores it in the first context CX memory; then performs simplified reading to generate a 7-bit valid context CX, generates an index value Index with the decimal value corresponding to the valid context CX, and uses the index value Index as the write address to store the context CX, the valid context CX and the index value Index in the first context CX memory; The first selector reads the index value Index and the high-probability symbol MPS corresponding to the given context CX from the lookup table of the first context CX memory, and the first selector determines whether to update the index value Index according to the first determination rule, and then outputs the updated or unupdated new index value Index, and selects the new high-probability symbol MPS corresponding to the new index value Index, and outputs the new index value Index, the new high-probability symbol MPS and the probability table Qe; and then the second selector determines the index value Index, the high-probability symbol MPS and the probability table Qe to be fed back to the encoding unit for arithmetic encoding; The first determination rule is: determine whether the target pixel is a high-probability symbol; if the target pixel is a high-probability symbol, do not update the index value Index, and directly output the index value Index; if the target pixel is not a high-probability symbol, update the index value Index, and output a new index value Index; In the step 2), the step S2-1: encoding unit processing flow includes: The pixel D to be encoded, the high probability symbol MPS, the index value Index and the probability table Qe transmitted by the adaptive encoding module are arithmetic encoded; Secondly, it is determined whether the first register A and the first register C need to be renormalized. The probability table Qe assigns A to the first register A, and the A corresponds to the low probability symbol LPS; and when A=A<<1, the renormalization stage is executed; the renormalization stage doubles the values ​​of the first register C and the first register A until A is greater than 0x8000; Next, perform the arithmetic coding; the arithmetic coding includes: the probability table Qe is doubled by shifting left through a 1-bit shifter, and the first register A and the first register C perform arithmetic operations and logical operations, and then are updated into the first register A and the first register C; finally, after encoding all the pixels in the strip, the QM encoder executes the FLUSH process to output the compressed pixel SCD; The precisions of the first register C and the first register A are 28 bits and 16 bits respectively. The first register C is divided into two parts, Clow and Chigh, where Clow represents the lower 16 bits of the first register C, and Chigh represents the higher 12 bits of the first register C; At the end of the arithmetic coding for each strip, the flush of the first register C executed includes a CLEARBITS process that clears the trailing bits in the compressed data stream to zero. The CLEARBITS process is: calculate TEMP = (A - 1 + C) & 0xffff0000 = A - 1 + Clow, compare TEMP < C, and check the carry of the calculation; if the comparison TEMP < C is true, the carry is 0; if the comparison TEMP < C is false, the carry is 1 or Clow = 0; Where A is the assignment of the first register A and C is the assignment of the first register C.

2. The JBIG arithmetic coding and decoding method according to claim 1, characterized in that: In the arithmetic coding, the arithmetic operations and logical operations performed by the first register C and the first register A are as follows: TO temp =A-Qe (1) C temp =C+A temp (2) A temp <Yes (3) A < 2 * Qe (4) Where A is the assignment of the first register A and C is the assignment of the first register C; the implementation of equation (4) takes precedence over equation (3), and the addition operation in equation (2) is implemented as a carry-select adder.

3. The JBIG arithmetic coding and decoding method according to any one of claims 1 to 2, characterized in that: In step 3), the process of the adaptive decoding module in step S3-1 includes: reading the first 8 bits of the context CX from the context CX register as an address, and decoding the pixel value corresponding to the 9th bit in the context CX; when decoding the last bit of the context CX, there are two index values, Index0 and Index1, corresponding to two most-probable symbols, MPS0 and MPS1 respectively, which are converted into two probability tables Qe running in parallel; The two index values Index0, Index1, the two most-probable symbols MPS0, MPS1, the pixel SCD to be decoded, and the decoding unit feedback signal jointly output a new index value Index and a new most-probable symbol MPS through a multiplexer; the two probability tables Qe running in parallel, the pixel SCD to be decoded, and the decoding unit feedback signal jointly output a new probability table Qe through another multiplexer; at the same time, update the context CX of the context CX register; In step 3), the process of the decoding unit in step S3-2 includes: the pixel SCD to be decoded, the new most-probable symbol MPS, and the new probability table Qe are subjected to renormalization or arithmetic decoding; The precision of the second register C and the second register A in the decoding unit are 24 bits and 16 bits respectively. The second register C is divided into Clow -2 and Chigh -2 Two parts, and Clow -2 Indicates the lower 8 bits of the second register C, Chigh -2 Represents the upper 16 bits of the second register C; and Clow -2 Used only to read the incoming compressed data stream, shifting it to the high bit while doing the renormalization; In the arithmetic decoding, the new probability table Qe is shifted left to achieve doubling, and the second register A is shifted left to perform arithmetic and logical operations; when initializing the second register C at the beginning of each stripe, an 8-bit shift is performed, and only Chigh -2 Perform arithmetic and logical operations; finally, restore the original pixel D.

4. The JBIG arithmetic coding and decoding method according to claim 3, characterized in that: In the arithmetic decoding unit, the arithmetic operations and logical operations performed by the second register A and the second register C are as follows: TO temp =A-Qe (1) A < 2 * Qe (4) C high -A temp <0 (7) C high_temp =C high -A temp (6) Where A is the value assigned to the second register A, C high Chigh -2 .

5. The JBIG arithmetic coding and decoding method according to claim 4, characterized in that: The updating index value Index and the output probability value Qe are implemented as follows: Based on the input old index value Index, the NLPS-I lookup table, the NMPS-I lookup table, the NLPS-Qe lookup table and the NMPS-Q lookup table are combined and created; Output a new index value Index through the NLPS-I lookup table and the NMPS-I lookup table; Through the NLPS-Qe lookup table and the NMPS-Q lookup table, a 16-bit probability value Qe corresponding to the next low-probability symbol LPS and the next high-probability symbol MPS defined in the original table is output, and then the final probability value Qe is selected through two multiplexers.

6. The JBIG arithmetic coding and decoding method according to claim 5, characterized in that: The first context CX memory is configured to be 32 bits wide and 256 bits deep; data is read from the first context CX memory asynchronously or written into the first context CX memory synchronously.

7. The JBIG arithmetic coding and decoding method according to claim 6, characterized in that: The encoding unit uses a multiplexer to select the final assignments to the first register A and the first register C.

8. The JBIG arithmetic coding and decoding method according to claim 7, characterized in that: In the arithmetic coding, in the carry select adder, the 16-bit addition Clow+A temp Decision C temp The lower 16 bits of the carry select adder select value Chigh or Chigh+1 as C temp The upper 12 digits.

9. A JBIG arithmetic coding and decoding system, characterized in that The system is a system based on the JBIG arithmetic coding and decoding method according to any one of claims 1 to 8, the system comprising: a context CX construction module, a QM encoder, and a decoder, the QM encoder comprising an adaptive coding module and an encoding unit, the decoder comprising an adaptive decoding module and a decoding unit; The adaptive encoding module is configured with a first context CX register, a first context CX memory, a first selector, and a second selector; the encoding unit is configured with a first register A and a first register C; the adaptive decoding module is configured with a context CX register and 2 multiplexers; and the decoding unit is configured with a second register A and a second register C.

10. The JBIG arithmetic coding and decoding system according to claim 9, characterized in that: The context CX construction module is configured to: tell the QM encoder to perform the INITENC process at the beginning of each strip; when INITENC is completed, the context CX construction module prepares to generate the context CX and pixel D for the first pixel of the image, and tells the QM encoder to perform the ENCODE process; after encoding all pixels in the stripe, the context CX construction module instructs the QM encoder to perform the FLUSH process; when the FLUSH process ends, the encoding of the stripe is completed, and the compressed pixel SCD is obtained.

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