Grid driving circuit, abnormity positioning method, display panel, detection method and device

Abstract

The invention discloses a gate drive circuit and an abnormality positioning method thereof, a display panel and an abnormality detection method thereof, and a display device. The gate drive circuit comprises a plurality of shift register units and a first signal line, and the plurality of shift register units are connected in parallel through the first signal line; the plurality of shift register units are in cascade connection in sequence through the second signal line; the signal steering unit is connected in series on the first signal line between two adjacent shift register units; and / or the first signal line is connected in series with the second signal line between two adjacent shift register units; the signal steering unit can change a transmission path of a signal on a first signal line passing through the signal steering unit so as to prevent the signal on the first signal line from being transmitted to the next shift register unit; and / or, the signal steering unit can change the transmission path of the signal on the second signal line passing through the signal steering unit so as to prevent the signal on the second signal line from being transmitted to the next shift register unit.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and specifically relate to a gate drive circuit and an abnormality positioning method thereof, a display panel and an abnormality detection method thereof, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display screens have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, bright colors, high contrast, and fast response rate. Summary of the invention

[0003] In a first aspect, an embodiment of the present disclosure provides a gate driving circuit, comprising a plurality of shift register units,

[0004] a first signal line, the plurality of shift register units being connected in parallel via the first signal line;

[0005] a second signal line, through which the plurality of shift register units are sequentially connected in cascade;

[0006] a signal steering unit, connected in series to the first signal line between two adjacent shift register units; and / or connected in series to the second signal line between two adjacent shift register units;

[0007] The signal steering unit can change the transmission path of the signal on the first signal line passing through it, so as to prevent the signal on the first signal line from being transmitted to the next shift register unit;

[0008] And / or, the signal steering unit can change the transmission path of the signal on the second signal line passing through it, so as to prevent the signal on the second signal line from being transferred to the next shift register unit.

[0009] In some embodiments, the signal steering unit includes a first signal steering unit;

[0010] The first signal steering unit includes a first transistor and a second transistor,

[0011] The gate of the first transistor and the gate of the second transistor are connected to the first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line;

[0012] The second electrode of the first transistor is connected to the first signal line; the second electrode of the second transistor is connected to the first test end.

[0013] In some embodiments, the signal steering unit further includes a second signal steering unit;

[0014] The second signal steering unit includes a third transistor and a fourth transistor,

[0015] The gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal; the first electrode of the third transistor and the first electrode of the fourth transistor are connected to the second signal line;

[0016] The second electrode of the third transistor is connected to the second signal line; the second electrode of the fourth transistor is connected to the second test end.

[0017] In some embodiments, the first transistor and the third transistor are P-type transistors or N-type transistors;

[0018] The second transistor and the fourth transistor are N-type transistors or P-type transistors.

[0019] In some embodiments, the plurality of shift register units are arranged sequentially along a first direction.

[0020] The first signal steering unit is located between two adjacent shift register units at middle positions along the first direction;

[0021] And / or, the second signal steering unit is located between two adjacent shift register units at middle positions along the first direction.

[0022] In some embodiments, the first signal line includes a clock signal line, a reset signal line, and a power line;

[0023] The second signal line includes a cascade signal line.

[0024] In some embodiments, the number of the first signal steering units is multiple, and the number of the second signal steering units is multiple;

[0025] There are a plurality of first signal lines and a plurality of second signal lines;

[0026] Different first signal lines are connected to different first signal steering units;

[0027] Different second signal lines are connected to different second signal steering units.

[0028] In some embodiments, at least part of the first signal steering unit and / or at least part of the second signal steering unit is located between different shift register units.

[0029] In a second aspect, an embodiment of the present disclosure further provides a display panel, which includes the above-mentioned gate driving circuit.

[0030] In some embodiments, there is a display area and a frame area, and the frame area surrounds the periphery of the display area;

[0031] The display panel further includes a plurality of pixel units, which are located in the display area and arranged in an array;

[0032] The gate drive circuit includes a first part;

[0033] The first part includes a plurality of shift register units, and the plurality of shift register units are sequentially connected in cascade;

[0034] The first portion is located in a first side frame area outside the display area,

[0035] One of the shift register units in the first part is connected to at least one row of the pixel units; and / or one of the shift register units in the first part is connected to at least some of the pixel units in one row.

[0036] In some embodiments, the gate drive circuit further includes a second part;

[0037] The second part includes a plurality of the shift register units, and the plurality of the shift register units are connected in cascade in sequence;

[0038] The second portion is located in a second side frame area outside the display area, and the second side frame area is opposite to the first side frame area;

[0039] One of the shift register units in the second part is connected to at least one row of the pixel units; and / or one of the shift register units in the second part is connected to at least some of the pixel units in one row.

[0040] In some embodiments, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit.

[0041] The first gate driving circuit is used to provide a gate control cascade signal to the pixel unit;

[0042] The second gate driving circuit is used to provide a light emitting control cascade signal to the pixel unit.

[0043] In some embodiments, a timing control circuit and a flexible printed circuit are also included;

[0044] The first signal steering unit in the gate driving circuit is connected to the timing control circuit via a first control terminal;

[0045] A first signal steering unit in the gate driving circuit is connected to the flexible printed circuit via a first test terminal;

[0046] The second signal steering unit in the gate driving circuit is connected to the timing control circuit via a second control terminal;

[0047] The second signal steering unit in the gate driving circuit is connected to the flexible printed circuit via a second test terminal.

[0048] In a third aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel.

[0049] In a fourth aspect, an embodiment of the present disclosure further provides a method for locating an abnormality of a gate driving circuit, wherein the gate driving circuit comprises a plurality of shift register units,

[0050] a first signal line, the plurality of shift register units being connected in parallel via the first signal line;

[0051] a second signal line, through which the plurality of shift register units are sequentially connected in cascade;

[0052] a signal steering unit, connected in series to the first signal line between two adjacent shift register units; and / or connected in series to the second signal line between two adjacent shift register units;

[0053] The abnormality positioning method comprises:

[0054] Controlling the signal steering unit to change the transmission path of the signal on the first signal line to prevent the signal on the first signal line from being transmitted to the next shift register unit, and a signal abnormality occurs on the first signal line;

[0055] And / or, the signal steering unit is controlled to change the transmission path of the signal on the second signal line to prevent the signal on the second signal line from being transmitted to the next shift register unit, and a signal abnormality occurs on the second signal line.

[0056] In some embodiments, the signal steering unit includes a first signal steering unit;

[0057] The first signal steering unit includes a first transistor and a second transistor,

[0058] The gate of the first transistor and the gate of the second transistor are connected to the first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line;

[0059] The second electrode of the first transistor is connected to the first signal line; the second electrode of the second transistor is connected to the first test terminal;

[0060] The abnormality locating method includes: the first control end controls the first transistor to be turned off and controls the second transistor to be turned on, the first signal line is broken, and the signal on the first signal line is transmitted to the first test end through the second transistor.

[0061] In some embodiments, the signal steering unit further includes a second signal steering unit;

[0062] The second signal steering unit includes a third transistor and a fourth transistor,

[0063] The gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal; the first electrode of the third transistor and the first electrode of the fourth transistor are connected to the second signal line;

[0064] The second electrode of the third transistor is connected to the second signal line; the second electrode of the fourth transistor is connected to the second test terminal;

[0065] The abnormality locating method further includes: the second control end controls the third transistor to be turned off and controls the fourth transistor to be turned on, the second signal line is broken, and the signal on the second signal line is transmitted to the second test end through the fourth transistor.

[0066] In a fifth aspect, an embodiment of the present disclosure further provides a method for detecting an abnormality of a display panel, wherein the display panel includes the above-mentioned gate driving circuit; the abnormality detection method includes:

[0067] Controlling a signal steering unit in the gate driving circuit to change a transmission path of a signal on a first signal line, so that the first signal line is disconnected and a first abnormality occurs on the display panel;

[0068] Comparing the first abnormality with the abnormal state of the fault display panel to determine whether the first abnormality is consistent with the abnormal state of the fault display panel;

[0069] If yes, it is determined that the first signal line of the fault display panel is abnormal; if no, it is determined that the first signal line of the fault display panel is normal;

[0070] and / or, controlling a signal steering unit in the gate driving circuit to change a transmission path of a signal on a second signal line, so that the second signal line is disconnected and a second abnormality occurs on the display panel;

[0071] Comparing the second abnormality with the abnormal state of the fault display panel to determine whether the second abnormality is consistent with the abnormal state of the fault display panel;

[0072] If yes, it is determined that the second signal line of the fault display panel is abnormal; if no, it is determined that the second signal line of the fault display panel is normal.

[0073] In some embodiments, there are a plurality of first signal lines and a plurality of second signal lines;

[0074] Different first signal lines and different second signal lines are respectively connected to different signal steering units;

[0075] The abnormality detection method includes: performing abnormality detection on the first signal line and the second signal line one by one.

[0076] In some embodiments, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit.

[0077] The first gate driving circuit provides a gate control cascade signal to the pixel unit;

[0078] The second gate driving circuit provides a light emitting control cascade signal to the pixel unit;

[0079] The abnormality detection method comprises: performing abnormality detection on the first signal line and the second signal line in the first gate driving circuit one by one;

[0080] The first signal line and the second signal line in the second gate driving circuit are detected for abnormality one by one.

[0081] The gate drive circuit provided in the embodiment of the present disclosure, by setting a signal steering unit, can accurately locate the abnormal signal on the first signal line and / or the second signal line when a short circuit occurs in the first signal line and / or the second signal line, thereby being able to actively reproduce the poor display caused by the abnormal signal, thereby being able to help analysts quickly locate the abnormal signal and improve the efficiency of analyzing the poor display caused by the abnormal signal.

[0082] The display panel provided by the embodiment of the present disclosure adopts the gate driving circuit in the above embodiment. When the signal steering unit in the gate driving circuit causes the first signal line and / or the second signal line to be broken, the abnormal signal on the first signal line and / or the second signal line can be accurately located, so that the poor display caused by the abnormal signal can be actively reproduced, and further, it can help analysts to quickly locate the abnormal signal and improve the analysis efficiency of the poor display caused by the abnormal signal.

[0083] The display device provided in the embodiment of the present disclosure improves the analysis efficiency of display defects of the display device by adopting the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0085] Figure 1a A circuit diagram of a pixel circuit in the related art.

[0086] Figure 1b The present invention is a circuit diagram of a light emitting control gate driving circuit in the related art.

[0087] Figure 1c The figure is a circuit connection diagram of a gate driving circuit in a display panel in the related art.

[0088] Figure 2a The diagram is a circuit connection diagram of a gate driving circuit in an embodiment of the present disclosure.

[0089] Figure 2b Schematic diagram of circuit connection of another gate driving circuit in an embodiment of the present disclosure.

[0090] Figure 2c The figure is a circuit connection diagram of another gate driving circuit in the embodiment of the present disclosure.

[0091] Figure 2d The diagram is a circuit connection diagram of yet another gate driving circuit in an embodiment of the present disclosure.

[0092] Figure 3a 4 is a circuit diagram of the first signal steering unit in the embodiment of the present disclosure.

[0093] Figure 3b 4 is a circuit diagram of the second signal steering unit in the embodiment of the present disclosure.

[0094] Figure 3c The diagram is a circuit connection diagram of yet another gate driving circuit in an embodiment of the present disclosure.

[0095] Figure 4a It is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0096] Figure 4b FIG. 4 is a schematic diagram of another display panel in an embodiment of the present disclosure.

[0097] Figure 4cFIG. 4 is a schematic diagram of another display panel in an embodiment of the present disclosure.

[0098] Figure 4d FIG. 4 is a schematic diagram of another display panel in an embodiment of the present disclosure.

[0099] Figure 4e FIG. 4 is a schematic diagram of another display panel in an embodiment of the present disclosure.

[0100] Figure 5a The present invention is a flowchart of a method for detecting an abnormality of a first signal line in a display panel according to an embodiment of the present invention.

[0101] Figure 5b The present invention is a flow chart of a method for detecting an abnormality of a second signal line in a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION

[0102] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a gate drive circuit and its abnormality positioning method, a display panel and its abnormality detection method, and a display device provided by the embodiments of the present disclosure are further described in detail below in combination with the accompanying drawings and specific implementation methods.

[0103] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0104] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be limiting.

[0105] In the related art, refer to Figure 1a and Figure 1b , the display panel (such as OLED display panel) includes a gate drive circuit, which provides two necessary drive signals for the pixel circuit, namely the Gate signal (gate control signal) and the Emission signal (light-emitting control signal). The Gate signal is used to drive the pixel circuit in the data writing stage, and the Emission signal is used to drive the pixel circuit in the light-emitting stage; whether the display panel can display normally is closely related to these two signals. When they are abnormal, the display panel will show Y lines (horizontal bright lines), split screen (color or brightness of the upper and lower screen areas are inconsistent), no display (the whole screen is black) and other undesirable phenomena.

[0106] The Gate signal and the Emission signal are generated by two different gate drive circuits. For the gate drive circuit that generates the Gate signal, its input signals include GSTV (gate control cascade signal), GCK (first clock signal), and GCB (second clock signal), and these input signals work together to make the gate drive circuit generate the Gate signal; and for the gate drive circuit that generates the Emission signal, its input signals include ESTV (light emission control cascade signal), ECK (third clock signal), and ECB (fourth clock signal), and these input signals work together to make the gate drive circuit generate the Emission signal. Figure 1c The positions of these input signals in the gate drive circuit are shown in FIG. Since the macroscopic structures of the gate drive circuits generating the Gate signal and the Emission signal are similar (i.e., they are both composed of a plurality of cascaded shift register units), in order to simplify the display, Figure 1c In the text, GSTV and ESTV are collectively referred to as STV signals; GCK and ECK are collectively referred to as CK signals; GCB and ECB are collectively referred to as CB signals.

[0107] During the display panel display process, electrochemical corrosion, cracking and other factors may cause any input signal of the gate drive circuit to be abnormal, thereby affecting the gate signal and emission signal provided by the gate drive circuit, thereby causing poor display. Figure 1c The gate drive circuit includes a plurality of shift register units (gate drive 0 to gate drive n, i.e., GOA0 to GOAn or EOA0 to EOAn) 1, and the plurality of shift register units 1 are connected in a cascade manner to transmit the Gate signal or the Emission signal downward line by line; however, when the Gate signal and the Emission signal are abnormal, it is not possible to accurately determine which input signal line (GSTV, GCK, GCB, ESTV, ECK, ECB) is the cause of the abnormality. In the analysis process of such display defects, each input signal line is currently checked step by step through a microscope, and some tiny abnormal points on the input signal line may be ignored under long-term observation. In addition, when reproducing such display defects, it is necessary to use a laser device to accurately hit the corresponding input signal line to disconnect the corresponding input signal line, so as to reproduce the display defects caused by the disconnection of the corresponding input signal line. If the laser device deviates to other signal lines, the reproduced screen with poor display will be directly scrapped. This display defect reproduction operation has extremely high requirements for the analysis personnel and will incur a lot of time costs.

[0108] How to accurately locate abnormal input signals in gate drive circuits has become a problem that needs to be solved urgently.

[0109] In order to solve the problems in the related art, in a first aspect, an embodiment of the present disclosure provides a gate driving circuit, referring to Figure 2a , Figure 2b , Figure 2c and Figure 2d , which includes a plurality of shift register units 1, a first signal line 2, wherein the plurality of shift register units 1 are connected in parallel via the first signal line 2; a second signal line 3, wherein the plurality of shift register units 1 are connected in cascade in sequence via the second signal line 3; a signal steering unit 4, which is connected in series on the first signal line 2 between two adjacent shift register units 1; and / or, which is connected in series on the second signal line 3 between two adjacent shift register units 1; the signal steering unit 4 can change the transmission path of the signal on the first signal line 2 passing through it to prevent the signal on the first signal line 2 from being transmitted to the next shift register unit 1; and / or, the signal steering unit 4 can change the transmission path of the signal on the second signal line 3 passing through it to prevent the signal on the second signal line 3 from being transmitted to the next shift register unit 1.

[0110] The first signal line 2 refers to any signal line in the gate drive circuit through which multiple shift register units 1 can be connected in parallel, such as a clock signal line, a reset signal line, a power line, etc. The second signal line 3 refers to any signal line in the gate drive circuit through which multiple shift register units 1 can be connected in cascade in sequence, such as a gate control cascade signal line, a light emitting control cascade signal line, etc.

[0111] In this embodiment, Figure 2a and Figure 2b The diagram shows a first signal line (GCK, GCB) 2 and a second signal line (GSTV) 3 in a gate driving circuit for generating a Gate signal; the gate driving circuit for generating a Gate signal includes a plurality of shift register units (GOA0-GOAn) 1. Figure 2c and Figure 2d The diagram shows a first signal line (ECK, ECB) 2 and a second signal line (ESTV) 3 in a gate driving circuit for generating an Emission signal; the gate driving circuit for generating an Emission signal includes a plurality of shift register units (EOA0-EOAn) 1.

[0112] In this embodiment, when the signal steering unit 4 changes the transmission path of the signal on the first signal line 2 passing through it, it can prevent the signal on the first signal line 2 from being transmitted to the next shift register unit 1, and then the first signal line 2 can be broken, and then the display panel including the gate drive circuit can have a poor display when the first signal line 2 is broken; similarly, when the signal steering unit 4 changes the transmission path of the signal on the second signal line 3 passing through it, it can prevent the signal on the second signal line 3 from being transmitted to the next shift register unit 1, and then the second signal line 3 can be broken, and then the display panel including the gate drive circuit can have a poor display when the second signal line 3 is broken; in summary, the setting of the signal steering unit 4 can enable the display panel including the gate drive circuit to reproduce the poor display when the first signal line 2 and / or the second signal line 3 are broken.

[0113] In this embodiment, by setting up a signal steering unit 4, when the first signal line 2 and / or the second signal line 3 is broken, the abnormal signal on the first signal line 2 and / or the second signal line 3 can be accurately located, so that the poor display caused by the abnormal signal can be actively reproduced, which can help analysts quickly locate the abnormal signal and improve the analysis efficiency of the poor display caused by the abnormal signal.

[0114] In some embodiments, reference Figure 3a The signal steering unit 4 includes a first signal steering unit 41; the first signal steering unit 41 includes a first transistor Ta and a second transistor Tb, the gate of the first transistor Ta and the gate of the second transistor Tb are connected to the first control terminal A; the first electrode of the first transistor Ta and the first electrode of the second transistor Tb are connected to the first signal line 2; the second electrode of the first transistor Ta is connected to the first signal line 2; the second electrode of the second transistor Tb is connected to the first test terminal B.

[0115] In some embodiments, the first transistor Ta is a P-type transistor or an N-type transistor; the second transistor Tb is an N-type transistor or a P-type transistor.

[0116] In some embodiments, the first transistor Ta is a P-type transistor; the second transistor Tb is an N-type transistor. When the first control terminal A provides a low-level signal through path ①, the first transistor Ta is turned on, the second transistor Tb is turned off, the transmission path of the signal on the first signal line 2 remains unchanged, and is transmitted along the path ④→②, that is, the signal on the first signal line 2 is still transmitted to the next shift register unit 1 through the first signal line 2; when the first control terminal A provides a high-level signal through path ①, the second transistor Tb is turned on, the first transistor Ta is turned off, the transmission path of the signal on the first signal line 2 is changed, and is transmitted along the path ④→③, that is, the signal on the first signal line 2 is directly transmitted to the first test terminal B through path ③. At the first test terminal B, the output signal of the first test terminal B can be tested by a detection device to determine whether the first signal steering unit 41 has changed the transmission path of the signal on the first signal line 2.

[0117] In some embodiments, reference Figure 3b , the signal steering unit 4 also includes a second signal steering unit 42; the second signal steering unit 42 includes a third transistor Tc and a fourth transistor Td, the gate of the third transistor Tc and the gate of the fourth transistor Td are connected to the second control terminal C; the first electrode of the third transistor Tc and the first electrode of the fourth transistor Td are connected to the second signal line 3; the second electrode of the third transistor Tc is connected to the second signal line 3; the second electrode of the fourth transistor Td is connected to the second test terminal D.

[0118] In some embodiments, the third transistor Tc is a P-type transistor or an N-type transistor; the fourth transistor Td is an N-type transistor or a P-type transistor.

[0119] In some embodiments, the third transistor Tc is a P-type transistor; the fourth transistor Td is an N-type transistor. When the second control terminal C provides a low-level signal through path ①, the third transistor Tc is turned on, the fourth transistor Td is turned off, the transmission path of the signal on the second signal line 3 remains unchanged, and is transmitted along the path ④→②, that is, the signal on the second signal line 3 is still transmitted to the next shift register unit 1 through the second signal line 3; when the second control terminal C provides a high-level signal through path ①, the fourth transistor Td is turned on, the third transistor Tc is turned off, the transmission path of the signal on the second signal line 3 is changed, and is transmitted along the path ④→③, that is, the signal on the second signal line 3 is directly transmitted to the second test terminal D through path ③. At the second test terminal D, the output signal of the second test terminal D can be tested by a detection device to determine whether the second signal steering unit 42 has changed the transmission path of the signal on the second signal line 3.

[0120] In some embodiments, multiple shift register units 1 are arranged in sequence along the first direction Z, and the first signal steering unit 41 is located between two adjacent shift register units 1 at the middle position along the first direction Z; and / or, the second signal steering unit 42 is located between two adjacent shift register units 1 at the middle position along the first direction Z.

[0121] Such a configuration can make the poor display caused by the short circuit of the first signal line 2 reproduce in the middle area of ​​the display area of ​​the display panel, thereby facilitating better observation, comparison and analysis of the poor display; similarly, the poor display caused by the short circuit of the second signal line 3 can be reproduced in the middle area of ​​the display area of ​​the display panel, thereby facilitating better observation, comparison and analysis of the poor display.

[0122] In some embodiments, reference Figure 3c The first signal line 2 includes a clock signal line (such as GCK, GCB, ECK, ECB), a reset signal line (such as Reset) and a power line (such as VGH, VGL); the second signal line 3 includes a cascade signal line (such as GSTV, ESTV).

[0123] In some embodiments, there are multiple first signal steering units 41, multiple second signal steering units 42; there are multiple first signal lines 2, multiple second signal lines 3; different first signal lines 2 are connected to different first signal steering units 41; different second signal lines 3 are connected to different second signal steering units 42. Such a configuration facilitates the positioning of abnormal signals of multiple first signal lines 2 and multiple second signal lines 3 one by one, so that the display defects caused by abnormal signals of different first signal lines 2 and different second signal lines 3 can be reproduced one by one, thereby helping analysts to quickly locate the abnormal signals and improve the analysis efficiency of the display defects caused by the abnormal signals.

[0124] In some embodiments, at least part of the first signal steering units 41 and / or at least part of the second signal steering units 42 are located between different shift register units 1. This arrangement avoids arranging multiple first signal steering units 41 and / or multiple second signal steering units 42 between the same group of adjacent shift register units 1, thereby avoiding the situation where the space between the same group of adjacent shift register units 1 is insufficient and it is difficult to accommodate multiple signal steering units 4.

[0125] Based on the above structure of the gate drive circuit, an embodiment of the present disclosure also provides a method for locating an abnormality of the gate drive circuit, including: controlling a signal steering unit to change a transmission path of a signal on a first signal line, preventing the signal on the first signal line from being transmitted to a next shift register unit, and causing a signal abnormality on the first signal line; and / or controlling a signal steering unit to change a transmission path of a signal on a second signal line, preventing the signal on the second signal line from being transmitted to a next shift register unit, and causing a signal abnormality on the second signal line.

[0126] In some embodiments, the abnormality locating method includes: the first control end controls the first transistor to be turned off and the second transistor to be turned on, the first signal line is broken, and the signal on the first signal line is transmitted to the first test end through the second transistor.

[0127] In some embodiments, the abnormality locating method further includes: the second control terminal controls the third transistor to be turned off, and controls the fourth transistor to be turned on, the second signal line is broken, and the signal on the second signal line is transmitted to the second test terminal through the fourth transistor.

[0128] The gate drive circuit provided in the embodiment of the present disclosure, by setting a signal steering unit, can accurately locate the abnormal signal on the first signal line and / or the second signal line when a short circuit occurs in the first signal line and / or the second signal line, thereby being able to actively reproduce the poor display caused by the abnormal signal, thereby being able to help analysts quickly locate the abnormal signal and improve the efficiency of analyzing the poor display caused by the abnormal signal.

[0129] In a second aspect, an embodiment of the present disclosure further provides a display panel, comprising the gate driving circuit in the above embodiment.

[0130] By adopting the gate drive circuit in the above-mentioned embodiment, when the signal steering unit in the gate drive circuit causes the first signal line and / or the second signal line to be broken, the abnormal signal on the first signal line and / or the second signal line can be accurately located, so that the poor display caused by the abnormal signal can be actively reproduced, thereby helping analysts to quickly locate the abnormal signal and improve the analysis efficiency of the poor display caused by the abnormal signal.

[0131] In some embodiments, reference Figure 4a , Figure 4b , Figure 4c , Figure 4d and Figure 4eThe display panel has a display area 100 and a frame area 101, and the frame area 101 surrounds the periphery of the display area 100; the display panel also includes a plurality of pixel units 10, which are located in the display area 100 and arranged in an array; the gate driving circuit includes a first part 51; the first part 51 includes a plurality of shift register units 1, and the plurality of shift register units 1 are cascaded in sequence; the first part 51 is located in a first side frame area 101A outside the display area 100, and one shift register unit 1 in the first part 51 is connected to at least one row of pixel units 10; and / or, one shift register unit 1 in the first part 51 is connected to at least part of the pixel units 10 in a row.

[0132] In some embodiments, a shift register unit 1 in the first part 51 can correspond to connecting a row of pixel units 10, or can correspond to connecting multiple rows (such as 2 rows or 4 rows) of pixel units 10; a shift register unit 1 in the first part 51 can correspond to connecting all pixel units 10 in a row, or can correspond to connecting part of the pixel units 10 in a row, such as a shift register unit 1 in the first part 51 corresponds to connecting an odd number of pixel units 10 or an even number of pixel units 10 in a row; or, a shift register unit 1 in the first part 51 corresponds to connecting 1 / 2 of the pixel units 10 arranged sequentially in a row.

[0133] In some embodiments, if only the first part 51 is provided in the gate driving circuit, the connection mode between the first part 51 and the pixel unit 10 corresponds to the mode in which the gate driving circuit performs unilateral driving on the pixel unit array.

[0134] In some embodiments, the gate drive circuit also includes a second part 52; the second part 52 includes multiple shift register units 1, and the multiple shift register units 1 are cascaded in sequence; the second part 52 is located in the second side frame area 101B outside the display area 100, and the second side frame area 101B is opposite to the first side frame area 101A; one shift register unit 1 in the second part 52 is at least connected to a row of pixel units 10; and / or, one shift register unit 1 in the second part 52 is at least connected to part of the pixel units 10 in a row.

[0135] In some embodiments, a shift register unit 1 in the second part 52 can correspond to connecting a row of pixel units 10, or can correspond to connecting multiple rows (such as 2 rows or 4 rows) of pixel units 10; a shift register unit 1 in the second part 52 can correspond to connecting all pixel units 10 in a row, or can correspond to connecting part of the pixel units 10 in a row, such as a shift register unit 1 in the second part 52 corresponds to connecting an odd number of pixel units 10 or an even number of pixel units 10 in a row; or, a shift register unit 1 in the second part 52 corresponds to connecting 1 / 2 of the number of pixel units 10 arranged sequentially in a row.

[0136] In some embodiments, when the gate driving circuit includes the first part 51 and the second part 52, the connection mode of the first part 51, the second part 52 and the pixel unit 10 corresponds to the mode in which the gate driving circuit performs bilateral driving on the pixel unit array.

[0137] In some embodiments, the gate driving circuit includes a first gate driving circuit 8 and a second gate driving circuit 9, wherein the first gate driving circuit 8 is used to provide a gate control cascade signal (Gate) to the pixel unit 10; and the second gate driving circuit 9 is used to provide a light emitting control cascade signal (EM) to the pixel unit 10.

[0138] In some embodiments, reference Figure 1a , the pixel unit includes a pixel circuit and a light emitting element D', Figure 1a The pixel circuit is a 7T1C (7 thin film transistors and 1 capacitor) circuit, and the light emitting element D' can be an OLED element (organic electroluminescent element). The GLn signal (gate control cascade signal) and the GLn-1 signal (gate control cascade signal) in the pixel circuit are provided by the nth shift register unit and the n-1th shift register unit in the first gate driving circuit, respectively, and the GLn signal and the GLn-1 signal are used to drive the pixel circuit in the data writing stage; the EM signal (luminescence control cascade signal) in the pixel circuit is provided by the shift register unit in the second gate driving circuit, and the EM signal is used to drive the pixel circuit in the luminescence stage.

[0139] In some embodiments, reference Figure 4b-4e The display panel also includes a timing control circuit 6 and a flexible printed circuit 7; the first signal steering unit 41 in the gate driving circuit is connected to the timing control circuit 6 through the first control terminal A; the first signal steering unit 41 in the gate driving circuit is connected to the flexible printed circuit 7 through the first test terminal B; the second signal steering unit 42 in the gate driving circuit is connected to the timing control circuit 6 through the second control terminal C; the second signal steering unit 42 in the gate driving circuit is connected to the flexible printed circuit 7 through the second test terminal D.

[0140] The first control terminal A and the second control terminal C can be arranged in the timing control circuit 6. When the first signal steering unit 41 and the second signal steering unit 42 are working, the timing control circuit 6 provides control signals thereto respectively through the first control terminal A and the second control terminal C. The first test terminal B and the second test terminal D can be arranged in the flexible printed circuit 7. When the first signal steering unit 41 and the second signal steering unit 42 are working, the flexible printed circuit 7 receives signals on the first signal line 2 and the second signal line 3 respectively through the first test terminal B and the second test terminal D.

[0141] Based on the above structure of the display panel, the present disclosure also provides a method for detecting an abnormality of the display panel. Figure 5a and Figure 5b , including: step S101: controlling the signal steering unit in the gate driving circuit to change the transmission path of the signal on the first signal line, so that the first signal line is broken and the display panel has a first abnormality.

[0142] Step S102: Compare the abnormal state of the first abnormality and the abnormal state of the fault display panel to determine whether the abnormal state of the first abnormality and the abnormal state of the fault display panel are consistent.

[0143] If yes, then execute step S103: determine whether the first signal line of the faulty display panel is abnormal; if no, then execute step S104: determine whether the first signal line of the faulty display panel is normal.

[0144] And / or, step S201: controlling the signal steering unit in the gate driving circuit to change the transmission path of the signal on the second signal line, so that the second signal line is broken and a second abnormality occurs on the display panel.

[0145] Step S202: Compare the abnormal state of the second abnormality and the abnormal state of the fault display panel to determine whether the abnormal state of the second abnormality and the abnormal state of the fault display panel are consistent.

[0146] If yes, then execute step S203: determine whether the second signal line of the faulty display panel is abnormal; if no, then execute step S204: determine whether the second signal line of the faulty display panel is normal.

[0147] In some embodiments, there are multiple first signal lines and multiple second signal lines; different first signal lines and different second signal lines are connected to different signal steering units respectively; the abnormality detection method includes: performing abnormality detection on the first signal line and the second signal line one by one. Thus, the abnormality detection can be performed on multiple first signal lines and multiple second signal lines separately, and the abnormal signal line can be located more accurately.

[0148] In some embodiments, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit, the first gate driving circuit provides a gate control cascade signal to the pixel unit; the second gate driving circuit provides a light emitting control cascade signal to the pixel unit; the abnormality detection method includes: performing abnormality detection on the first signal line and the second signal line in the first gate driving circuit one by one; performing abnormality detection on the first signal line and the second signal line in the second gate driving circuit one by one.

[0149] The display panel provided by the embodiment of the present disclosure adopts the above-mentioned gate driving circuit. When the signal steering unit in the gate driving circuit causes the first signal line and / or the second signal line to be broken, the abnormal signal on the first signal line and / or the second signal line can be accurately located, so that the poor display caused by the abnormal signal can be actively reproduced, and further, it can help analysts to quickly locate the abnormal signal and improve the analysis efficiency of the poor display caused by the abnormal signal.

[0150] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel in the above embodiment.

[0151] By adopting the display panel in the above embodiment, the analysis efficiency of poor display of the display device is improved.

[0152] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, a navigator, or the like.

[0153] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A gate drive circuit, wherein: comprising a plurality of shift register units, a first signal line, the plurality of shift register units being connected in parallel via the first signal line; a second signal line, through which the plurality of shift register units are sequentially connected in cascade; a signal steering unit, connected in series to the first signal line between two adjacent shift register units; and / or connected in series to the second signal line between two adjacent shift register units; The signal steering unit can change the transmission path of the signal on the first signal line passing through it, so as to prevent the signal on the first signal line from being transmitted to the next shift register unit; And / or, the signal steering unit can change the transmission path of the signal on the second signal line passing through it, so as to prevent the signal on the second signal line from being transferred to the next shift register unit.

2. The gate drive circuit according to claim 1, wherein: The signal steering unit comprises a first signal steering unit; The first signal steering unit includes a first transistor and a second transistor, The gate of the first transistor and the gate of the second transistor are connected to the first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line; The second electrode of the first transistor is connected to the first signal line; the second electrode of the second transistor is connected to the first test end.

3. The gate driving circuit according to claim 2, wherein: The signal steering unit further includes a second signal steering unit; The second signal steering unit includes a third transistor and a fourth transistor, The gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal; the first electrode of the third transistor and the first electrode of the fourth transistor are connected to the second signal line; The second electrode of the third transistor is connected to the second signal line; the second electrode of the fourth transistor is connected to the second test end.

4. The gate driving circuit according to claim 3, wherein: The first transistor and the third transistor are P-type transistors or N-type transistors; The second transistor and the fourth transistor are N-type transistors or P-type transistors.

5. The gate driving circuit according to claim 3, wherein: The plurality of shift register units are arranged in sequence along a first direction, The first signal steering unit is located between two adjacent shift register units at middle positions along the first direction; And / or, the second signal steering unit is located between two adjacent shift register units at middle positions along the first direction.

6. The gate driving circuit according to claim 3, wherein: The first signal line includes a clock signal line, a reset signal line and a power line; The second signal line includes a cascade signal line.

7. The gate driving circuit according to claim 3, wherein: The number of the first signal steering units is multiple, and the number of the second signal steering units is multiple; There are a plurality of first signal lines and a plurality of second signal lines; Different first signal lines are connected to different first signal steering units; Different second signal lines are connected to different second signal steering units.

8. The gate driving circuit according to claim 7, wherein: At least part of the first signal steering unit and / or at least part of the second signal steering unit is located between different shift register units.

9. A display panel, wherein: A gate drive circuit comprising any one of claims 1 to 8.

10. The display panel according to claim 9, wherein: It has a display area and a frame area, wherein the frame area surrounds the periphery of the display area; The display panel further includes a plurality of pixel units located in the display area and arranged in an array; The gate drive circuit includes a first part; The first part includes a plurality of shift register units, and the plurality of shift register units are sequentially connected in cascade; The first portion is located in a first side frame area outside the display area, One of the shift register units in the first part is connected to at least one row of the pixel units; and / or one of the shift register units in the first part is connected to at least some of the pixel units in one row.

11. The display panel according to claim 10, wherein: The gate drive circuit also includes a second part; The second part includes a plurality of the shift register units, and the plurality of the shift register units are connected in cascade in sequence; The second portion is located in a second side frame area outside the display area, and the second side frame area is opposite to the first side frame area; One of the shift register units in the second part is connected to at least one row of pixel units; And / or, one of the shift register units in the second part is connected to at least part of the pixel units in a row.

12. The display panel according to claim 11, wherein: The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit is used to provide a gate control cascade signal to the pixel unit; The second gate driving circuit is used to provide a light emitting control cascade signal to the pixel unit.

13. The display panel according to claim 9, wherein: Also included are timing control circuits and flexible printed circuits; The first signal steering unit in the gate driving circuit is connected to the timing control circuit via a first control terminal; A first signal steering unit in the gate driving circuit is connected to the flexible printed circuit via a first test terminal; The second signal steering unit in the gate driving circuit is connected to the timing control circuit via a second control terminal; The second signal steering unit in the gate driving circuit is connected to the flexible printed circuit via a second test terminal.

14. A display device, wherein: A display panel comprising any one of claims 9 to 13.

15. A method for locating an abnormality of a gate drive circuit, wherein: The gate driving circuit includes a plurality of shift register units. a first signal line, the plurality of shift register units being connected in parallel via the first signal line; a second signal line, through which the plurality of shift register units are sequentially connected in cascade; A signal steering unit connected in series to the first signal line between two adjacent shift register units; and / or, connected in series on the second signal line between two adjacent shift register units; The abnormality positioning method comprises: Controlling the signal steering unit to change the transmission path of the signal on the first signal line to prevent the signal on the first signal line from being transmitted to the next shift register unit, and a signal abnormality occurs on the first signal line; And / or, the signal steering unit is controlled to change the transmission path of the signal on the second signal line to prevent the signal on the second signal line from being transmitted to the next shift register unit, and a signal abnormality occurs on the second signal line.

16. The abnormality locating method according to claim 15, wherein: The signal steering unit comprises a first signal steering unit; The first signal steering unit includes a first transistor and a second transistor, The gate of the first transistor and the gate of the second transistor are connected to the first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line; The second electrode of the first transistor is connected to the first signal line; The second electrode of the second transistor is connected to the first test terminal; The abnormality locating method includes: the first control end controls the first transistor to be turned off and controls the second transistor to be turned on, the first signal line is broken, and the signal on the first signal line is transmitted to the first test end through the second transistor.

17. The abnormality locating method according to claim 16, wherein: The signal steering unit further includes a second signal steering unit; The second signal steering unit includes a third transistor and a fourth transistor, The gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal; the first electrode of the third transistor and the first electrode of the fourth transistor are connected to the second signal line; The second electrode of the third transistor is connected to the second signal line; the second electrode of the fourth transistor is connected to the second test terminal; The abnormality locating method further includes: the second control end controls the third transistor to be turned off and controls the fourth transistor to be turned on, the second signal line is broken, and the signal on the second signal line is transmitted to the second test end through the fourth transistor.

18. A method for detecting abnormality of a display panel, wherein: The display panel comprises the gate driving circuit according to any one of claims 1 to 8; The anomaly detection method comprises: Controlling a signal steering unit in the gate driving circuit to change a transmission path of a signal on a first signal line, so that the first signal line is disconnected and a first abnormality occurs on the display panel; Comparing the first abnormality with the abnormal state of the fault display panel to determine whether the first abnormality is consistent with the abnormal state of the fault display panel; If yes, it is determined that the first signal line of the fault display panel is abnormal; if no, it is determined that the first signal line of the fault display panel is normal; and / or, controlling a signal steering unit in the gate driving circuit to change a transmission path of a signal on a second signal line, so that the second signal line is disconnected and a second abnormality occurs on the display panel; Comparing the second abnormality with the abnormal state of the fault display panel to determine whether the second abnormality is consistent with the abnormal state of the fault display panel; If yes, it is determined that the second signal line of the fault display panel is abnormal; if no, it is determined that the second signal line of the fault display panel is normal.

19. The abnormality detection method according to claim 18, wherein: There are a plurality of first signal lines and a plurality of second signal lines; Different first signal lines and different second signal lines are respectively connected to different signal steering units; The abnormality detection method includes: performing abnormality detection on the first signal line and the second signal line one by one.

20. The abnormality detection method according to claim 18, wherein: The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit provides a gate control cascade signal to the pixel unit; The second gate driving circuit provides a light emitting control cascade signal to the pixel unit; The abnormality detection method comprises: performing abnormality detection on the first signal line and the second signal line in the first gate driving circuit one by one; The first signal line and the second signal line in the second gate driving circuit are detected for abnormality one by one.

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