Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a reset driving circuit, the reset driving circuit comprises a plurality of cascaded shifting registers, each shifting register comprises a pull-up control module and a pull-up module, a square wave signal is accessed through the pull-up module to replace an accessed high-potential signal, and the reset driving circuit is connected with the pull-up control module. According to the technical scheme, the low-potential square wave signal can be output as the reset control signal in the black insertion period, so that the low-potential reset control signal can be obtained in the black insertion period, and the problem that a driving time sequence is wrong due to the fact that a high-potential reset control signal is output in the black insertion period is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel, in order to achieve an expected display effect of a pixel circuit, it is necessary to provide corresponding driving timings for the pixel circuit, and these driving timings can be provided by corresponding gate driving circuits.

[0003] However, as the driving timing required by the pixel circuit changes, the gate driving circuit also needs to be improved accordingly to achieve the expected display effect. Summary of the invention

[0004] The present application provides a display panel and a display device to alleviate the technical problem that a reset driving circuit in a gate driving circuit outputs a high-potential reset control signal during black insertion, resulting in a driving timing error.

[0005] In a first aspect, the present application provides a display panel, which includes a reset drive circuit, the reset drive circuit includes a plurality of cascaded shift registers, the shift register includes a pull-up control module and a pull-up module, the pull-up control module is configured to control the transmission of a high-voltage signal to a pull-up node according to an initialization control signal; the pull-up module is configured to output a low-voltage square wave signal as a reset control signal during a black insertion period according to the signal of the pull-up node.

[0006] In a second aspect, the present application provides a display device, which includes the above-mentioned display panel.

[0007] The display panel and display device provided by the present application can replace the high-voltage signal by connecting a square wave signal through a pull-up module, and can output a low-voltage square wave signal as a reset control signal during the black insertion period. This can obtain a low-voltage reset control signal during the black insertion period, thereby avoiding the problem of driving timing errors caused by outputting a high-voltage reset control signal during black insertion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0009] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0010] Figure 2 A schematic diagram of the structure of a shift register in a reset drive circuit provided in an embodiment of the present application.

[0011] Figure 3A schematic diagram of the structure of a light-emitting driving unit in a light-emitting driving circuit provided in an embodiment of the present application.

[0012] Figure 4 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.

[0013] Figure 5 A timing diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0015] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0016] See also Figures 1 to 5 , Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. The display panel includes a pixel circuit 50, a reset driving circuit 10 that provides a reset control signal REF for the pixel circuit 50, a light-emitting driving circuit 20 that provides a light-emitting control signal EM for the pixel circuit 50, a scanning driving circuit 30 that provides a scanning signal Gn for the pixel circuit 50, and an initialization driving circuit 40 that provides an initialization control signal INI for the pixel circuit 50.

[0017] The reset driving circuit 10, the light emitting driving circuit 20, the scanning driving circuit 30 and the initialization driving circuit 40 are all one of the gate driving circuits (GOA circuits). In other embodiments, the scanning signal Gn and the initialization control signal INI may also be provided by the same gate driving circuit.

[0018] The reset driving circuit 10 includes a plurality of cascaded shift registers, wherein the n-th stage shift register can output the n-th stage reset control signal REF[n].

[0019] The light emitting driving circuit 20 may include a plurality of cascaded light emitting driving units, wherein the n-th light emitting driving unit may output the n-th light emitting control signal EM[n].

[0020] The scan driving circuit 30 may include a plurality of cascaded scan driving units, wherein the n-1th scan driving unit may output the n-1th scan signal Gn[n-1], and the nth scan driving unit may output the nth scan signal Gn[n].

[0021] The initialization driving circuit 40 may include a plurality of cascaded initialization driving units, wherein the nth initialization driving unit may output the nth initialization control signal INI[n], and the n+1th initialization driving unit may output the n+1th initialization control signal INI[n+1].

[0022] The pixel circuits 50 may be distributed in an array in the display area of ​​the display panel.

[0023] In some embodiments, such as Figure 2 As shown, the shift register includes a pull-up control module 11 and a pull-up module 12. The pull-up control module 11 is configured to control the high potential signal VGH to be transmitted to the pull-up node Q according to the initialization control signal INI; the pull-up module 12 is configured to output a low potential square wave signal LC as the nth level reset control signal REF[n] during the black insertion period according to the signal of the pull-up node Q.

[0024] It can be understood that the display panel provided in this embodiment can output a low-potential square wave signal LC as the n-th level reset control signal REF[n] during the black insertion period by connecting the square wave signal LC through the pull-up module 12 to replace the connected high-potential signal VGH. This can obtain a low-potential reset control signal REF during the black insertion period, thereby avoiding the problem of driving timing error caused by outputting a high-potential reset control signal REF during black insertion.

[0025] In some embodiments, such as Figure 2 As shown, the pull-up module 12 includes a pull-up transistor T21, the gate of the pull-up transistor T21 is connected to the pull-up node Q, the first electrode of the pull-up transistor T21 is configured to access the square wave signal LC, and the second electrode of the pull-up transistor T21 is configured to output the nth level reset control signal REF[n].

[0026] It should be noted that the pull-up transistor T21 can be exemplarily an N-channel transistor. If the signal of the pull-up node Q is at a high potential during the black insertion period, the pull-up transistor T21 is turned on and the low-potential square wave signal LC can be output as a low-potential nth level reset control signal REF[n].

[0027] The first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source.

[0028] Alternatively, if Figure 2 As shown, the pull-up module 12 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the gate of the pull-up transistor T21, and a second end of the first capacitor C1 is connected to the second electrode of the pull-up transistor T21. The first capacitor C1 can play a role of bootstrapping to increase the gate potential of the pull-up transistor T21.

[0029] In some embodiments, such as Figure 2 As shown, the pull-up control module 11 may include a pull-up control transistor T11, a first electrode of the pull-up control transistor T11 is connected to the high potential signal VGH, a gate of the pull-up control transistor T11 is connected to the n+1th level initialization control signal INI[n+1], and a second electrode of the pull-up control transistor T11 is connected to the pull-up node Q.

[0030] The pull-up control transistor T11 may be illustratively an N-channel transistor, and when the pull-up control transistor T11 is turned on or turned on, the pull-up node Q is charged. In some other embodiments, the pull-up control transistor T11 may also include two transistors connected in series with their gates connected to reduce leakage.

[0031] In some embodiments, such as Figure 2 As shown, the shift register may further include a first transistor T43, a first electrode of the first transistor T43 is connected to the pull-up node Q, a second electrode of the first transistor T43 is connected to the first low potential line, and a gate of the first transistor T43 is connected to the pull-down node QB. The first transistor T43 is used to transmit the first low potential signal VGL1 in the first low potential line to the pull-up node Q under the control of the signal of the pull-down node QB. The first transistor T43 may be exemplarily an N-channel transistor.

[0032] In some embodiments, such as Figure 2 As shown, the shift register may further include a second transistor T55, a first electrode of the second transistor T55 is connected to the pull-down node QB, a second electrode of the second transistor T55 is connected to the first low potential line, and a gate of the second transistor T55 is connected to the pull-up node Q. The second transistor T55 is used to transmit the first low potential signal VGL1 in the first low potential line to the pull-down node QB under the control of the signal of the pull-up node Q. The second transistor T55 may be exemplarily an N-channel transistor.

[0033] In some embodiments, such as Figure 2As shown, the shift register may further include a third transistor T56, a first electrode of the third transistor T56 is connected to the pull-down node QB, a second electrode of the third transistor T56 is connected to the first low potential line, and a gate of the third transistor T56 is connected to the n+1-th level initialization control signal INI[n+1]. The third transistor T56 is used to transmit the first low potential signal VGL1 in the first low potential line to the pull-down node QB under the control of the n+1-th level initialization control signal INI[n+1]. The third transistor T56 may be exemplarily an N-channel transistor.

[0034] In some embodiments, such as Figure 2 As shown, the shift register may further include a fourth transistor T42, a first electrode of the fourth transistor T42 is connected to the pull-up node Q, a second electrode of the fourth transistor T42 is connected to the first low potential line, and a gate of the fourth transistor T42 is connected to the n-1th level scanning signal Gn[n-1]. The fourth transistor T42 is used to transmit the first low potential signal VGL1 in the first low potential line to the pull-up node Q under the control of the n-1th level scanning signal Gn[n-1]. The fourth transistor T42 may be exemplarily an N-channel transistor.

[0035] In some embodiments, such as Figure 2 As shown, the shift register may further include a fifth transistor T54 and a second capacitor C2, wherein a first electrode of the fifth transistor T54 is connected to a first end of the second capacitor C2 and is connected to a high potential signal VGH, a second electrode of the fifth transistor T54 is connected to a pull-down node QB, and a gate of the fifth transistor T54 is connected to a second end of the second capacitor C2 and a first node T. The fifth transistor T54 is used to transmit the high potential signal VGH to the pull-down node QB according to a signal of the first node T. The fifth transistor T54 may be exemplarily an N-channel transistor.

[0036] In some embodiments, such as Figure 2 As shown, the shift register may further include a sixth transistor T52_A, a first electrode of the sixth transistor T52_A is connected to the gate of the sixth transistor T52_A and is connected to the n-1th level scan signal Gn[n-1], and a second electrode of the sixth transistor T52_A is connected to the first node T. The sixth transistor T52_A is used to transmit the n-1th level scan signal Gn[n-1] to the first node T under the control of the n-1th level scan signal Gn. The sixth transistor T52_A may be exemplarily an N-channel transistor.

[0037] In some embodiments, such as Figure 2As shown, the shift register may further include a seventh transistor T52_B, a first electrode of the seventh transistor T52_B is connected to the low potential signal VGL, a gate of the seventh transistor T52_B is connected and connected to the n-th stage initialization control signal INI[n], and a second electrode of the seventh transistor T52_B is connected to the first node T. The seventh transistor T52_B is used to transmit the low potential signal VGL to the first node T under the control of the n-th stage initialization control signal INI[n]. The seventh transistor T52_B may be exemplarily an N-channel transistor.

[0038] In some embodiments, such as Figure 2 As shown, the shift register may further include an eighth transistor T31, a first electrode of the eighth transistor T31 is connected to the second low potential signal VGL2, a gate of the eighth transistor T31 is connected to the pull-down node QB, and a second electrode of the eighth transistor T31 is connected to the second electrode of the pull-up transistor T21. The eighth transistor T31 is used to output the second low potential signal VGL2 as a low potential n-th stage reset control signal REF[n] under the control of the signal of the pull-down node QB. The eighth transistor T31 may be exemplarily an N-channel transistor.

[0039] like Figure 3 As shown, the light-emitting driving unit includes a ninth transistor T13, a first electrode of the ninth transistor T13 is connected to the high potential signal VGH, a second electrode of the ninth transistor T13 is connected to the second node Q[n], and a gate of the ninth transistor T13 is connected to the first clock signal. The first clock signal may be one of CKA1-CKA4. The ninth transistor T13 is used to control the high potential signal VGH to be transmitted to the second node Q[n] according to the first clock signal. The ninth transistor T13 may be exemplarily an N-channel transistor.

[0040] like Figure 3 As shown, the light-emitting driving unit further includes a tenth transistor T22, a first electrode of the tenth transistor T22 is connected to the high potential signal VGH, a second electrode of the tenth transistor T22 is used to output the n-th level light-emitting control signal EM[n], and a gate of the tenth transistor T22 is connected to the second node Q[n]. The tenth transistor T22 is used to output the n-th level light-emitting control signal EM[n] with the high potential signal VGH being a high potential according to the signal of the second node Q[n]. The tenth transistor T22 can be exemplarily an N-channel transistor.

[0041] like Figure 3 As shown, the light-emitting driving unit further includes a third capacitor C3, a first end of the third capacitor C3 is connected to the second electrode of the tenth transistor T22, and a second end of the third capacitor C3 is connected to the gate of the tenth transistor T22.

[0042] like Figure 3As shown, the light-emitting driving unit further includes an eleventh transistor T32, a first electrode of the eleventh transistor T32 is connected to the first low potential signal VGL1, a second electrode of the eleventh transistor T32 is used to output a low potential n-th level light-emitting control signal EM[n], and a gate of the eleventh transistor T32 is connected to the third node QB[n]. The eleventh transistor T32 is used to output the first low potential signal VGL1 as a low potential n-th level light-emitting control signal EM[n] according to the signal of the third node QB[n]. The eleventh transistor T32 can be exemplarily an N-channel transistor.

[0043] like Figure 3 As shown, the light-emitting driving unit further includes a twelfth transistor T12, a first electrode of the twelfth transistor T12 is connected to the first low potential signal VGL1, a second electrode of the twelfth transistor T12 is connected to the third node QB[n], and a gate of the twelfth transistor T12 is connected to the first clock signal. The twelfth transistor T12 is used to control the first low potential signal VGL1 to be transmitted to the third node QB[n] according to the first clock signal. The twelfth transistor T12 can be exemplarily an N-channel transistor.

[0044] like Figure 3 As shown, the light-emitting driving unit further includes a thirteenth transistor T53, a first electrode of the thirteenth transistor T53 is connected to the gate of the thirteenth transistor T53 and is connected to the n-th level initialization control signal INI[n], and a second electrode of the thirteenth transistor T53 is connected to the third node QB[n]. The thirteenth transistor T53 is used to control the n-th level initialization control signal INI[n] to be transmitted to the third node QB[n] according to the n-th level initialization control signal INI[n]. The thirteenth transistor T53 can be exemplarily an N-channel transistor.

[0045] like Figure 3 As shown, the light-emitting driving unit further includes a fourteenth transistor T57, a first electrode of the fourteenth transistor T57 is connected to the gate of the fourteenth transistor T57 and is connected to the n-th level scanning signal Gn[n], and a second electrode of the fourteenth transistor T57 is connected to the third node QB[n]. The fourteenth transistor T57 is used to control the n-th level scanning signal Gn[n] to be transmitted to the third node QB[n] according to the n-th level scanning signal Gn[n]. The fourteenth transistor T57 can be exemplarily an N-channel transistor.

[0046] like Figure 3As shown, the light-emitting driving unit further includes a fifteenth transistor T52, a first electrode of the fifteenth transistor T52 is connected to the first low potential signal VGL1, a gate of the fifteenth transistor T52 is connected to the second node Q[n], and a second electrode of the fifteenth transistor T52 is connected to the third node QB[n]. The fifteenth transistor T52 is used to control the first low potential signal VGL1 to be transmitted to the third node QB[n] according to the signal of the second node Q[n]. The fifteenth transistor T52 can be exemplarily an N-channel transistor.

[0047] like Figure 3 As shown, the light-emitting driving unit further includes a sixteenth transistor T44 and a seventeenth transistor T45, the first electrode of the sixteenth transistor T44 is connected to the second node Q[n], the gate of the sixteenth transistor T44 is connected to the gate of the seventeenth transistor T45 and the third node QB[n], the second electrode of the sixteenth transistor T44 is connected to the first electrode of the seventeenth transistor T45, and the second electrode of the seventeenth transistor T45 is connected to the first low potential signal VGL1. The sixteenth transistor T44 and the seventeenth transistor T45 are used to control the first low potential signal VGL1 to be transmitted to the second node Q[n] according to the signal of the third node QB[n] in the case of preventing leakage. The sixteenth transistor T44 and the seventeenth transistor T45 can be exemplarily both N-channel transistors.

[0048] like Figure 3 As shown, the light-emitting driving unit further includes an eighteenth transistor T61 and a nineteenth transistor T62, the first electrode of the eighteenth transistor T61 is connected to the high potential signal VGH, the gate of the eighteenth transistor T61 is connected to the gate of the nineteenth transistor T62 and the second node Q[n], the second electrode of the eighteenth transistor T61 is connected to the first electrode of the nineteenth transistor T62, and the second electrode of the nineteenth transistor T62 is connected to the second electrode of the sixteenth transistor T44. The eighteenth transistor T61 and the nineteenth transistor T62 are used to control the high potential signal VGH to be transmitted to the second electrode of the sixteenth transistor T44 according to the signal of the second node Q[n], so as to prevent the second node Q[n] from leaking through the sixteenth transistor T44 and the seventeenth transistor T45. The eighteenth transistor T61 and the nineteenth transistor T62 can be exemplarily both N-channel transistors.

[0049] like Figure 4 As shown, the pixel circuit 50 includes a driving transistor Tdr, a light emitting control transistor Te, a light emitting device Di and a reset transistor Tr. The light emitting control transistor Te is connected between a first power line and a first electrode of the driving transistor Tdr; the light emitting device Di is connected between a second power line and a second electrode of the driving transistor Tdr; the reset transistor Tr is connected between a gate of the driving transistor Tdr and a reference voltage line, and the gate of the reset transistor Tr is connected to a reset control signal REF.

[0050] The light emitting stage of the pixel circuit 50 includes a black insertion period, during which the light emitting control transistor Te and the reset transistor Tr are both turned off. During the black insertion period, by turning off the light emitting control transistor Te and the reset transistor Tr, black insertion can be achieved by turning off the light emitting control transistor Te without reducing the gate potential of the driving transistor Tdr.

[0051] The potential of the first power signal VDD transmitted in the first power line is higher than the potential of the second power signal VSS transmitted in the second power line.

[0052] The gate of the light emitting control transistor Te is connected to the light emitting control signal EM. The reference voltage line is used to transmit the reference voltage signal Vref.

[0053] The light emitting device Di may be an organic light emitting diode, a mini light emitting diode, a micro light emitting diode or a quantum dot light emitting diode.

[0054] In some embodiments, such as Figure 4 As shown, the pixel circuit 50 further includes a write transistor Tw, and the write transistor Tw is configured to control the data signal Vdata to be transmitted to the gate of the driving transistor Tdr according to the scan signal Gn.

[0055] It should be noted that in the writing frame of the pixel circuit 50, the writing transistor Tw is turned on to write the data signal Vdata to the gate of the driving transistor Tdr. In the holding frame of the pixel circuit 50, the writing transistor Tw is turned off to control the data signal Vdata not to be written to the gate of the driving transistor Tdr.

[0056] In some embodiments, such as Figure 4 As shown, the pixel circuit 50 further includes a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor Tdr, and a second end of the storage capacitor Cst is connected to the source of the driving transistor Tdr.

[0057] In some embodiments, such as Figure 4 As shown, the pixel circuit 50 further includes an initialization transistor Ti, a first electrode of the initialization transistor Ti is connected to the initialization signal Vini, a second electrode of the initialization transistor Ti is connected to the source of the driving transistor Tdr, and a gate of the initialization transistor Ti is connected to the initialization control signal INI. The initialization transistor Ti is configured to control the initialization signal Vini to be transmitted to the source of the driving transistor Tdr according to the initialization control signal INI.

[0058] Each transistor in the pixel circuit 50 may be illustratively an N-channel transistor. Figure 5A timing diagram of a display panel provided in an embodiment of the present application. Each frame of the display panel includes a write frame or a hold frame.

[0059] In the write frame, the square wave signal LC is at a high potential, the initialization control signal INI is at a high potential, the initialization transistor Ti is turned on to initialize the source potential of the driving transistor Tdr; the reset control signal REF is at a high potential, the reset transistor Tr is turned on to reset the gate potential of the driving transistor Tdr; the light-emitting control signal EM is at a low potential, and the light-emitting control transistor Te is turned off to isolate the influence of the first power supply signal VDD on the potentials of each electrode of the driving transistor Tdr; when the scanning signal Gn is at a high potential and the light-emitting control signal EM is at a low potential, the data signal Vdata can be written to the gate of the driving transistor Tdr through the write transistor Tw when the light-emitting control transistor Te is turned off. When the initialization control signal INI, the reset control signal REF and the scanning signal Gn are all at a low potential, and the light-emitting control signal EM is at a high potential, the pixel circuit 50 is in the light-emitting stage.

[0060] In the hold frame, the square wave signal LC is at a low potential. Since the second electrode of the pull-up transistor T21 is configured to output the low potential square wave signal LC as a low potential reset control signal REF, even if the initialization control signal INI is at a high potential, the reset control signal REF will not be at a high potential in the reset drive circuit 10, thereby affecting the pixel circuit 50 to implement the black insertion function through the light emitting control transistor Te. When the initialization control signal INI, the reset control signal REF and the scanning signal Gn are all at a low potential, and the light emitting control signal EM is at a high potential, the pixel circuit 50 is in the light emitting stage.

[0061] Whether in the writing frame or the holding frame, there is a light-emitting stage, and each light-emitting stage may include at least one of a light-emitting period and a black-insertion period, wherein the light-emitting device Di is emitting light in the light-emitting period, and the light-emitting device Di is not emitting light or is in a dark state in the black-insertion period.

[0062] In some of the embodiments, the present embodiment provides a display device, which includes the above-mentioned display panel.

[0063] It can be understood that, since the display device provided in this embodiment includes the above-mentioned display panel, it is also possible to connect the square wave signal LC through the pull-up module 12 to replace the connected high-voltage signal VGH, and output the low-voltage square wave signal LC as the reset control signal REF during the black insertion period, which can obtain the low-voltage reset control signal REF during the black insertion period, thereby avoiding the problem of driving timing error caused by outputting the high-voltage reset control signal REF during black insertion.

[0064] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] The display panel and the display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a reset driving circuit, the reset driving circuit includes a plurality of cascaded shift registers, and the shift registers include: A pull-up control module, wherein the pull-up control module is configured to control the high potential signal to be transmitted to the pull-up node according to the initialization control signal; The pull-up module is configured to output a low-potential square wave signal as a reset control signal during a black insertion period according to a signal of the pull-up node.

2. The display panel according to claim 1, characterized in that: The pull-up module includes a pull-up transistor, a gate of the pull-up transistor is connected to the pull-up node, a first electrode of the pull-up transistor is configured to access the square wave signal, and a second electrode of the pull-up transistor is configured to output the reset control signal.

3. The display panel according to claim 2, characterized in that: Each frame of the display panel includes a writing frame or a holding frame. In the holding frame, the square wave signal is at a low potential, and the second electrode of the pull-up transistor is configured to output the reset control signal at a low potential.

4. The display panel according to claim 3, characterized in that: In a write frame, the square wave signal is at a high level.

5. The display panel according to any one of claims 1 to 4, characterized in that: The display panel further includes a pixel circuit, and the pixel circuit includes: Driver transistor; a light emitting control transistor, the light emitting control transistor being connected between the first power line and the first electrode of the driving transistor; a light emitting device connected between a second power line and a second electrode of the driving transistor; A reset transistor, wherein the reset transistor is connected between the gate of the driving transistor and a reference voltage line, and the gate of the reset transistor is connected to the reset control signal; The light emitting stage of the pixel circuit includes the black insertion period, during which the light emitting control transistor and the reset transistor are both turned off.

6. The display panel according to claim 5, characterized in that: The reset transistor is an N-channel transistor, and during the black insertion period, the reset control signal is at a low potential.

7. The display panel according to claim 5, characterized in that: The pixel circuit further includes a write transistor configured to control the data signal to be transmitted to the gate of the drive transistor according to the scan signal.

8. The display panel according to claim 7, characterized in that: In the pixel circuit, in a writing frame, the writing transistor is turned on to write the data signal to the gate of the driving transistor.

9. The display panel according to claim 8, characterized in that: In the pixel circuit, in a holding frame, the write transistor is turned off to control the data signal not to be written to the gate of the drive transistor.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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