Refresh Circuit, Refresh Method, and Memory of a Memory

Abstract

Embodiments of the present disclosure provide a refresh circuit, a refresh method, and a memory for a memory. The refresh circuit includes an address generation module and an address decoding module. The address generation module generates an address signal and determines a word line control signal according to a refresh command. The address decoding module determines M address selection signals according to the address signal and the word line control signal. Each address selection signal includes a module address selection signal and a row address selection signal. The M module address selection signals correspond to M memory modules one by one, and the M row address selection signals correspond to M word lines one by one. Thus, the M address selection signals correspond to M different word lines of all memory modules, and different word lines of all memory modules can be opened simultaneously, which can reduce the voltage drop on the word lines and shorten the operation duration of the word lines, thereby improving the success rate of memory refresh and further improving the stability of the memory.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of memories, and in particular, to a refresh circuit, a refresh method, and a memory of a memory. Background Art

[0002] The storage unit of a dynamic random access memory (DRAM) consists of a capacitor and a switch. The data of the DRAM is stored in the capacitor. Since the capacitor will gradually lose charge, if regular refreshing is not performed, the stored data may be damaged. Therefore, the DRAM requires regular refreshing operations to recharge to ensure the accuracy of the data. When the DRAM is refreshed, the address signal is generated by an internal counter. Since the order of the address signals generated by the internal counter is fixed, during the refresh operation, the order of opening the word lines of all storage units is fixed.

[0003] In the prior art, the word lines of all the same storage modules are opened simultaneously, resulting in a large voltage drop on the word lines. The word lines of the storage modules farther from the power supply act slower, affecting the success rate of refreshing and resulting in poor stability of the memory. Summary of the Invention

[0004] The present disclosure provides a refresh circuit, a refresh method, and a memory of a memory, which can reduce the voltage drop on the word lines and shorten the action duration of the word lines, thereby improving the success rate of memory refreshing and further improving the stability of the memory.

[0005] In a first aspect, the present disclosure provides a refresh circuit of a memory. The memory includes M storage modules arranged along a first direction, and each of the storage modules includes m storage units arranged along a second direction. The first direction and the second direction intersect. The M storage units arranged along the first direction are connected to the same word line, M = 2 N , N is an integer greater than zero, and m is an integer greater than or equal to M. The refresh circuit includes: an address generation module and an address decoding module.

[0006] The address generation module is configured to generate an address signal and determine a word line control signal according to a refresh command. The address decoding module is configured to determine M address selection signals according to the address signal and the word line control signal, where each of the address selection signals includes a module address selection signal and a row address selection signal. The M module address selection signals correspond to the M storage modules one by one, and the M row address selection signals correspond to the M word lines one by one.

[0007] In some embodiments of the present disclosure, the address decoding module includes a combinational logic unit and an address latch unit. The address input terminal of the combinational logic unit is connected to the address output terminal of the address generation module. The address output terminal of the combinational logic unit is connected to the address input terminal of the address latch unit. The control terminal of the address latch unit is connected to the word line control output terminal of the address generation module. The first level input terminal of the combinational logic unit is connected to a high level, and the second level input terminal of the combinational logic unit is connected to a low level.

[0008] The combinational logic unit is configured to determine M module address selection signals according to the module address signals in the address signal, and determine M row address selection signals according to the row address signals in the address signal. The address latch unit is configured to output M address selection signals when the word line control signal is at a high level.

[0009] In some embodiments of the present disclosure, the combinational logic unit includes M logic units. The module address signal includes N module address sub-signals. The N address input terminals of each logic unit are respectively connected to the N module address sub-signals in a one-to-one correspondence. The first level input terminal of the logic unit is connected to a high level or a low level. The second level input terminal of the logic unit is connected to a high level or a low level. The output terminal of the logic unit is connected to the address input terminal of the address latch unit.

[0010] Each logic unit is configured to force the N module address sub-signals to be at a high level or a low level to obtain one module address selection signal.

[0011] In some embodiments of the present disclosure, the combinational logic unit includes a first logic unit, a second logic unit, a third logic unit, and a fourth logic unit. The module address signal includes a first module address sub-signal and a second module address sub-signal.

[0012] The first level input terminal and the second level input terminal of the first logic unit are connected to a low level. The first address input terminal of the first logic unit is connected to the first module address sub-signal. The second address input terminal of the first logic unit is connected to the second module address sub-signal. The output terminal of the first logic unit is connected to the first address input terminal of the address latch unit. The first level input terminal of the second logic unit is connected to a low level. The second level input terminal of the second logic unit is connected to a high level. The first address input terminal of the second logic unit is connected to the first module address sub-signal. The second address input terminal of the second logic unit is connected to the second module address sub-signal. The output terminal of the second logic unit is connected to the second address input terminal of the address latch unit.

[0013] The first level input terminal of the third logic unit is connected to a high level, the second level input terminal of the third logic unit is connected to a low level, the first address input terminal of the third logic unit is connected to the first module address sub-signal, the second address input terminal of the third logic unit is connected to the second module address sub-signal, and the output terminal of the third logic unit is connected to the third address input terminal of the address latch unit. The first level input terminal and the second level input terminal of the fourth logic unit are connected to a high level, the first address input terminal of the fourth logic unit is connected to the first module address sub-signal, the second address input terminal of the fourth logic unit is connected to the second module address sub-signal, and the output terminal of the fourth logic unit is connected to the fourth address input terminal of the address latch unit.

[0014] The first logic unit is configured to force the first module address sub-signal and the second module address sub-signal to be output as low levels to obtain a first module address selection signal. The second logic unit is configured to force the first module address sub-signal to be output as a high level and the second module address sub-signal to be output as a low level to obtain a second module address selection signal. The third logic unit is configured to force the first module address sub-signal to be output as a low level and the second module address sub-signal to be output as a high level to obtain a third module address selection signal. The fourth logic unit is configured to force the first module address sub-signal and the second module address sub-signal to be output as high levels to obtain a fourth module address selection signal.

[0015] In some embodiments of the present disclosure, each of the logic units includes N exclusive-OR gates and 2N inverters. In each of the logic units, two input terminals of each of the exclusive-OR gates are respectively connected to output terminals of two of the inverters, input terminals of N of the inverters are respectively connected to N of the module address sub-signals, input terminals of the other N inverters are connected to a high level or a low level, and an output terminal of each of the exclusive-OR gates is connected to an address input terminal of the address latch unit.

[0016] In some embodiments of the present disclosure, each of the logic units includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first exclusive-OR gate, and a second exclusive-OR gate. The input terminal of the first inverter is connected to a first module address sub-signal, and the output terminal of the first inverter is connected to the first input terminal of the first exclusive-OR gate. The input terminal of the second inverter is connected to a low level or a high level, and the output terminal of the second inverter is connected to the second input terminal of the first exclusive-OR gate. The input terminal of the third inverter is connected to a second module address sub-signal, and the output terminal of the third inverter is connected to the first input terminal of the second exclusive-OR gate. The input terminal of the fourth inverter is connected to a low level or a high level, and the output terminal of the fourth inverter is connected to the second input terminal of the second exclusive-OR gate. The output terminals of the first exclusive-OR gate and the second exclusive-OR gate are connected to the address input terminals of the address latch unit.

[0017] In some embodiments of the present disclosure, the address latch unit includes M address latches. The address input terminals of the M address latches are connected to the output terminals of the M logic units in a one-to-one correspondence, and the control terminals of the M address latches are all connected to the word line control output terminal of the address generation module.

[0018] In some embodiments of the present disclosure, the address generation module includes a command decoder, a word line control signal generator, and an internal counter. The output terminal of the command decoder is connected to the input terminal of the word line control signal generator and the input terminal of the internal counter. The output terminal of the internal counter is connected to the address input terminal of the address decoding module, and the output terminal of the word line control signal generator is connected to the control terminal of the address decoding module.

[0019] The command decoder is configured to generate an internal refresh command in response to the received refresh command. The word line control signal generator is configured to pull up the word line control signal according to the internal refresh command. The internal counter is configured to generate the address signal according to the internal refresh command.

[0020] In a second aspect, the present disclosure provides a refresh method for a memory, which is applied to any of the refresh circuits provided in the first aspect. The refresh method includes:

[0021] Generating an address signal and determining a word line control signal according to a refresh command; determining M address selection signals according to the address signal and the word line control signal.

[0022] Wherein, each of the address selection signals includes a module address selection signal and a row address selection signal. The M module address selection signals correspond to the M storage modules in a one-to-one correspondence, and the M row address selection signals correspond to the M word lines in a one-to-one correspondence.

[0023] In a third aspect, the present disclosure provides a memory, including M memory modules arranged along a first direction and any one of the refresh circuits provided in the first aspect.

[0024] Wherein, each of the memory modules includes m memory cells arranged along a second direction, the first direction and the second direction intersect, M memory cells arranged along the first direction are connected to the same word line, M = 2 N , N is an integer greater than zero, and m is an integer greater than or equal to M.

[0025] In the technical solution of the present disclosure, a refresh circuit is provided, including an address generation module and an address decoding module. The address generation module generates an address signal and determines a word line control signal according to a refresh command. The address decoding module determines M address selection signals according to the address signal and the word line control signal. Among them, each address selection signal includes a module address selection signal and a row address selection signal. The M module address selection signals correspond to the M memory modules one by one, and the M row address selection signals correspond to the M word lines one by one. In this way, the M address selection signals correspond to M different word lines of all memory modules, and different word lines of all memory modules can be opened simultaneously, which can reduce the voltage drop on the word line and shorten the operation time of the word line, thereby improving the success rate of memory refreshing and further improving the stability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0027] Figure 1 FIG. 18 is a schematic structural diagram of a memory provided by the prior art;

[0028] Figure 2 FIG. 22 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure;

[0029] Figure 3 FIG. 26 is a schematic structural diagram of a refresh circuit provided by an embodiment of the present disclosure;

[0030] Figure 4 FIG. 30 is a working timing diagram of the refresh circuit provided by an embodiment of the present disclosure;

[0031] Figure 5 FIG. 34 is a circuit schematic diagram of an address decoding module provided by an embodiment of the present disclosure;

[0032] Figure 6 FIG. 38 is a schematic flowchart of a refresh method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts also fall within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. Further, it will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly defined otherwise herein. As used herein, the statement of joining two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0035] The mention of "embodiments" in the present disclosure means that specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The phrase "embodiments" appearing at various positions in the specification does not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described in the present disclosure may be combined with other embodiments.

[0036] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or in the above-mentioned drawings are used to distinguish different objects and not to describe a specific order, and may explicitly or implicitly include one or more of such features.

[0037] The term "and / or" in the present disclosure is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: the existence of A, the simultaneous existence of A and B, and the existence of B. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0038] In the description of the present disclosure, unless otherwise specified, the meanings of "a plurality" and "at least two" refer to more than two (including two). Similarly, "multiple groups" and "at least two groups" refer to more than two groups (including two groups).

[0039] To enable those skilled in the art of this technology to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0040] Figure 1 A structural schematic diagram of a memory provided for the prior art is shown as Figure 1 shown. The memory includes a counter 30, a plurality of storage modules 10, and a plurality of word lines 20. Each storage module 10 includes a plurality of storage cells 11. A plurality of storage cells 11 in the row direction are connected to the same word line 20. Each word line 20 is connected to a power supply. When the memory is refreshed, the counter 30 generates an address signal, and based on this address signal, the word line 20 of the corresponding storage cell 11 can be selected and opened.

[0041] In practical applications, the order of the address signals generated by the counter 30 is fixed. Therefore, when the memory performs a refresh operation, the opening order of the word lines 20 of all storage cells 11 is fixed. As Figure 1 shown, when the memory performs a refresh operation, the word lines 20 of all storage modules 10 are opened simultaneously. Therefore, the voltage drop on the word line 20 is relatively large, and the word line 20 of the storage module 10 farther from the power supply moves slower, affecting the action duration of the word line 20. When the action duration of the word line 20 is relatively long, the success rate of the memory refresh is relatively low, resulting in relatively poor stability of the memory.

[0042] In view of this, the present disclosure provides a refresh circuit for a memory, including an address generation module and an address decoding module. The address generation module generates an address signal and determines a word line control signal according to a refresh command. The address decoding module determines M address selection signals according to the address signal and the word line control signal. Each address selection signal includes a module address selection signal and a row address selection signal. The M module address selection signals correspond to the M storage modules one by one, and the M row address selection signals correspond to the M word lines one by one. Thus, the M address selection signals correspond to M different word lines of all storage modules, and different word lines of all storage modules can be opened simultaneously, which can reduce the voltage drop on the word line, shorten the action duration of the word line, thereby improving the success rate of the memory refresh and further improving the stability of the memory.

[0043] The following uses several specific embodiments to describe in detail the technical solutions provided by the present disclosure.

[0044] Figure 2 A structural schematic diagram of a memory provided for an embodiment of the present disclosure is shown as Figure 2 shown. The memory includes a refresh circuit 100 and M storage modules 10 arranged in the first direction, where M = 2 N , and N is an integer greater than zero. Each storage module 10 includes m storage cells 11 arranged in the second direction, where m is an integer greater than or equal to M. The first direction and the second direction intersect. M storage cells 11 arranged in the first direction are connected to the same word line 20.

[0045] Exemplarily, asFigure 2 As shown, the memory includes four storage modules 10, namely, a first storage module 10a, a second storage module 10b, a third storage module 10c and a fourth storage module 10d, and the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d are arranged in sequence along the first direction. Each storage module 10 includes four storage units 11, respectively denoted as storage unit 11a, storage unit 11b, storage unit 11c and storage unit 11d, and the storage units 11a, storage unit 11b, storage unit 11c and storage unit 11d in each storage module 10 are arranged in sequence along the second direction.

[0046] The memory includes four word lines 20, namely a first word line 21, a second word line 22, a third word line 23 and a fourth word line 24. The first word line 21 connects the memory cell 11a in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d, the second word line 22 connects the memory cell 11b in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d, the third word line 23 connects the memory cell 11c in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d, and the fourth word line 24 connects the memory cell 11d in the first storage module 10a, the second storage module 10b, the third storage module 10c and the fourth storage module 10d.

[0047] It should be noted that Figure 2 Taking N=2 as an example, the memory includes 2 2 In practical applications, the number of storage modules 10 can also be 2. 1 , 2 3 or 2 N , N is any integer greater than 3, and the present disclosure does not impose any specific limitation on this.

[0048] It should also be noted that Figure 2 Taking m=M as an example, it is exemplified that the memory includes M word lines 20. In practical applications, the number of word lines 20 can also be any integer greater than M, and the present disclosure does not make any specific limitation on this.

[0049] Figure 3 A schematic diagram of a refresh circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 3As shown, the refresh circuit 100 includes an address generation module 110 and an address decoding module 120. The input end of the address generation module 110 receives a refresh command. The address output end of the address generation module 110 is connected to the address input end of the address decoding module 120, and the word line control output end of the address generation module 110 is connected to the control end of the address decoding module 120.

[0050] The address generation module 110 is configured to generate an address signal and determine a word line control signal according to the refresh command. The address decoding module 120 is configured to determine M address selection signals according to the address signal and the word line control signal. Among them, each address selection signal includes a module address selection signal and a row address selection signal. The M module address selection signals correspond to the M storage modules 10 one by one, and the M row address selection signals correspond to the M word lines 20 one by one.

[0051] Exemplarily, as Figure 3 shown, the address generation module 110 includes a command decoder 111, a word line control signal generator 112, and an internal counter 113. Among them, the output end of the command decoder 111 is connected to the input end of the word line control signal generator 112 and the input end of the internal counter 113. The output end of the internal counter 113 is connected to the address input end of the address decoding module 120, and the output end of the word line control signal generator 112 is connected to the control end of the address decoding module 120.

[0052] When the memory needs to be refreshed, a refresh command is generated. The command decoder 111 can receive the refresh command and respond to it, decoding and generating an internal refresh command. The word line control signal generator 112 pulls up the word line control signal according to the internal refresh command. At the same time, the internal counter 113 generates an address signal according to the internal refresh command, as Figure 4 shown, Figure 4 is a working timing diagram of a refresh circuit provided by an embodiment of the present disclosure.

[0053] For example, if the address signal is A<12:0>=0000000000000, the address signal A<12:0> includes thirteen address sub-signals, namely the first address sub-signal A<0>, the second address sub-signal A<1>, the third address sub-signal A<2>, the fourth address sub-signal A<3>, the fifth address sub-signal A<4>, the sixth address sub-signal A<5>, the seventh address sub-signal A<6>, the eighth address sub-signal A<7>, the ninth address sub-signal A<8>, the tenth address sub-signal A<9>, the eleventh address sub-signal A<10>, the twelfth address sub-signal A<11>, and the thirteenth address sub-signal A<12>.

[0054] The internal counter 113 includes thirteen output terminals, namely the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal, the sixth output terminal, the seventh output terminal, the eighth output terminal, the ninth output terminal, the tenth output terminal, the eleventh output terminal, the twelfth output terminal, and the thirteenth output terminal. Among them, the first output terminal outputs the first address sub-signal A<0>, the second output terminal outputs the second address sub-signal A<1>, the third output terminal outputs the third address sub-signal A<2>, the fourth output terminal outputs the fourth address sub-signal A<3>, the fifth output terminal outputs the fifth address sub-signal A<4>, the sixth output terminal outputs the sixth address sub-signal A<5>, the seventh output terminal outputs the seventh address sub-signal A<6>, the eighth output terminal outputs the eighth address sub-signal A<7>, the ninth output terminal outputs the ninth address sub-signal A<8>, the tenth output terminal outputs the tenth address sub-signal A<9>, the eleventh output terminal outputs the eleventh address sub-signal A<10>, the twelfth output terminal outputs the twelfth address sub-signal A<11>, and the thirteenth output terminal outputs the thirteenth address sub-signal A<12>.

[0055] Among them, the address signal includes a module address signal and a row address signal. The module address signal includes N module address sub-signals. The N module address sub-signals can be the high N-bit address sub-signals in the address signal, and the row address signal can be the remaining address sub-signals in the address signal.

[0056] For example, based on the above embodiment, when N = 2, the module address signal includes a first module address sub-signal and a second module address sub-signal. The thirteenth address sub-signal A<12> can be used as the second module address sub-signal, and the twelfth address sub-signal A<11> can be used as the first module address sub-signal. Then the module address signal A<12,11>=00, and the row address signal A<10:0>=00000000000.

[0057] Continue to refer to Figure 3 , the address decoding module 120 includes a combinational logic unit 121 and an address latch unit 122. The address input terminal of the combinational logic unit 121 is connected to the address output terminal of the address generation module 110. The address output terminal of the combinational logic unit 121 is connected to the address input terminal of the address latch unit 122. The control terminal of the address latch unit 122 is connected to the word line control output terminal of the address generation module 110. The first level input terminal of the combinational logic unit 121 is connected to a high level, and the second level input terminal of the combinational logic unit 121 is connected to a low level.

[0058] Exemplarily, such as Figure 3As shown, the combinational logic unit 121 includes M logic units 1211. The N address input terminals of each logic unit 1211 are connected in one-to-one correspondence with N module address sub-signals. The first level input terminal of the logic unit 1211 is connected to a high level or a low level, the second level input terminal of the logic unit 1211 is connected to a high level or a low level, and the output terminal of the logic unit 1211 is connected to the address input terminal of the address latch unit 122.

[0059] For example, as Figure 3 shown, the combinational logic unit 121 includes four logic units 1211, namely the first logic unit 1211a, the second logic unit 1211b, the third logic unit 1211c, and the fourth logic unit 1211d. Among them, the first level input terminal and the second level input terminal of the first logic unit 1211a are connected to a low level. The first address input terminal of the first logic unit 1211a is connected to the first module address sub-signal, the second address input terminal of the first logic unit 1211a is connected to the second module address sub-signal, and the output terminal of the first logic unit 1211a is connected to the first address input terminal of the address latch unit 122.

[0060] The first level input terminal of the second logic unit 1211b is connected to a low level, the second level input terminal of the second logic unit 1211b is connected to a high level, the first address input terminal of the second logic unit 1211b is connected to the first module address sub-signal, the second address input terminal of the second logic unit 1211b is connected to the second module address sub-signal, and the output terminal of the second logic unit 1211b is connected to the second address input terminal of the address latch unit 122.

[0061] The first level input terminal of the third logic unit 1211c is connected to a high level, the second level input terminal of the third logic unit 1211c is connected to a low level, the first address input terminal of the third logic unit 1211c is connected to the first module address sub-signal, the second address input terminal of the third logic unit 1211c is connected to the second module address sub-signal, and the output terminal of the third logic unit 1211c is connected to the third address input terminal of the address latch unit 122.

[0062] The first level input terminal and the second level input terminal of the fourth logic unit 1211d are connected to a high level. The first address input terminal of the fourth logic unit 1211d is connected to the first module address sub-signal, the second address input terminal of the fourth logic unit 1211d is connected to the second module address sub-signal, and the output terminal of the fourth logic unit 1211d is connected to the fourth address input terminal of the address latch unit 122.

[0063] Based on the above embodiments, the first logic unit 1211a may perform a logical operation on the first module address sub-signal A<11> and a low level to obtain a low level, so as to force the output of the first module address sub-signal A<11> to be a low level, perform a logical operation on the second module address sub-signal A<12> and a low level to obtain a low level, so as to force the output of the second module address sub-signal A<12> to be a low level, and then the obtained first module address selection signal AS1<12,11>=00.

[0064] The first logic unit 1211a may also determine the first row address selection signal AS1<10:0> according to the row address signal A<10:0>. For example, the first logic unit 1211a determines the row address signal A<10:0> as the first row address selection signal AS1<10:0>, so as to obtain the first address selection signal AS1<12:0>.

[0065] The second logic unit 1211b may perform a logical operation on the first module address sub-signal A<11> and a high level to obtain a high level, so as to force the output of the first module address sub-signal A<11> to be a high level, perform a logical operation on the second module address sub-signal A<12> and a low level to obtain a low level, so as to force the output of the second module address sub-signal A<12> to be a low level, and then the obtained second module address selection signal AS2<12,11>=01.

[0066] The second logic unit 1211b may also determine the second row address selection signal AS2<10:0> according to the row address signal A<10:0>. The second row address selection signal AS2<10:0> is different from the first row address selection signal AS1<10:0>. For example, the second logic unit 1211b adds 1 to the row address signal A<10:0> and then determines it as the second row address selection signal AS2<10:0>, so as to obtain the second address selection signal AS2<12:0>.

[0067] The third logic unit 1211c may perform a logical operation on the first module address sub-signal A<11> and a low level to obtain a low level, so as to force the output of the first module address sub-signal A<11> to be a low level, perform a logical operation on the second module address sub-signal A<12> and a high level to obtain a high level, so as to force the output of the second module address sub-signal A<12> to be a high level, and then the obtained third module address selection signal AS3<12,11>=10.

[0068] The third logic unit 1211c can also determine a third row address selection signal AS3<10:0> according to the row address signal A<10:0>. The third row address selection signal AS3<10:0> is different from both the second row address selection signal AS2<10:0> and the first row address selection signal AS1<10:0>. For example, the third logic unit 1211c adds 2 to the row address signal A<10:0> to determine it as the third row address selection signal AS3<10:0>, so as to obtain a third address selection signal AS3<12:0>.

[0069] The fourth logic unit 1211d can perform a logical operation on the first module address sub-signal A<11> and a high level to obtain a high level, so as to force the output of the first module address sub-signal A<11> to be high. It performs a logical operation on the second module address sub-signal A<12> and a high level to obtain a high level, so as to force the output of the second module address sub-signal A<12> to be high. Then, the obtained fourth module address selection signal AS4<12,11>=11.

[0070] The fourth logic unit 1211d can also determine a fourth row address selection signal AS4<10:0> according to the row address signal A<10:0>. The fourth row address selection signal AS4<10:0> is different from the third row address selection signal AS3<10:0>, the second row address selection signal AS2<10:0>, and the first row address selection signal AS1<10:0>. For example, the fourth logic unit 1211d adds 3 to the row address signal A<10:0> to determine it as the fourth row address selection signal AS4<10:0>, so as to obtain a fourth address selection signal AS4<12:0>.

[0071] It should be noted that Figure 3 only taking N = 2 as an example, the combinational logic unit 121 is exemplarily shown to include 2 2 logic units 1211. In practical applications, the number of logic units 1211 can also be 2 1 、2 3 or 2 N , where N is any integer greater than 3, and the present disclosure does not make specific limitations thereon.

[0072] In this way, each logic unit 1211 can force the output of N module address sub-signals to be high level or low level respectively to obtain a module address selection signal. Then, the combinational logic unit 121 can determine M module address selection signals according to the module address signals in the address signal.

[0073] Each logic unit 1211 can also determine a row address selection signal according to the row address signal. Then, the combinational logic unit 121 can determine M row address selection signals according to the row address signals in the address signal.

[0074] Continue to see Figure 3 The address latch unit 122 includes M address latches 1221 , the address input ends of the M address latches 1221 are connected to the output ends of the M logic units 1211 in a one-to-one correspondence, and the control ends of the M address latches 1221 are all connected to the word line control output end of the address generation module 110 .

[0075] For example, Figure 3 As shown, the address latch unit 122 includes four address latches 1221, namely a first address latch 1221a, a second address latch 1221b, a third address latch 1221c and a fourth address latch 1221d, and the control end of the first address latch 1221a, the control end of the second address latch 1221b, the control end of the third address latch 1221c and the control end of the fourth address latch 1221d receive word line control signals.

[0076] The address input end of the first address latch 1221a is connected to the output end of the first logic unit 1211a, the address input end of the second address latch 1221b is connected to the output end of the second logic unit 1211b, the address input end of the third address latch 1221c is connected to the output end of the third logic unit 1211c, and the address input end of the fourth address latch 1221d is connected to the output end of the fourth logic unit 1211d.

[0077] During the refresh operation, the word line control signal received by the first address latch 1221a, the second address latch 1221b, the third address latch 1221c and the fourth address latch 1221d is a high level. Under the effect of the high level, the first address latch 1221a outputs the first address selection signal AS1<12:0>, the second address latch 1221b outputs the second address selection signal AS2<12:0>, the third address latch 1221c outputs the third address selection signal AS3<12:0>, and the fourth address latch 1221d outputs the fourth address selection signal AS4<12:0>.

[0078] It should be noted that Figure 3 Taking N=2 as an example, the address latch unit 122 includes 2 2 In practical applications, the number of address latches 1221 can also be 2. 1 , 2 3 or 2 N , N is any integer greater than 3, and the present disclosure does not impose any specific limitation on this.

[0079] Thus, each address latch 1221 can output an address selection signal when the word line control signal is at a high level. Then, the address latch unit 122 can output M address selection signals when the word line control signal is at a high level.

[0080] In summary, the module address selection signals among the address selection signals correspond to different memory modules 10, the M address selection signals correspond to M memory modules 10, the row address selection signals among the address selection signals correspond to different word lines 20, the M address selection signals also correspond to M word lines 20. Then, the M address selection signals correspond to M different word lines 20 of all memory modules 10, and can simultaneously turn on the different word lines 20 of all memory modules 10, which can reduce the voltage drop on the word lines 20 and shorten the operation duration of the word lines 20, thereby improving the success rate of memory refreshing and further improving the stability of the memory.

[0081] In some embodiments, the combinational logic unit 121 is configured to determine M module address selection signals according to the module address signals in the address signals. The address latch unit 122 is configured to determine M row address selection signals according to the row address signals; and output M address selection signals when the word line control signal is at a high level.

[0082] Exemplarily, as Figure 3 shown, the first logic unit 1211a can update the module address signal in the address signal to the first module address selection signal AS1<12,11>, and transmit the updated address signal to the first address register 1221a. The first address register 1221a can determine the first row address selection signal AS1<10:0> according to the row address signal A<10:0>. For example, the first address register 1221a determines the row address signal A<10:0> as the first row address selection signal AS1<10:0> to obtain the first address selection signal AS1<12:0>, and outputs the first address selection signal AS1<12:0> under the action of a high level.

[0083] The second logic unit 1211b can update the module address signal in the address signal to a second module address selection signal AS2<12,11>, and transmit the updated address signal to the second address register 1221b. The second address register 1221b can determine a second row address selection signal AS2<10:0> according to the row address signal A<10:0>. The second row address selection signal AS2<10:0> is different from the first row address selection signal AS1<10:0>. For example, the second logic unit 1211b adds 1 to the row address signal A<10:0> to determine the second row address selection signal AS2<10:0>, so as to obtain a second address selection signal AS2<12:0>, and outputs the second address selection signal AS2<12:0> under the action of a high level.

[0084] The third logic unit 1211c can update the module address signal in the address signal to a third module address selection signal AS3<12,11>, and transmit the updated address signal to the third address register 1221c. The third address register 1221c can determine a third row address selection signal AS3<10:0> according to the row address signal A<10:0>. The third row address selection signal AS3<10:0> is different from both the second row address selection signal AS2<10:0> and the first row address selection signal AS1<10:0>. For example, the third logic unit 1211c adds 2 to the row address signal A<10:0> to determine the third row address selection signal AS3<10:0>, so as to obtain a third address selection signal AS3<12:0>, and outputs the third address selection signal AS3<12:0> under the action of a high level.

[0085] The fourth logic unit 1211d can update the module address signal in the address signal to a fourth module address selection signal AS4<12,11>, and transmit the updated address signal to the fourth address register 1221d. The fourth address register 1221d can determine a fourth row address selection signal AS4<10:0> according to the row address signal A<10:0>. The fourth row address selection signal AS4<10:0> is different from the third row address selection signal AS3<10:0>, the second row address selection signal AS2<10:0>, and the first row address selection signal AS1<10:0>. For example, the fourth logic unit 1211d adds 3 to the row address signal A<10:0> to determine the fourth row address selection signal AS4<10:0>, so as to obtain a fourth address selection signal AS4<12:0>, and outputs the fourth address selection signal AS4<12:0> under the action of a high level.

[0086] In some embodiments, Figure 5 is a circuit schematic diagram of an address decoding module provided by an embodiment of the present disclosure, as Figure 5As shown, each logic unit 1211 includes N exclusive-OR gates XOR and 2N inverters INV. In each logic unit 1211, the two input terminals of each exclusive-OR gate XOR are respectively and correspondingly connected to the output terminals of two inverters INV. The input terminals of N inverters INV are respectively and correspondingly connected to N module address sub-signals. The input terminals of the other N inverters INV are connected to a high level or a low level. The output terminal of the exclusive-OR gate XOR is connected to the address input terminal of the address latch unit 122.

[0087] Exemplarily, as Figure 5 shown, each logic unit 1211 includes two exclusive-OR gates XOR and four inverters INV. The two exclusive-OR gates XOR are respectively the first exclusive-OR gate XOR1 and the second exclusive-OR gate XOR2. The four inverters INV are respectively the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4.

[0088] The input terminal of the first inverter INV1 is connected to the first module address sub-signal A<11>. The output terminal of the first inverter INV1 is connected to the first input terminal of the first exclusive-OR gate XOR1. The input terminal of the second inverter INV2 is connected to a high level or a low level. The output terminal of the second inverter INV2 is connected to the second input terminal of the first exclusive-OR gate XOR1. The input terminal of the third inverter INV3 is connected to the second module address sub-signal A<12>. The output terminal of the third inverter INV3 is connected to the first input terminal of the second exclusive-OR gate XOR2. The input terminal of the fourth inverter INV4 is connected to a high level or a low level. The output terminal of the fourth inverter INV4 is connected to the second input terminal of the second exclusive-OR gate XOR2. The output terminals of the first exclusive-OR gate XOR1 and the second exclusive-OR gate XOR2 are connected to the address input terminal of the address latch unit 122.

[0089] Each first inverter INV1 can invert the first module address sub-signal A<11> to obtain the inverted signal of the first module address sub-signal A<11>. Each third inverter INV3 can invert the second module address sub-signal A<12> to obtain the inverted signal of the second module address sub-signal A<12>. Based on the above embodiments, if the first module address sub-signal A<11>=0 and the second module address sub-signal A<12>=0, then the inverted signal of the first module address sub-signal A<11> is a high level, and the inverted signal of the second module address sub-signal A<12> is a high level.

[0090] For example, as Figure 5As shown, in the first logic unit 1211a, the input terminals of the second inverter INV2 and the fourth inverter INV4 are connected to a low level. Both the second inverter INV2 and the fourth inverter INV4 can invert the low level to a high level. The first exclusive-OR gate XOR1 can perform an exclusive-OR operation on the high level and the inverted signal of the first module address sub-signal A<11> to obtain a low level. The second exclusive-OR gate XOR2 can perform an exclusive-OR operation on the high level and the inverted signal of the second module address sub-signal A<12> to obtain a low level, that is, the first module address selection signal AS1<12,11> = 00.

[0091] In the second logic unit 1211b, the input terminal of the second inverter INV2 is connected to a high level. The second inverter INV2 can invert the high level to a low level. The input terminal of the fourth inverter INV4 is connected to a low level. The fourth inverter INV4 can invert the low level to a high level. The first exclusive-OR gate XOR1 can perform an exclusive-OR operation on the low level and the inverted signal of the first module address sub-signal A<11> to obtain a high level. The second exclusive-OR gate XOR2 can perform an exclusive-OR operation on the high level and the inverted signal of the second module address sub-signal A<12> to obtain a low level, that is, the second module address selection signal AS2<12,11> = 01.

[0092] In the third logic unit 1211c, the input terminal of the second inverter INV2 is connected to a low level. The second inverter INV2 can invert the low level to a high level. The input terminal of the fourth inverter INV4 is connected to a high level. The fourth inverter INV4 can invert the high level to a low level. The first exclusive-OR gate XOR1 can perform an exclusive-OR operation on the high level and the inverted signal of the first module address sub-signal A<11> to obtain a low level. The second exclusive-OR gate XOR2 can perform an exclusive-OR operation on the low level and the inverted signal of the second module address sub-signal A<12> to obtain a high level, that is, the third module address selection signal AS3<12,11> = 10.

[0093] In the fourth logic unit 1211d, the input terminals of the second inverter INV2 and the fourth inverter INV4 are connected to a high level. Both the second inverter INV2 and the fourth inverter INV4 can invert the high level to a low level. The first exclusive-OR gate XOR1 can perform an exclusive-OR operation on the low level and the inverted signal of the first module address sub-signal A<11> to obtain a high level. The second exclusive-OR gate XOR2 can perform an exclusive-OR operation on the low level and the inverted signal of the second module address sub-signal A<12> to obtain a high level, that is, the fourth module address selection signal AS4<12,11> = 11.

[0094] It should be noted that Figure 5 Taking N = 2 as an example only, it exemplarily shows that each logic unit 1211 includes 2 exclusive-OR gates XOR and 2 There are 2 inverters INV. In practical applications, the number of exclusive-OR gates XOR in each logic unit 1211 can also be 1, 3, or any integer greater than 3. Correspondingly, the number of inverters INV is twice the number of exclusive-OR gates XOR. The present disclosure does not make specific limitations on this.

[0095] The present disclosure also provides a refreshing method, which is applied to the refreshing circuit 100 provided in any of the above embodiments.

[0096] Figure 6 It is a schematic flowchart of a refreshing method provided by an embodiment of the present disclosure. As Figure 6 shown, the specific steps of the refreshing method include:

[0097] S101, generate an address signal and determine a word line control signal according to a refresh command.

[0098] Exemplarily, when the memory needs to be refreshed, a refresh command is generated. The command decoder decodes the refresh command to generate an internal refresh command. The word line control signal generator pulls up the word line control signal according to the internal refresh command. At the same time, the internal counter generates an address signal according to the internal refresh command.

[0099] Among them, the address signal includes a module address signal and a row address signal. The module address signal includes N module address sub-signals. The N module address sub-signals can be the high N-bit address sub-signals in the address signal. Then the row address signal can be the remaining address sub-signals in the address signal. For example, for the address signal A<12:0>=0000000000000, when N = 2, the module address signal includes a first module address sub-signal and a second module address sub-signal. The thirteenth address sub-signal A<12> can be used as the second module address sub-signal, and the twelfth address sub-signal A<11> can be used as the first module address sub-signal. Then the module address signal A<12,11>=00, and the row address signal A<10:0>=0000000000.

[0100] S102, determine M address selection signals according to the address signal and the word line control signal.

[0101] Among them, each address selection signal includes a module address selection signal and a row address selection signal. The M module address selection signals correspond to M storage modules one by one, and the M row address selection signals correspond to M word lines one by one.

[0102] Exemplarily, the combinational logic unit can determine M module address selection signals according to the module address signal in the address signal, and determine M row address selection signals according to the row address signal in the address signal. The address latch unit outputs M address selection signals when the word line control signal is at a high level.

[0103] For example, the combinational logic unit can force the N module address sub-signals to be output as high level and low level respectively to obtain M module address selection signals, and can add M different values to the row address signal to obtain M row address selection signals, so as to obtain M address selection signals. The address latch unit outputs the M address selection signals under the action of the high level.

[0104] In other embodiments, the combinational logic unit can determine M module address selection signals according to the module address signal in the address signal, and the address latch unit determines M row address selection signals according to the row address signal. When the word line control signal is at high level, the M address selection signals are output.

[0105] For example, the combinational logic unit can update the module address signal in the address signal M times to update the module address signal in the address signal to M different module address selection signals respectively. The address latch unit receives the M updated address signals, and determines M different row address selection signals according to the row address signals in the M updated address signals, so as to obtain M address selection signals, and outputs the M address selection signals under the action of the high level.

[0106] In the embodiments of the present disclosure, by generating an address signal and determining a word line control signal according to a refresh command, and determining M address selection signals according to the address signal and the word line control signal, wherein each address selection signal includes a module address selection signal and a row address selection signal, the M module address selection signals correspond to M storage modules one by one, and the M row address selection signals correspond to M word lines one by one. Thus, the M address selection signals correspond to M different word lines of all storage modules, and the different word lines of all storage modules can be opened simultaneously, which can reduce the voltage drop on the word line and shorten the operation duration of the word line, thereby improving the success rate of memory refresh and further improving the stability of the memory.

[0107] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural term is usually included. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this specification. Where the term "example" is used in this specification, the "example" is merely illustrative and should not be considered exclusive or extensive.

[0108] The above has described several embodiments of the present disclosure in detail. Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A memory refresh circuit, characterized in that: The memory includes M storage modules arranged along a first direction, each of the storage modules includes M storage units arranged along a second direction, the first direction intersects with the second direction, and the M storage units arranged along the first direction are connected to the same word line, M=2 N , N is an integer greater than zero; The refresh circuit comprises: an address generation module and an address decoding module; The address generation module is configured to generate an address signal and determine a word line control signal according to a refresh command; The address decoding module is configured to determine M address selection signals according to the address signal and the word line control signal, wherein each of the address selection signals includes a module address selection signal and a row address selection signal, the M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines; The address decoding module includes a combinational logic unit and an address latch unit; The address input end of the combinational logic unit is connected to the address output end of the address generation module, the address output end of the combinational logic unit is connected to the address input end of the address latch unit, the control end of the address latch unit is connected to the word line control output end of the address generation module, the first level input end of the combinational logic unit is connected to a high level, and the second level input end of the combinational logic unit is connected to a low level; The combinational logic unit is configured to determine the M module address selection signals according to the module address signal in the address signal, and determine the M row address selection signals according to the row address signal in the address signal; The address latch unit is configured to output M address selection signals when the word line control signal is at a high level.

2. The refresh circuit according to claim 1, characterized in that: The combinational logic unit includes M logic units, and the module address signal includes N module address sub-signals; The N address input terminals of each logic unit are connected to the N module address sub-signals in a one-to-one correspondence, the first level input terminal of the logic unit is connected to a high level or a low level, the second level input terminal of the logic unit is connected to a high level or a low level, and the output terminal of the logic unit is connected to the address input terminal of the address latch unit; Each of the logic units is configured to force the N module address sub-signals to be output as a high level or a low level to obtain one module address selection signal.

3. The refresh circuit according to claim 2, characterized in that: The combinational logic unit includes a first logic unit, a second logic unit, a third logic unit and a fourth logic unit, and the module address signal includes a first module address sub-signal and a second module address sub-signal; The first level input terminal and the second level input terminal of the first logic unit are connected to a low level, the first address input terminal of the first logic unit is connected to the first module address sub-signal, the second address input terminal of the first logic unit is connected to the second module address sub-signal, and the output terminal of the first logic unit is connected to the first address input terminal of the address latch unit; The first level input terminal of the second logic unit is connected to a low level, the second level input terminal of the second logic unit is connected to a high level, the first address input terminal of the second logic unit is connected to the first module address sub-signal, the second address input terminal of the second logic unit is connected to the second module address sub-signal, and the output terminal of the second logic unit is connected to the second address input terminal of the address latch unit; The first level input terminal of the third logic unit is connected to a high level, the second level input terminal of the third logic unit is connected to a low level, the first address input terminal of the third logic unit is connected to the first module address sub-signal, the second address input terminal of the third logic unit is connected to the second module address sub-signal, and the output terminal of the third logic unit is connected to the third address input terminal of the address latch unit; The first level input terminal and the second level input terminal of the fourth logic unit are connected to a high level, the first address input terminal of the fourth logic unit is connected to the first module address sub-signal, the second address input terminal of the fourth logic unit is connected to the second module address sub-signal, and the output terminal of the fourth logic unit is connected to the fourth address input terminal of the address latch unit; The first logic unit is configured to force the first module address sub-signal and the second module address sub-signal to be output as a low level to obtain a first module address selection signal; The second logic unit is configured to force the first module address sub-signal to be output as a high level and force the second module address sub-signal to be output as a low level to obtain a second module address selection signal; The third logic unit is configured to force the first module address sub-signal to be output as a low level and force the second module address sub-signal to be output as a high level, thereby obtaining a third module address selection signal; The fourth logic unit is configured to force the first module address sub-signal and the second module address sub-signal to be output as a high level to obtain a fourth module address selection signal.

4. The refresh circuit according to claim 2, characterized in that: Each of the logic units includes N XOR gates and 2N inverters; In each of the logic units, the two input ends of each of the XOR gates are connected one-to-one with the output ends of the two inverters, the input ends of the N inverters are connected one-to-one with the N module address sub-signals, the input ends of the other N inverters are connected to a high level or a low level, and the output end of each of the XOR gates is connected to the address input end of the address latch unit.

5. The refresh circuit according to claim 4, characterized in that: Each of the logic units includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first XOR gate and a second XOR gate; The input end of the first inverter is connected to the first module address sub-signal, the output end of the first inverter is connected to the first input end of the first XOR gate, the input end of the second inverter is connected to a low level or a high level, the output end of the second inverter is connected to the second input end of the first XOR gate, the input end of the third inverter is connected to the second module address sub-signal, the output end of the third inverter is connected to the first input end of the second XOR gate, the input end of the fourth inverter is connected to a low level or a high level, the output end of the fourth inverter is connected to the second input end of the second XOR gate, and the output end of the first XOR gate and the output end of the second XOR gate are connected to the address input end of the address latch unit.

6. The refresh circuit according to claim 2, characterized in that: The address latch unit includes M address latches; The address input terminals of the M address latches are connected to the output terminals of the M logic units in a one-to-one correspondence, and the control terminals of the M address latches are all connected to the word line control output terminal of the address generation module.

7. The refresh circuit according to any one of claims 1 to 6, characterized in that: The address generation module includes a command decoder, a word line control signal generator and an internal counter; The output end of the command decoder is connected to the input end of the word line control signal generator and the input end of the internal counter, the output end of the internal counter is connected to the address input end of the address decoding module, and the output end of the word line control signal generator is connected to the control end of the address decoding module; The command decoder is configured to generate an internal refresh command in response to the received refresh command; The word line control signal generator is configured to pull up the word line control signal according to the internal refresh command; The internal counter is configured to generate the address signal according to the internal refresh command.

8. A memory refresh method, applied to the refresh circuit according to any one of claims 1 to 7, characterized in that: include: According to the refresh command, an address signal is generated and a word line control signal is determined; Determine M address selection signals according to the address signal and the word line control signal; wherein each of the address selection signals includes a module address selection signal and a row address selection signal, the M module address selection signals correspond one-to-one to the M storage modules, and the M row address selection signals correspond one-to-one to the M word lines; Determining M address selection signals according to the address signal and the word line control signal comprises: Determine M module address selection signals according to the module address signal in the address signal; Determine M row address selection signals according to the row address signal in the address signal; When the word line control signal is at a high level, M address selection signals are output.

9. A memory, characterized in that: comprising M storage modules arranged along a first direction and a refresh circuit according to any one of claims 1 to 7; Each of the storage modules includes M storage units arranged along the second direction, the first direction and the second direction intersect, and the M storage units arranged along the first direction are connected to the same word line, M=2 N , N is an integer greater than zero.

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