Semiconductor device, system for the device and method performed by the device

Abstract

The disclosure provides a semiconductor device, a system for a semiconductor device, and a method performed by a semiconductor device. The semiconductor device may include a three-dimensional NAND flash memory device having high capacity and / or high efficiency. In one aspect, a semiconductor device includes a voltage pump, a pump switch circuit configured to be coupled to the voltage pump, and an interface including a voltage pin coupled to the pump switch circuit. The voltage pump has an input, an output, and a series of pump stages coupled between the input and the output. The pump switching circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages in the series of pump stages to output a target voltage at an output of the voltage pump.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, such as power supplies in semiconductor devices. Background Art

[0002] Semiconductor devices, such as memory devices, are becoming smaller and faster. Power efficiency is a key issue for semiconductor devices, which can affect the performance of the semiconductor device and / or associated systems. Summary of the invention

[0003] The present disclosure describes methods, devices, systems and techniques for managing power supply in semiconductor devices, such as non-volatile memory devices, such as NAND flash memory devices.

[0004] One aspect of the disclosure features a semiconductor device, the semiconductor device comprising: a voltage pump having an input, an output, and a series of pump stages coupled between the input and the output; a pump switch circuit configured to be coupled to the voltage pump; and an interface including a voltage pin coupled to the pump switch circuit. The pump switch circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages in the series of pump stages to output a target voltage at the output of the voltage pump.

[0005] In some embodiments, the corresponding number is an integer equal to or greater than 0.

[0006] In some embodiments, the semiconductor device further comprises: a voltage detector; and a control circuit coupled to the voltage detector and the pump switch circuit. The voltage detector is configured to detect a value of the input voltage received at the voltage pin. The control circuit is configured to: receive the value of the input voltage from the voltage detector; and control the pump switch circuit to couple to the corresponding node in the voltage pump based on the value of the input voltage.

[0007] In some implementations, the control circuit is configured to: receive a signal indicating the target voltage; and control the pump switch circuit to couple to the corresponding node in the voltage pump based on the signal and the value of the input voltage.

[0008] In some embodiments, the target voltage is a first target voltage, and wherein the control circuit is configured to: receive a second signal indicating a second target voltage; and control the pump switch circuit to couple to a second corresponding node in the voltage pump based on the second signal and a second input voltage received at the voltage pin.

[0009] In some embodiments, the first target voltage corresponds to a first operation performed in a semiconductor device, and the second target voltage corresponds to a second operation performed in the semiconductor device, the second operation is different from the first operation, and the second target voltage is different from the first target voltage.

[0010] In some implementations, the pump switch circuit includes a transistor coupled between the voltage pin and the voltage detector.

[0011] In some embodiments, the pump switching circuit includes a switch that can be switched to couple to each of a plurality of nodes in the voltage pump, and the plurality of nodes include: a first node located between the output of the voltage pump and a first pump stage in the series of pump stages, the first pump stage being adjacent to the output of the voltage pump; and a second node located between two adjacent pump stages in the series of pump stages.

[0012] In some embodiments, the semiconductor device further includes a reference voltage circuit configured to provide a reference voltage. The control circuit is configured to calibrate the target voltage based on the reference voltage.

[0013] In some embodiments, the interface further comprises: a second voltage pin coupled to the input of the voltage pump and configured to receive a second voltage. The voltage pump is configured to generate an output voltage at the output of the voltage pump based on the series of pump stages and the second voltage. The second voltage may be a supply voltage VCC or VCCQ.

[0014] In some implementations, the voltage pump is configured to generate the target voltage at a first power efficiency, and generate the output voltage at a second power efficiency lower than the first power efficiency.

[0015] In some embodiments, the interface further includes a third voltage pin configured to receive a third voltage. The semiconductor device may further include a second voltage detector coupled to the voltage pin and configured to detect a value of the third voltage received at the third voltage pin. The control circuit may be configured to: receive the value of the third voltage from the second voltage detector; determine whether the value of the third voltage matches a predetermined voltage; and in response to determining that the value of the third voltage does not match the predetermined voltage, prohibit receiving the third voltage at the third voltage pin, and control the pump switch circuit to couple to the corresponding node in the voltage pump based on the value of the input voltage to generate the target voltage.

[0016] In some embodiments, the semiconductor device further comprises: a memory array having a memory cell array coupled to a plurality of word lines; a decoder coupled to the memory array and configured to select each of the plurality of word lines; and a switch circuit coupled between the decoder and the voltage pump and configured to: generate a set of operating voltages based on the target voltage, and output the set of operating voltages to the decoder. The decoder is configured to apply the set of operating voltages to corresponding word lines among the plurality of word lines, respectively.

[0017] In some embodiments, the input voltage is in the range of 6 volts to 10 volts.

[0018] Another aspect of the disclosure is characterized by a system, the system comprising: a memory device including a memory array having an array of memory cells coupled to a plurality of word lines; and a controller coupled to the memory device and configured to send a command to the memory device, the command instructing the memory device to perform an operation. The memory device also includes: a voltage generator including a voltage pump having an input, an output, and a series of pump stages coupled between the input and the output; a pump switch circuit configured to be coupled to the voltage pump; and an interface including a voltage pin coupled to the pump switch circuit and configured to receive an input voltage. The pump switch circuit is configured to provide the input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages in the series of pump stages to output a target voltage at the output of the voltage pump. The memory device is configured to perform the operation based on the target voltage output at the output of the voltage pump.

[0019] In some implementations, the system includes a voltage converter coupled to the memory device. The voltage converter is configured to generate the input voltage based on a reference voltage and provide the input voltage to the voltage pin.

[0020] In some implementations, the voltage converter is coupled to the controller and is configured to generate the input voltage based on a signal from the controller, the signal being associated with the command and indicative of the input voltage.

[0021] In some implementations, the voltage converter is configured to provide a voltage to the controller.

[0022] In some embodiments, the memory device further comprises: a voltage detector; and a control circuit coupled to the voltage detector and the pump switch circuit. The voltage detector is configured to detect a value of the input voltage received at the voltage pin. The control circuit is configured to: receive a signal from the controller, the signal being associated with the operation and indicating the target voltage; receive the value of the input voltage from the voltage detector; and control the pump switch circuit to couple to the corresponding node in the voltage pump based on the value of the input voltage and the signal.

[0023] In some embodiments, the target voltage is a first target voltage, and wherein the control circuit is configured to: receive a second signal from the controller, the second signal being associated with a second operation and indicating a second target voltage; and control the pump switch circuit to couple to a second corresponding node in the voltage pump based on the second signal and a second input voltage received at the voltage pin.

[0024] In some implementations, the first target voltage corresponds to a first operation performed in the memory device, and the second target voltage corresponds to a second operation performed in the memory device, the second operation being different from the first operation, and the second target voltage being different from the first target voltage.

[0025] In some embodiments, the controller is configured to send a control signal to a voltage converter to generate the second input voltage to be provided to the voltage pin.

[0026] In some embodiments, the pump switch circuit includes a switch that can be switched to couple to each of a plurality of nodes in the voltage pump, the plurality of nodes including: a first node between the output of the voltage pump and a first pumping stage in the series of pumping stages, the first pumping stage being adjacent to the output of the voltage pump; and a second node between two adjacent voltage pumping stages in the series of pumping stages.

[0027] In some implementations, the voltage generator further includes a reference voltage circuit configured to provide a reference voltage. The control circuit is coupled to the voltage generator and configured to calibrate the target voltage based on the reference voltage.

[0028] In some implementations, the interface further comprises: a second voltage pin coupled to the input of the voltage pump and configured to receive a second voltage. The voltage pump is configured to generate an output voltage at the output of the voltage pump based on the series of pumping stages and the second voltage.

[0029] In some embodiments, the interface further comprises a third voltage pin configured to receive a third voltage. The memory device further comprises a second voltage detector coupled to the voltage pin and configured to detect a value of the third voltage received at the third voltage pin. The control circuit is configured to: receive the value of the third voltage from the second voltage detector; determine whether the value of the third voltage matches a predetermined voltage associated with the target voltage; and in response to determining that the value of the third voltage does not match the predetermined voltage, prohibit receiving the third voltage at the third voltage pin, and control the pump switch circuit to couple to the corresponding node in the voltage pump based on the value of the input voltage to generate the target voltage.

[0030] In some implementations, the interface includes a plurality of additional voltage pins including the voltage pin, and the memory device includes a plurality of voltage pumps, and wherein each of the plurality of additional voltage pins is coupled to a corresponding voltage pump of the plurality of voltage pumps.

[0031] In some embodiments, the system further includes: a column decoder coupled to the memory array and configured to select each of the plurality of word lines; and a switch circuit coupled between the column decoder and the voltage generator, wherein the switch circuit is configured to: generate a set of operating voltages based on the target voltage, and output the set of operating voltages to the column decoder. The column decoder is configured to apply the set of operating voltages to corresponding word lines of the plurality of word lines, respectively, and the memory device is configured to perform the operation on the corresponding word line based on the set of operating voltages.

[0032] Another aspect of the present disclosure is characterized by a method performed by a semiconductor device, the method comprising: receiving a command to perform an operation in the semiconductor device; receiving a signal indicating a target voltage associated with the operation; detecting a value of an input voltage at a voltage pin of the semiconductor device, wherein the semiconductor device includes a pump switch circuit coupled to the voltage pin; based on the value of the input voltage and the signal indicating the target voltage, controlling the pump switch circuit to couple to a corresponding node in a voltage pump of the semiconductor device, wherein the voltage pump includes an input, an output, and a series of pump stages coupled between the input and the output; generating the target voltage at the output of the voltage pump using a corresponding number of pump stages coupled between the corresponding node and the output; and performing the operation based on the target voltage.

[0033] In some embodiments, the method further includes: receiving a second input voltage from a second voltage pin; determining whether the second input voltage matches a predetermined voltage associated with the target voltage; and in response to determining that the second input voltage does not match the predetermined voltage, prohibiting the second input voltage from being received by the semiconductor device. Controlling the pump switch circuit to couple to the corresponding node in the voltage pump may be performed in response to determining that the second input voltage does not match the predetermined voltage.

[0034] Implementations of the above technology include methods, systems, circuits, computer programs, and computer-readable media. In one example, a method may include the above actions. In another example, one such computer program is suitably implemented in a non-transitory machine-readable medium storing instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above actions. One such computer-readable medium stores instructions that are configured to cause the one or more processors to perform the above actions when executed by one or more processors.

[0035] The details of one or more disclosed embodiments are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from a review of the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram illustrating an example system.

[0037] Figure 2 is a schematic diagram illustrating an example memory device.

[0038] Figure 3 is a schematic diagram illustrating an example circuit system including an example voltage pump and an example pump switching circuit.

[0039] Figure 4 is a schematic diagram illustrating another example memory device.

[0040] Figure 5 is a flow chart of an example process for managing power supply between a controller and a semiconductor device.

[0041] The same reference numbers and designations indicate the same elements in the various drawings. It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale.

[0042] Description of reference numerals:

[0043] 100: System

[0044] 110: Installation

[0045] 112: Device controller

[0046] 113: Processor

[0047] 114: Internal memory

[0048] 116: Memory

[0049] 120: Host device

[0050] 122: Host controller

[0051] 130: Voltage Converter

[0052] 140, 220: High voltage generator

[0053] 200, 400: Memory device

[0054] 202: Memory interface / I / O terminal

[0055] 202a, 202b, 401, 402: Pins

[0056] 202c: Additional pins / pins

[0057] 204: Control Logic

[0058] 206: X decoder / column decoder

[0059] 208: Switching Circuit

[0060] 210: Storage Array

[0061] 222, 310: Voltage pump

[0062] 224: Reference voltage circuit

[0063] 230: Internal Detector

[0064] 240, 330: Pump switch circuit

[0065] 250, 320: Pin detector

[0066] 300: Circuit System

[0067] 311: Input

[0068] 312-1, 312-2, 312-m, 312-n: Pump stage

[0069] 313: Output

[0070] 315-0, 315-1, 315-2, 315-m: Node

[0071] 331: Additional voltage pin / pins

[0072] 332: Transistor

[0073] 334: Gate Controller

[0074] 336: Switch

[0075] 340: Control circuit

[0076] 403a, 403b: Additional voltage pin / pins

[0077] 410: Memory chip

[0078] 500: Process

[0079] 502, 504, 506, 510, 512: Steps

[0080] 508: Error ID

[0081] V ADD : Input voltage / additional voltage

[0082] V ADD1 、V ADD2 : Additional voltage

[0083] VCC, VCCQ: supply voltage / second voltage / voltage

[0084] V IN : Input voltage

[0085] V OUT : Output voltage

[0086] VPP: Programming voltage / Erase voltage / Operation voltage / Third voltage / Voltage DETAILED DESCRIPTION

[0087] Embodiments of the present disclosure provide a technique for managing power supply in a semiconductor device, such as a non-volatile memory device (such as a NAND flash memory device). The technique can provide efficient power supply for a semiconductor device (such as a memory device) to improve the performance of a system including the semiconductor device (such as a solid-state drive (SSD) system).

[0088] In some embodiments, a semiconductor device includes a voltage pump configured to pump a fixed (or stable) voltage (e.g., a supply voltage (e.g., VDD or VCC / VCCQ)) received at an input and generate an output voltage at an output based on the fixed voltage. The voltage pump includes a series of pumping stages coupled between the input and the output. The pump efficiency using the series of pumping stages may be low (e.g., 20% to 30%), and more than half of the power supply in the system may be used for the voltage pump (e.g., to provide voltage to word lines through switches or regulators of a memory array). The technology can reduce or minimize the pump power consumption of the semiconductor device, for example, by reducing the number of pumping stages used in the voltage pump, thereby improving the pump efficiency. For example, the technology can use an additional voltage pin to provide a different power supply level (e.g., an additional voltage higher than the supply voltage) to the voltage pump to generate a target voltage using zero or a small number of pumping stages (e.g., 1, 2, ...) in the voltage pump.

[0089] The technology can also provide different power supply levels for different operations (e.g., reading, programming and / or erasing), which can further reduce power consumption and improve the performance of semiconductor devices and systems. With efficient power consumption, the technology can increase the number of memory chips that can be operated simultaneously and improve the performance of the system.

[0090] In some embodiments, a voltage converter (e.g., a direct current-direct current (DC-DC) converter) is configured to generate one or more desired voltages (e.g., 1.2 volts, 3 volts, 6 volts, or 8 volts) based on a fixed voltage (e.g., 12 volts). The voltage converter may be off-die, for example, separate from the semiconductor device and / or a controller coupled to the semiconductor device. The voltage converter may have a conversion efficiency that is higher than the pump efficiency using the series of pump stages. In some examples, the conversion efficiency of the voltage converter is as high as 90% or greater. The voltage converter may generate a desired voltage (e.g., based on a command from a controller) and provide the desired voltage to an additional voltage pin coupled to a voltage pump. Using the desired voltage, the semiconductor device may reduce or minimize the use of pump stages in the voltage pump, for example, by directly providing the desired voltage at the output of the voltage pump or by using a small number of pump stages (e.g., 1, 2, or any suitable number) to provide the target voltage.

[0091] In some embodiments, a semiconductor device includes one or more voltage pins, the one or more voltage pins including a voltage pin for a VDD or VCC / VCCQ voltage input (e.g., a fixed voltage or a stable voltage (e.g., 1.3 volts or 3 volts)) and a voltage pin for a VPP voltage input (e.g., varying in a range between 10.5 volts and 13.5 volts). The additional voltage pin for the desired voltage may be different from the voltage pins for VDD or VCC / VCCQ and VPP. The additional voltage pin may be coupled to a voltage pump through a power switch circuit, which may be configured to couple to a corresponding node based on the desired voltage at the additional voltage pin and a target voltage to select a corresponding number of pump stages. In some embodiments, the semiconductor device includes a voltage detector, which is configured to detect a voltage level at the voltage pin for the VPP voltage input. If the voltage level does not match the target voltage, the semiconductor device may disable power input at the voltage pin for the VPP voltage input, and configure the power switch circuit to receive power from the additional voltage pin, and select a corresponding number of pump stages in the voltage pump to provide the target voltage. The term "match" may mean "identical" or a difference within a threshold value (eg, 1%, 5%, or 10%, or a suitable percentage).

[0092] In some embodiments, the semiconductor device includes two or more additional voltage pins, which can be respectively coupled to two or more voltage pumps (for example, through corresponding power switching circuits) that can provide more different voltages for different operations in the semiconductor device, thereby improving the power efficiency of the semiconductor device and the performance of the semiconductor device.

[0093] The technology may be implemented using various interfaces or protocols, such as a Serial Peripheral Interface (“SPI”), such as a single-bit SPI or a multi-bit SPI, or a Quad Peripheral Interface (“QPI”). The technology may be applied to various types of semiconductor devices, such as non-volatile memory devices (such as NAND flash memory devices, NOR flash memory devices, resistive random-access memory (RRAM) devices, phase-change random-access memory (PCRAM) devices, etc.). The technology may be applied to various memory types, such as a single-level cell (SLC) device, a multi-level cell (MLC) device (like a 2-level cell device), a triple-level cell (TLC) device, a quad-level cell (QLC) device, or a penta-level cell (PLC) device. Additionally or alternatively, the technology may be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSD), embedded systems, etc. For illustrative purposes, in the present disclosure, a memory device is described as an example of a semiconductor device. A power supply refers to a power supply supplied to a semiconductor device or a component in a semiconductor device. A voltage is described as an example of a power supply.

[0094] Figure 1 1 is a schematic diagram showing an exemplary system 100. System 100 includes a device 110 and a host device 120. Device 110 includes a device controller 112 and a memory 116. Device controller 112 includes a processor 113 and an internal memory 114. In some embodiments, device 110 includes a plurality of memories 116 coupled to device controller 112. Memory 116 includes a plurality of blocks. Memory 116 may be a two-dimensional memory including two-dimensional (2D) memory blocks. Memory 116 may also be a 3D memory including three-dimensional (3D) memory blocks. Memory 116 may be a semiconductor device and formed on a semiconductor substrate (e.g., a silicon wafer).

[0095] The host device 120 includes a host controller 122 , which may include at least one processor and at least one memory coupled to the at least one processor and storing programming instructions executed by the at least one processor to perform one or more corresponding operations.

[0096] In some embodiments, device 110 is a storage device. For example, device 110 may be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid state drive (SSD), or some other suitable storage. In some embodiments, device 110 is a smart watch, a digital camera, or a media player. In some embodiments, device 110 is a client device coupled to host device 120. For example, device 110 is an SD card in a digital camera or a media player as host device 120.

[0097] Device controller 112 is a general purpose microprocessor or an application specific microcontroller. In some implementations, device controller 112 is a memory controller of device 110. The following section describes various techniques based on implementations in which device controller 112 is a memory controller. However, the techniques described in the following section are also applicable to implementations in which device controller 112 is another type of controller other than a memory controller.

[0098] The processor 113 is configured to execute instructions and process data. The instructions include firmware instructions and / or other program instructions stored in a secondary memory as firmware code and / or other program code, respectively. The data includes program data corresponding to the firmware and / or other programs executed by the processor and other suitable data. In some embodiments, the processor 113 is a general-purpose microprocessor or an application-specific microcontroller.

[0099] The processor 113 accesses instructions and data from the internal memory 114. In some embodiments, the internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when the device 110 is an eMMC, an SD card, or a smart watch, the internal memory 114 is an SRAM. In some embodiments, when the device 110 is a digital camera or a media player, the internal memory 114 is a DRAM.

[0100] In some embodiments, the internal memory is a cache memory included in the device controller 112, such as Figure 1The internal memory 114 stores instruction codes corresponding to instructions executed by the processor 113 and / or data requested by the processor 113 during runtime. The device controller 112 transfers the instruction codes and / or data from the memory 116 to the internal memory 114 .

[0101] In some embodiments, the memory 116 is a non-volatile memory configured for long-term storage of instructions and / or data, such as a NAND flash memory device or a NOR flash memory device, or some other suitable non-volatile memory device. The memory 116 may include one or more memory chips. In embodiments where the memory 116 is a NAND flash memory, the device 110 is a flash memory device (e.g., a flash memory card), and the device controller 112 is a NAND flash memory controller. For example, in some embodiments, when the device 110 is an eMMC or an SD card, the memory 116 is a NAND flash memory; in some embodiments, when the device 110 is a digital camera, the memory 116 is an SD card; and in some embodiments, when the device 110 is a media player, the memory 116 is a hard disk. In some embodiments where the memory 116 is a NOR flash memory, the device 110 may optionally include the device controller 112. In some cases, the device 110 may not include a device controller, and the memory 116 may communicate directly with the host device 120.

[0102] In some embodiments, the system includes a controller and a semiconductor device. The controller can be coupled to the semiconductor device via an electrical connection (e.g., electrical wiring, pins, or bus) or a wireless connection, and can communicate directly with the semiconductor device, for example. The controller can be Figure 1 The host controller 122 or Figure 1 The semiconductor device may be implemented as a device controller 112. Figure 1 The memory 116 is shown. The semiconductor device may also be Figure 2 The memory device 200 is further described in detail in FIG.

[0103] In some embodiments, the device 110 is supplied with a fixed total power supply (e.g., 25 volts). Embodiments in the present disclosure provide techniques for efficiently managing power consumption in the device 110, which may be critical to the performance of the device 110. In some embodiments, the device 110 includes a voltage converter 130, which is configured to convert a fixed (or stable) voltage (e.g., 12 volts), for example based on a command from the device controller 112, to generate different voltages for different purposes / uses. The voltage converter 130 may have a high conversion efficiency, for example, up to 90% or greater than 90%. The voltage converter 130 may be integrated on a board of the device 110. The voltage converter 130 may be separate from the memory 116, which may include one or more dies or memory chips. That is, the voltage converter 130 may be off-die. In some embodiments, the voltage converter 130 is arranged to be located outside the device controller 112, for example, as Figure 1 In some implementations, the voltage converter 130 is integrated into the device controller 112 .

[0104] In some examples, the voltage converter 130 generates an operating voltage (e.g., 1.2 volts) to be provided to the device controller 112. In some examples, the voltage converter 130 generates, for example, VDD (e.g., 3 volts or 1.3 volts), VCC / VCCQ (e.g., 3 volts or 1.3 volts), VPP (e.g., 10.5 volts to 13.5 volts), and / or one or more additional voltage levels (e.g., 6 volts or 8 volts) to be provided to the memory 116 via voltage pins (as described in further detail below). VPP may represent a programming or erase voltage. VCC / VCCQ may represent a higher voltage relative to ground (GND). VDD may represent a fixed (or stable) voltage supply and may be used interchangeably with VCC. The memory 116 may include a high voltage (HV) generator 140 that may receive one or more voltages from the voltage converter 130 and generate one or more corresponding voltages to be provided to the memory 116 for performing one or more corresponding operations.

[0105] Figure 2 2 is a schematic diagram showing an exemplary memory device 200. The memory device 200 may be implemented as Figure 1 The memory 116 is shown. Figure 2 As shown in , the memory device 200 includes a plurality of components that can be integrated onto a board such as a silicon based carrier and packaged. The memory device 200 can be configured to efficiently manage power used to perform operations in the memory device 200. In some embodiments, as Figure 2As shown in FIG. 1 , the memory device 200 includes a memory interface (input / output (I / O) terminal) 202 , a control logic 204 , an X decoder 206 , a switch circuit 208 , a memory array 210 , and a high voltage (HV) generator 220 .

[0106] In some embodiments, the memory array 210 includes a plurality of memory cells. The memory cells may be coupled in series to a plurality of column word lines and a plurality of row bit lines. Each memory cell may include a memory transistor configured as a storage element (e.g., a capacitor) for storing data. The memory transistor may include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read only memory (NROM) transistor, or any suitable non-volatile memory metal oxide semiconductor (MOS) device that can store charge.

[0107] The memory device 200 may include an X decoder (or column decoder) 206 and an optional Y decoder (or row decoder). Each memory cell may be coupled to the X decoder 206 via a corresponding word line and to the Y decoder via a corresponding bit line. Thus, the X decoder 206 and the Y decoder may select each memory cell for a read operation or a write operation via a corresponding word line and a corresponding bit line.

[0108] The memory interface 202 may include a device configured to couple to one or more external devices (eg, Figure 1The memory interface 202 may include a plurality of pins of the device controller 112 and / or the host device 120 and / or the voltage converter 130 shown. The pins may include SI / SIO0 for serial data input / serial data input & output, SO / SIO1 for serial data output / serial data input & output, SIO2 for serial data input or output, SIO3 for serial data input or output, RESET# for hardware reset pin low active low, CS# for chip selection, and ECS# for ECC correction signal, and R / B# pin for indicating the ready or busy state of the memory device 200. ECS is an abbreviation for Error Correction Code (ECC) correction signal. The memory interface 202 may also include one or more other pins, such as WP# for write protection low active and / or Hold# for holding signal input. As discussed in further detail below, the memory interface 202 may also include one or more voltage pins, such as a pin 202 a for receiving a supply voltage VCC / VCCQ and a pin 202 b for receiving an operating voltage VPP.

[0109] HV generator 220 can be configured to receive input voltages from voltage pins in memory interface 202 and generate corresponding target voltages for different operations (e.g., read, write / program, and / or erase). For example, the read voltage (e.g., 6 volts) can be less than the write voltage (e.g., 8 volts). In some embodiments, such as Figure 2 As shown in , the HV generator 220 includes one or more voltage pumps (222) configured to pump the voltage from the memory interface 202 to a target voltage. Figure 3 As further described in detail in FIG. 2 , the voltage pump 222 includes a series of pump stages. In some embodiments, for example, Figure 2 As shown in , the HV generator 220 includes a reference voltage circuit 224 configured to provide a reference voltage that can be used to calibrate the voltage output by the voltage pump 222 .

[0110] In some embodiments, the HV generator 220 outputs a voltage (eg, a read voltage or a write voltage) to the X decoder 206 via the switch circuit 208. In some embodiments, the switch circuit 208 is externally coupled between the HV generator 220 and the X decoder 206, for example Figure 2. In some embodiments, the switch circuit 208 is included in the HV generator 220. The switch circuit 208 may include a switch and / or a regulator, and may be configured to adjust the voltage from the HV generator 220 to a set of voltages for a word line group (e.g., in the same block). The X decoder 206 may select the word line group and apply the set of voltages to the word line group, respectively. In some embodiments, the memory device 200 includes an internal detector 230 that may be coupled to the pin 202b and the control logic 204. The internal detector 230 may be configured to detect the voltage level of the program / erase voltage VPP provided at the pin 202b and provide the detection result to the control logic 204.

[0111] The control logic 204 may be coupled to components in the memory device 200, including the memory interface 202, the X decoder 206, the switch circuit 208, the HV generator 220, and / or the internal detector 230. The control logic 204 may be configured to generate a signal from, for example, a controller (e.g., Figure 1 The device controller 112 is shown to receive commands, address information and / or data. The control logic 204 may also process the commands, address information and / or data to generate physical address information such as blocks / pages in the memory array 210, for example.

[0112] In some embodiments, the control logic 204 includes a data register, an SRAM buffer, an address generator, a mode logic, and a state machine. The mode logic may be configured to determine whether a read or write operation occurs and provide the result of the determination to the state machine.

[0113] During a write operation, the data register in the control logic 204 may temporarily store input data from the memory interface 202, and the address generator in the control logic 204 may generate a corresponding physical address to store the input data in a specified memory cell of the memory array 210. The address generator may connect the X decoder 206 and the page buffer, and control the X decoder 206 and the page buffer to select a specified memory cell through a corresponding word line and a bit line. As long as power is supplied, the SRAM buffer may store the input data from the data register in its memory. The state machine may process the write signal from the SRAM buffer and provide a control signal to the HV generator 220, which may provide a write voltage to the X decoder 206 (through the switch circuit 208) and the page buffer. The page buffer is configured to output a write voltage to the bit line (BL) for storing the input data in a specified memory cell.

[0114] During a read operation, the state machine may provide control signals to the HV generator 220 and the page buffer circuit. The voltage generator may provide a read voltage to the X decoder 206 and the page buffer for selecting a memory cell. The page buffer may sense a small power signal (e.g., a current signal) representing a data bit (“1” or “0”) stored in the selected memory cell through a bit line coupled to the page buffer and the selected memory cell. The sense amplifier may amplify the small power signal swing to a recognizable logic level so that the data bit can be correctly interpreted by logic inside or outside the memory device 200. The data buffer may receive the amplified voltage from the sensor amplifier and output the amplified power signal to logic outside the memory device 200 through the memory interface 202.

[0115] As discussed above and in further detail below, embodiments of the present disclosure provide techniques for efficiently managing power supplies used to perform operations in storage array 210. In some embodiments, for example, Figure 2 As shown in FIG. 1 , the memory interface 202 includes an additional (or extra) pin 202 c configured to receive an additional (or extra) voltage V that may have a voltage level different from the voltages (VCC / VCCQ and VPP) received at the pins 202 a, 202 b. ADD The additional pin 202c may be coupled to the HV generator 220 (eg, a voltage pump 222). The pin 202b for receiving the voltage VPP may also be coupled to the voltage pump 222 in the HV generator 220. The voltage pump 222 may output a voltage associated with the voltage VPP to the X-decoder 206 via the switch circuit 208.

[0116] In some embodiments, the memory device 200 includes a pump switch circuit 240 and a pin detector 250. The additional pin 202c can be coupled to the pump switch circuit 240 coupled to the pin detector 250 and the HV generator 220 (e.g., the voltage pump 222). The additional pin 202c can also be directly coupled to the pin detector 250. The pin detector 250 can be coupled to the control logic 204, and the control logic 204 can be coupled to the pump switch circuit 240.

[0117] As described in further detail below, the pin detector 250 may be configured to detect an input voltage V received at the additional pin 202c. ADD The value (or voltage level) of the input voltage V ADD The value of may be provided to control logic 204 (eg, via pin detector 250). Control logic 204 may be provided to control logic 204 via memory interface 202 from a controller (eg, Figure 1The device controller 112 shown receives commands. The commands may include commands for operations such as read, write, or erase. The controller may indicate a target voltage for the operation in the command. The controller may also provide a signal to the control logic 204, and the signal indicates the target voltage for the operation. The control logic 204 may be configured to operate based on the input voltage V ADD The controller may generate a control signal to the pump switch circuit 240 based on the value of and the target voltage indicated in the command and / or signal. The control signal may control the pump switch circuit 240 to couple to the corresponding node in the voltage pump 222 to select a corresponding number of pump stages (e.g., 0, 1, 2, ...) in the voltage pump 222. As described above, the controller may also control the voltage converter (e.g., the voltage converter 130) to generate a desired voltage to be provided to the pin 202c as the input voltage V ADD The desired voltage may be configured to be close to or equal to the target voltage, which may minimize or eliminate the use of pumping stages in the voltage pump 222 , thereby improving the power consumption efficiency of the memory device 200 .

[0118] Figure 3 is a schematic diagram showing an example circuit system 300 including an example voltage pump 310 and an example pump switch circuit 330. The circuit system 300 can be implemented in the memory device 200. The voltage pump 310 can be connected to Figure 2 The voltage pump 222 is the same or similar to the voltage pump 222 shown. The pump switch circuit 330 can be connected to Figure 2 The pump switching circuit 240 shown is the same or similar.

[0119] In some embodiments, the voltage pump 310 includes an input 311, an output 313, and a series of pumping stages 312-1, 312-2, ..., 312-m, ..., 312-n (generally referred to as pumping stages 312 and individually referred to as pumping stages 312) between the input 311 and the output 313. m and n are integers, and m is less than or equal to n. The input 311 of the voltage pump 310 can be coupled to a voltage pin (e.g., Figure 2 The pin 202a) receives the input voltage V IN (It can be a fixed (or stable) voltage VDD or VCC / VCCQ). The voltage pump 310 can generate an output voltage V at the output 313. OUT In some embodiments, the input voltage V received at the input 311 IN can be pumped through the series of pump stages 312 to generate an output voltage V OUT .

[0120] The circuit system 300 may further include a pin detector 320 and a control circuit 340. Figure 3 As shown in FIG. , the pump switch circuit 330 may be coupled to an additional voltage pin 331 (eg, Figure 2Pin 331 can receive an additional voltage V to the pump switch circuit 330. ADD (For example, Figure 2 V ADD ). Pin detector 320 (eg, Figure 2 The pin detector 250 shown can be coupled to the pump switch circuit 330 and configured to detect the additional voltage V at the pin 331. ADD The pin detector 320 can provide an additional voltage V to the control circuit 340. ADD The control circuit 340 can be connected with Figure 2 The control logic 204 is the same or similar to that shown. For example, the control circuit 340 may be Figure 2 The control circuit 340 may be coupled to the pump switch circuit 330 and configured to send a control signal to the pump switch circuit 330 to control the connection between the pump switch circuit 330 and the voltage pump, thereby controlling the connection between the pump switch circuit 330 and the voltage pump based on the additional voltage V ADD Generates the target voltage.

[0121] In some embodiments, for example, Figure 3 As shown in , the pump switch circuit 330 includes a transistor 332, a gate controller 334, and a switch 336. The transistor 332 has a gate terminal coupled to the gate controller 334, and the gate controller 334 is configured to provide a gate voltage to turn on or off the transistor 332. The gate controller 334 may include an operational amplifier (OPA). The transistor 332 has a first terminal (e.g., source or drain) coupled to the additional voltage pin 331 and a second terminal (e.g., drain or source) coupled to the switch 336. During operation, the gate controller 334 may turn on the transistor 332. If the additional voltage V received at the pin 331 is ADD is greater than (or higher than) the threshold voltage of the transistor 332, the pin detector 320 detects the additional voltage V at the second terminal of the transistor 332. ADD , and the additional voltage V ADD The value (or voltage level) of is provided to the control circuit 340.

[0122] As described above, the control circuit 340 can be generated from a controller (e.g., Figure 1 The device controller 112 shown in the figure receives commands. The commands may include commands for operations such as read, write, or erase. The controller may indicate a target voltage for the operation in the command (e.g., 6 volts for a read operation or 8 volts for a write operation). The control circuit 340 may also receive a signal from the controller, and the signal indicates the target voltage for the operation. The control circuit 340 may be configured to operate based on the additional voltage V ADDThe controller may generate a control signal to the pump switch circuit 330 based on the value of and the target voltage indicated in the command or signal. The control signal may control the switch 336 in the pump switch circuit 330 to couple to corresponding nodes 315-0, 315-1, 315-2, ..., 315-m (generally referred to as nodes 315 and individually referred to as nodes 315) in the voltage pump 310 to select a corresponding number of pump stages (e.g., 0, 1, 2, ..., m) in the voltage pump 310. As described above, the controller may also control the voltage converter (e.g., Figure 1 The voltage converter 130 is used to generate the desired voltage to be provided to the pin 331 as the additional voltage V ADD The desired voltage can be configured to be close to the target voltage, which can minimize or eliminate the use of pumping stages in the voltage pump 310. If the control circuit 340 decides to use an additional voltage V ADD To provide the target voltage, the control circuit 340 may disable the input 311 of the voltage pump 310 or disable the coupling to the input 311 to receive the input voltage V IN Voltage pins (for example, Figure 2 As shown in 202a).

[0123] In some examples, if the target voltage for the read operation is 6 volts, the controller may control the voltage converter to generate a 6 volt voltage to be provided to pin 331. Then, the control circuit 340 may generate a control signal to control the switch 336 to couple to the node 315-0 at or adjacent to the output 313 to provide the target voltage, bypassing the series of pump stages 312 in the voltage pump 310. If the target voltage for the write operation is 8 volts and if the additional voltage V received at the pin 331 is ADD is 6V, the control circuit 340 determines the additional voltage V ADD needs to be pumped by a pump stage (eg, pump stage 312 - 1 ), and the control circuit 340 may be based on the additional voltage V ADD The control switch 336 is coupled to the node 315 - 1 to select the pump stage 312 - 1 to generate the target voltage.

[0124] As described above, by using the additional voltage pin 331 to receive a voltage different from the V received at the input 311 of the voltage pump 310, IN The additional voltage V ADD , the circuit system 300 can generate the target voltage by using zero or a small number of pumping stages in the voltage pump 310, which can improve power efficiency. In some embodiments, a memory device (e.g., Figure 2 The memory device 200 shown includes two or more additional voltage pins (eg, Figure 2 Pin 202c or Figure 3 pin 331) and two or more voltage pumps (eg, Figure 2The voltage pump 222 or Figure 3 A voltage pump 310 is shown to provide different levels of voltage for different uses / operations. Figure 4 4 is a schematic diagram showing another example memory device 400. The example memory device 400 includes a memory chip 410 (eg, Figure 1 The memory 116 or Figure 2 Memory device 200 shown in FIG. 4 ). Memory chip 410 may be a NAND flash memory chip. Memory device 400 may include one or more memory chips. Memory chip 410 may have multiple voltage pins, such as pin 401 for receiving voltage VCC / VCCQ, pin 402 for receiving voltage VPP, and pin 403 for receiving additional voltage V ADD1 、V ADD2 Two additional voltage pins 403a, 403b.

[0125] Each additional voltage pin may be connected, for example, via a pump switch circuit (e.g., Figure 2 The pump switch circuit 240 or Figure 3 The pump switch circuit 330 is shown coupled to a corresponding voltage pump. One or more pin detectors (e.g., Figure 2 The pin detector 250 or Figure 3 The pin detector 320 shown can be configured to detect a voltage received at an additional voltage pin. The pin detector can be configured to detect one or more voltages at one or more additional voltage pins. The control circuit (e.g., Figure 2 The control logic 204 or Figure 3 The control circuit 340 shown may be coupled to one or more pump switching circuits to control one or more voltage pumps.

[0126] Figure 5 is a flow chart of an example process 500 for managing power supply between a controller and a semiconductor device. The controller may be Figure 1 The device controller 112 or Figure 1 The host controller 122 is shown. The semiconductor device may be Figure 1 The memory 116, Figure 2 The memory device 200 or Figure 4 The memory device 400 or memory chip 410 is shown. The semiconductor device may include a memory array (e.g., Figure 2 As shown in the storage array 210). Figure 5 As shown in , process 500 may include a plurality of steps that may be executed by a controller and a semiconductor device, respectively.

[0127] A semiconductor device may include a memory array (e.g., Figure 2The memory array 210 shown has an array of memory cells coupled to a plurality of word lines. The controller may be configured to send a command to the semiconductor device, and the command may instruct the semiconductor device to perform operations such as read, program / write or erase operations on the memory array.

[0128] In some embodiments, a semiconductor device includes a voltage generator (e.g., Figure 1 The HV generator 140 or Figure 2 HV generator 220 shown), a pump switching circuit (eg, Figure 2 The pump switch circuit 240 or Figure 3 Pump switch circuit 330) and interface (e.g., Figure 2 The pump switch circuit may be configured to couple to a voltage pump, and the interface may include a memory interface 202 coupled to the pump switch circuit and configured to receive an input voltage (eg, Figure 2 or Figure 3 V ADD ) additional voltage pins (e.g., Figure 2 Pin 202c, Figure 3 Pin 331 or Figure 4 The voltage generator may include one or more voltage pumps (e.g., Figure 2 The voltage pump 222 or Figure 3 The voltage pump 310 is shown. The voltage pump may have an input (e.g., Figure 3 Input 311 as shown), output (e.g., Figure 3 output 313) and a series of pump stages (eg, Figure 3 Pump stage 312 is shown).

[0129] In some embodiments, a semiconductor device includes a voltage detector (e.g., Figure 2 The pin detector 250 or Figure 3 The pin detector 320 shown) and the control circuit (eg, Figure 2 The control logic 204 or Figure 3 The control circuit 340 is shown. The control circuit is coupled to the voltage detector and the pump switch circuit. The voltage detector can be configured to detect the value of the additional voltage received at the additional voltage pin. The control circuit can be configured to receive the value of the additional voltage from the voltage detector and control the pump switch circuit based on the value of the additional voltage.

[0130] In some embodiments, the interface includes a second voltage pin (eg, Figure 2 Pin 202a or Figure 4 The second voltage pin is coupled to the input of the voltage pump and is configured to receive a second voltage (eg, Figure 2 or Figure 4 The voltage pump may be configured to generate an output voltage at an output of the voltage pump based on the series of pump stages and the second voltage. The voltage pump may generate an output voltage based on the second voltage and the series of pump stages having a first power efficiency (e.g., 20% to 30%).

[0131] In some embodiments, the interface includes a device configured to receive a third voltage (e.g., Figure 2 or Figure 4 A third voltage pin (eg, VPP) is provided. Figure 2 Pin 202b or Figure 4 The semiconductor device may further include a second voltage detector (eg, Figure 2 The second voltage detector is coupled to the third voltage pin and is configured to detect a voltage at the third voltage pin (eg, Figure 2 The value of the third voltage received at ).

[0132] In some embodiments, the semiconductor device further includes a column decoder (eg, Figure 2 X decoder 206) and switch circuits (eg, Figure 2 The switch circuit 208 is shown. The column decoder may be configured to select each of the plurality of word lines. The switch circuit may be configured to: generate a set of operating voltages based on the target voltage from the voltage generator, and output the set of operating voltages to the column decoder, and the column decoder may be configured to apply the set of operating voltages to corresponding word lines of the plurality of word lines, respectively. The semiconductor device may be configured to perform operations on the corresponding word lines based on the set of operating voltages.

[0133] Referring to process 500, at step 502, the controller selects a target voltage for performing an operation. In some embodiments, after manufacturing the semiconductor device, appropriate operating voltages (or target voltages) may be determined for different operations with respect to minimum power consumption. For example, for a read operation, 6 volts may be selected as the target voltage; for a write operation, 8 volts may be selected as the target voltage.

[0134] At step 504, the controller sends a signal indicating the target voltage to the semiconductor device. After receiving the signal indicating the target voltage, at step 506, the semiconductor device determines whether the power supply is correct, for example, by determining whether the current voltage to the semiconductor device (e.g., the third voltage VPP received at the third voltage pin) matches the predetermined voltage. The predetermined voltage can be determined based on the target voltage. For example, the predetermined voltage can be a voltage provided to the corresponding voltage pump 222 to generate the target voltage as the output of the voltage pump 222. The second voltage detector (e.g., Figure 2 The internal detector 230 is shown to be capable of detecting the value (or voltage level) of the current voltage.

[0135] If the semiconductor device determines that the current voltage matches the predetermined voltage, then at step 512, the semiconductor device performs an operation using the current voltage. If the semiconductor device determines that the current voltage does not match the predetermined voltage, then the semiconductor device sets an error flag 508. The controller may detect the error flag 508 and take corresponding actions. For example, the controller may send a signal to a voltage converter (e.g., Figure 1 The controller may send a control signal to a voltage converter 130 as shown. The controller may send a control signal in response to detecting an error flag 508 or after selecting a target voltage for operation at step 502. The voltage converter may generate an additional voltage corresponding to the target voltage and provide the additional voltage to an additional voltage pin on the semiconductor device. The control signal may be associated with the operation and indicate the target voltage or the additional voltage.

[0136] At step 510, the semiconductor device disables an external power source and changes a power supply configuration. The semiconductor device may disable the external power source by disabling receiving a second voltage VCC / VCCQ from a second voltage pin or at an input of a voltage pump and disabling receiving a third voltage VPP from a third voltage pin. The semiconductor device may change the power supply configuration by receiving an additional voltage from an additional voltage pin, and controlling a pump switch circuit coupled to a corresponding node in the voltage pump to select a corresponding number of pump stages of the series of pump stages to output a target voltage at an output of the voltage pump. After generating the target voltage, at step 512, the semiconductor device performs an operation using the target voltage. For example, the switch circuit may generate a set of operating voltages based on the target voltage from the voltage pump and output the set of operating voltages to a column decoder. The column decoder may apply the set of operating voltages to corresponding word lines of the plurality of word lines, respectively. The semiconductor device may perform an operation on the corresponding word line based on the set of operating voltages.

[0137] In some embodiments, the control circuit is configured to: receive a signal from a controller, the signal being associated with an operation and indicating a target voltage; receive a value of an additional voltage detected from a voltage detector; and control a pump switch circuit to couple to a corresponding node in the voltage pump based on the value of the additional voltage and the signal.

[0138] In some embodiments, the pump switching circuit includes a switch (e.g., Figure 3 336), which can be switched to couple to multiple nodes in the voltage pump (e.g., Figure 3 The plurality of nodes may include: a first node (eg, Figure 3The node 315-0 shown is located between the output of the voltage pump and the first pump stage in the series of pump stages, and the first pump stage is adjacent to the output of the voltage pump; and a second node (for example, node 315-1, 315-2 or 315-m) is located between two adjacent voltage pump stages in the series of pump stages.

[0139] In some embodiments, the control circuit is configured to: receive a second signal from a controller, the second signal being associated with a second operation and indicating a second target voltage; and control the pump switch circuit to couple to a second corresponding node in the voltage pump based on the second signal and a second input voltage received at the voltage pin.

[0140] In some embodiments, the voltage generator further includes a reference voltage circuit (eg, Figure 2 A reference voltage circuit 224 is shown, and the control circuit is coupled to the voltage generator and is configured to calibrate the target voltage based on the reference voltage.

[0141] In some embodiments, the interface includes a plurality of additional voltage pins including the additional voltage pins described above (e.g., Figure 4 As shown in 403a, 403b). The semiconductor device may include a plurality of voltage pumps, and each of the plurality of additional voltage pins is coupled to a corresponding voltage pump of the plurality of voltage pumps.

[0142] The disclosed examples and other examples may be implemented as one or more computer programs, such as one or more modules of computer program instructions encoded on a computer-readable medium to be executed by a data processing device or to control the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more of them. The term "data processing device" encompasses all devices, devices, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the device may also include code that creates an execution environment for the computer program in question (e.g., code that constitutes processor firmware), a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0143] A system may include all devices, apparatuses, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may include code that creates an execution environment for the computer program in question (e.g., code constituting processor firmware), a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0144] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language file), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of code). A computer program may be deployed for execution on one computer located at one location or on multiple computers distributed between multiple locations and interconnected by a communications network.

[0145] The processes and logic flows described in this document may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows may also be performed by special purpose logic circuit systems (e.g., field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs)), and the apparatus may also be implemented as such special purpose logic circuit systems.

[0146] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors and any one or more processors of any type of digital computer. Generally speaking, the processor will receive instructions and data from a read-only memory or a random access memory or from both. The essential elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally speaking, a computer may also include one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data, or will be operatively coupled to receive data from or transmit data to the one or more mass storage devices or to perform both operations. However, a computer need not necessarily have such devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices, including, for example: semiconductor memory devices, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices; magnetic disks. The processor and the memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0147] Although this document may set forth many details, these details should not be interpreted as limitations on the scope of the invention claimed or claimable, but rather should be interpreted as descriptions of features specific to a particular embodiment. Certain features set forth in this document in the context of different embodiments may also be implemented in conjunction with a single embodiment. Conversely, the various features set forth in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be set forth above as functioning in certain combinations and even initially claimed, in some cases, one or more features from the combination may be removed from the claimed combination, and the claimed combination may involve a sub-combination or a variation of the sub-combination. Similarly, although the operations are depicted in a particular order in the drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in a sequential order, or requiring all of the operations shown to be performed to achieve the desired result.

[0148] Only a few examples and implementations are disclosed. Changes, modifications and improvements may be made to the examples and implementations and other implementations based on what is disclosed.

Claims

1. A semiconductor device comprising: a voltage pump having an input, an output, and a series of pump stages coupled between the input and the output; a pump switching circuit configured to be coupled to the voltage pump; as well as interface, including a voltage pin coupled to the pump switching circuit, The pump switch circuit is configured to provide an input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages in the series of pump stages to output a target voltage at the output of the voltage pump.

2. The semiconductor device according to claim 1, wherein The corresponding number is an integer equal to or greater than 0.

3. The semiconductor device according to claim 1, further comprising: Voltage detector; as well as a control circuit coupled to the voltage detector and the pump switch circuit, wherein the voltage detector is configured to detect a value of the input voltage received at the voltage pin, and The control circuit is configured to: receiving the value of the input voltage from the voltage detector, and The pump switch circuit is controlled to couple to the corresponding node in the voltage pump based on the value of the input voltage.

4. The semiconductor device according to claim 3, wherein: The control circuit is configured to: receiving a signal indicative of the target voltage, and Based on the signal and the value of the input voltage, the pump switch circuit is controlled to couple to the corresponding node in the voltage pump.

5. The semiconductor device according to claim 4, wherein: The target voltage is a first target voltage, and wherein the control circuit is configured to: receiving a second signal indicative of a second target voltage, and The pump switch circuit is controlled to couple to a second corresponding node in the voltage pump based on the second signal and a second input voltage received at the voltage pin.

6. The semiconductor device according to claim 3, wherein: The pump switching circuit includes a switch switchable to couple to each of a plurality of nodes in the voltage pump, and The multiple nodes include: a first node located between the output of the voltage pump and a first pumping stage in the series of pumping stages, the first pumping stage being adjacent to the output of the voltage pump, and A second node is located between two adjacent pump stages in the series of pump stages.

7. The semiconductor device according to claim 3, wherein: The interface also includes: a second voltage pin coupled to the input of the voltage pump and configured to receive a second voltage, Wherein the voltage pump is configured to generate an output voltage at the output of the voltage pump based on the series of pump stages and the second voltage.

8. The semiconductor device according to claim 3, wherein: The interface further includes a third voltage pin configured to receive a third voltage, The semiconductor device further includes a second voltage detector coupled to the voltage pin and configured to detect a value of the third voltage received at the third voltage pin, and The control circuit is configured to: receiving the value of the third voltage from the second voltage detector, determining whether the value of the third voltage matches a predetermined voltage, and In response to determining that the value of the third voltage does not match the predetermined voltage, receiving the third voltage at the third voltage pin is prohibited, and the pump switch circuit is controlled to couple to the corresponding node in the voltage pump based on the value of the input voltage to generate the target voltage.

9. The semiconductor device according to claim 1, further comprising: a memory array having an array of memory cells coupled to a plurality of word lines; a decoder coupled to the memory array and configured to select each of the plurality of word lines; as well as A switch circuit is coupled between the decoder and the voltage pump and is configured to: generating a set of operating voltages based on the target voltage, and outputting the set of operating voltages to the decoder, and The decoder is configured to apply the set of operating voltages to corresponding word lines among the plurality of word lines, respectively.

10. The semiconductor device according to claim 1, wherein The input voltage is in the range of 6V to 10V.

11. A system for a semiconductor device, comprising: A memory device including a memory array having an array of memory cells coupled to a plurality of word lines; as well as a controller coupled to the memory device and configured to send a command to the memory device, the command instructing the memory device to perform an operation, The memory device further comprises: a voltage generator comprising a voltage pump having an input, an output, and a series of pump stages coupled between the input and the output; a pump switching circuit configured to be coupled to the voltage pump; and an interface comprising a voltage pin coupled to the pump switch circuit and configured to receive an input voltage, wherein the pump switch circuit is configured to provide the input voltage received at the voltage pin to a corresponding node in the voltage pump to select a corresponding number of pump stages in the series of pump stages to output a target voltage at the output of the voltage pump, and Wherein the memory device is configured to perform the operation based on the target voltage output at the output of the voltage pump.

12. The system of claim 11, comprising a voltage converter coupled to the memory device, The voltage converter is configured to generate the input voltage based on a reference voltage and provide the input voltage to the voltage pin.

13. The system according to claim 12, wherein: The voltage converter is coupled to the controller and is configured to generate the input voltage based on a signal from the controller, the signal being associated with the command and indicative of the input voltage.

14. The system according to claim 11, wherein: The memory device further comprises: voltage detector; and a control circuit coupled to the voltage detector and the pump switch circuit, wherein the voltage detector is configured to detect a value of the input voltage received at the voltage pin, The control circuit is configured to: receiving a signal from the controller, the signal associated with the operation and indicative of the target voltage, receiving the value of the input voltage from the voltage detector, and Based on the value of the input voltage and the signal, the pump switch circuit is controlled to couple to the corresponding node in the voltage pump.

15. The system of claim 14, wherein: The target voltage is a first target voltage, and wherein the control circuit is configured to: receiving a second signal from the controller, the second signal being associated with a second operation and indicating a second target voltage, and The pump switch circuit is controlled to couple to a second corresponding node in the voltage pump based on the second signal and a second input voltage received at the voltage pin.

16. The system of claim 15, wherein: The controller is configured to send a control signal to a voltage converter to generate the second input voltage to be provided to the voltage pin.

17. The system of claim 14, wherein: The pump switching circuit includes a switch switchable to couple to each of a plurality of nodes in the voltage pump, and The multiple nodes include: a first node located between the output of the voltage pump and a first pumping stage in the series of pumping stages, the first pumping stage being adjacent to the output of the voltage pump, and The second node is located between two adjacent voltage pumping stages in the series of pumping stages.

18. The system of claim 14, wherein: The interface also includes: a second voltage pin coupled to the input of the voltage pump and configured to receive a second voltage, Wherein the voltage pump is configured to generate an output voltage at the output of the voltage pump based on the series of pump stages and the second voltage.

19. The system of claim 14, wherein: The interface further includes a third voltage pin configured to receive a third voltage, wherein the memory device further comprises a second voltage detector coupled to the voltage pin and configured to detect a value of the third voltage received at the third voltage pin, and The control circuit is configured to: receiving the value of the third voltage from the second voltage detector, determining whether the value of the third voltage matches a predetermined voltage associated with the target voltage, and In response to determining that the value of the third voltage does not match the predetermined voltage, receiving the third voltage at the third voltage pin is prohibited, and the pump switch circuit is controlled to couple to the corresponding node in the voltage pump based on the value of the input voltage to generate the target voltage.

20. The system of claim 11, wherein: The interface includes a plurality of additional voltage pins including the voltage pin, and Wherein the memory device includes a plurality of voltage pumps, and wherein each of the plurality of additional voltage pins is coupled to a corresponding voltage pump of the plurality of voltage pumps.

21. The system of claim 11, further comprising: a column decoder coupled to the memory array and configured to select each of the plurality of word lines; as well as a switch circuit coupled between the column decoder and the voltage generator, wherein the switch circuit is configured to: generating a set of operating voltages based on the target voltage, and outputting the set of operating voltages to the column decoder, and wherein the column decoder is configured to apply the set of operating voltages to corresponding word lines among the plurality of word lines, respectively, and Wherein the memory device is configured to perform the operation based on the set of operating voltages applied to the corresponding word line.

22. A method performed by a semiconductor device, the method comprising: receiving a command to perform an operation in the semiconductor device; receiving a signal indicative of a target voltage associated with the operation; detecting a value of an input voltage at a voltage pin of the semiconductor device, wherein the semiconductor device includes a pump switch circuit coupled to the voltage pin; controlling the pump switch circuit to couple to a corresponding node in a voltage pump of the semiconductor device based on the value of the input voltage and the signal indicative of the target voltage, wherein the voltage pump includes an input, an output, and a series of pump stages coupled between the input and the output; generating the target voltage at the output of the voltage pump using a corresponding number of pump stages coupled between the corresponding node and the output; as well as The operation is performed based on the target voltage.

23. The method according to claim 22, further comprising: receiving a second input voltage from a second voltage pin; determining whether the second input voltage matches a predetermined voltage associated with the target voltage; as well as In response to determining that the second input voltage does not match the predetermined voltage, prohibiting the second input voltage from being received by the semiconductor device, The controlling of the pump switch circuit to couple to the corresponding node in the voltage pump is performed in response to determining that the second input voltage does not match the predetermined voltage.

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