Memory devices and their operating methods, memory systems, storage media

Abstract

This disclosure provides a memory device, its operation method, a memory system, and a storage medium. The memory device includes a memory cell array and peripheral circuitry. The memory cell array includes multiple memory blocks. Each memory block includes multiple memory cells and multiple word lines. The peripheral circuitry is configured to apply a first pass voltage to a first word line, a second pass voltage to a second word line, and a third pass voltage to a third word line when performing a first read operation on a memory cell coupled to a selected word line. The first word line is at least one word line physically located above and below the selected word line. The second and third word lines are both word lines physically located on the side of the first word line away from the selected word line. The memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell. The first pass voltage, the second pass voltage, and the third pass voltage are all different.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, a memory system, and a storage medium. Background Technology

[0002] Low-power, lightweight, and high-performance non-volatile memory devices, such as 3D NAND flash memory, are widely used in electronic products. However, many problems still need to be solved when performing read operations on these memory devices. Summary of the Invention

[0003] To address one or more of the existing technical problems, this disclosure provides a memory device, its operating method, a memory system, and a storage medium. Specifically, this disclosure provides a memory device comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks; each memory block includes multiple memory cells and multiple word lines coupled to the multiple memory cells.

[0004] The peripheral circuit is configured to apply a first pass voltage to a first word line, a second pass voltage to a second word line, and a third pass voltage to a third word line when performing a first read operation on a memory cell coupled to a selected word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on the side of the first word line away from the selected word line; the memory cell coupled to the second word line is a programmed memory cell; and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different.

[0005] In some embodiments, the first through voltage is greater than the second through voltage; the second through voltage is greater than the third through voltage.

[0006] In some embodiments, the peripheral circuitry is further configured to: perform storage status detection on selected memory blocks; the storage status detection result includes full memory blocks and incomplete memory blocks; perform the first read operation on selected word-line coupled memory cells in the incomplete memory blocks; and perform the second read operation on selected word-line coupled memory cells in the full memory blocks.

[0007] In some embodiments, the peripheral circuitry is further configured to: when performing the second read operation on a memory cell coupled to a selected word line in the filled memory block, apply the first through voltage on a fourth word line and apply the second through voltage on a fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

[0008] In some embodiments, the peripheral circuit is further configured to: after performing the first read operation once, increment the read count by a first count value; after performing the second read operation once, increment the read count by a second count value; wherein the first count value is less than the second count value.

[0009] In some embodiments, when the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

[0010] In some embodiments, a dummy word line is provided between at least two of the first word line, the second word line, and the third word line; the peripheral circuit is further configured to apply the second pass voltage to the dummy word line when the first read operation is performed.

[0011] In some embodiments, the peripheral circuitry is further configured to: apply a read voltage to the selected word line during the execution of the first read operation; wherein the memory cell coupled to the selected word line is a programmed memory cell.

[0012] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0013] This disclosure also provides a memory system, including: one or more memory devices as described in the above embodiments of this disclosure; and a memory controller coupled to the memory devices for controlling the memory devices.

[0014] This disclosure also provides an operation method for a memory device, the operation method comprising: when performing a first read operation on a memory cell coupled to a selected word line, applying a first through voltage on a first word line, applying a second through voltage on a second word line, and applying a third through voltage on a third word line; wherein the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on the side of the first word line away from the selected word line; the memory cell coupled to the second word line is a programmed memory cell; and the memory cell coupled to the third word line is an unprogrammed memory cell; the first through voltage, the second through voltage, and the third through voltage are all different;

[0015] The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks; each memory block includes multiple memory cells and multiple word lines coupled to the multiple memory cells.

[0016] In some embodiments, the first through voltage is greater than the second through voltage; the second through voltage is greater than the third through voltage.

[0017] In some embodiments, the operation method further includes: performing storage status detection on selected storage blocks; the storage status detection result includes full storage blocks and incomplete storage blocks; performing the first read operation on selected word-line-coupled storage cells in the incomplete storage blocks; and performing the second read operation on selected word-line-coupled storage cells in the full storage blocks.

[0018] In some embodiments, the operation method further includes: when performing the second read operation on a memory cell coupled to a selected word line in the filled memory block, applying the first through voltage on a fourth word line and applying the second through voltage on a fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

[0019] In some embodiments, the operation method further includes: after performing the first read operation once, incrementing the read count by a first count value; after performing the second read operation once, incrementing the read count by a second count value; wherein the first count value is less than the second count value.

[0020] In some embodiments, when the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

[0021] In some embodiments, a dummy word line is provided between at least two of the first word line, the second word line, and the third word line; the operation method further includes: when performing the first read operation, applying the second through voltage to the dummy word line.

[0022] In some embodiments, the operation method further includes: applying a read voltage to the selected word line during the execution of the first read operation; wherein the memory cell coupled to the selected word line is a programmed memory cell.

[0023] This disclosure also provides a storage medium storing executable instructions, which, when executed by a memory controller, can implement the steps of the method described in the above embodiments of this disclosure.

[0024] This disclosure provides a memory device, its operation method, a memory system, and a storage medium. The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple memory blocks; each memory block includes multiple memory cells and multiple word lines coupled to the multiple memory cells. The peripheral circuitry is configured to apply a first pass voltage to a first word line, a second pass voltage to a second word line, and a third pass voltage to a third word line when performing a first read operation on a memory cell coupled to a selected word line. The first word line is at least one word line physically located above and below the selected word line. The second and third word lines are both word lines physically located on the side of the first word line away from the selected word line. The memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell. The first pass voltage, the second pass voltage, and the third pass voltage are all different. In this disclosure, when performing the first read operation, applying the first pass voltage to the first word line adjacent to the selected word line reduces the coupling effect of the read voltage on the adjacent word lines. At the same time, applying a third conduction voltage to the third word line coupled to the unprogrammed memory cell can reduce read interference caused by the first read operation to the unprogrammed memory cell, thereby improving the read performance and reliability of the memory device. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0026] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0027] Figure 2bThis is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0028] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0029] Figure 3b This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of the present disclosure;

[0030] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND-type memory strings according to an embodiment of the present disclosure;

[0031] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0032] Figure 6a A schematic diagram of a storage string in a filled storage block provided in an embodiment of this disclosure;

[0033] Figure 6b A schematic diagram of a storage string in an incomplete storage block provided in an embodiment of this disclosure;

[0034] Figure 6c A schematic diagram of a storage string in another unfilled storage block provided in an embodiment of this disclosure;

[0035] Figure 7 This is a schematic diagram illustrating the implementation process of a method for performing a first read operation on a memory block that is not fully written, as provided in an embodiment of this disclosure.

[0036] Figure 8 A schematic diagram of a storage string in another unfilled storage block provided in an embodiment of this disclosure;

[0037] Figure 9a A schematic diagram illustrating the voltage application during a first read operation on an unfilled memory block, provided in an embodiment of this disclosure.

[0038] Figure 9b A schematic diagram illustrating the voltage application during a second read operation on a fully written memory block, provided in an embodiment of this disclosure.

[0039] Figure 10 This is a schematic diagram illustrating the read operation implementation process of a memory device according to an embodiment of the present disclosure.

[0040] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0041] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0043] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0048] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0049] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0050] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments in solid state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0051] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0052] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0053] Figure 3a An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each two rows of memory cell rows are separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The storage block shown contains 6 storage chips. In actual applications, the number of storage chips in a storage block is not limited to this.

[0054] In some embodiments, each memory block may be coupled with multiple word lines, and the multiple memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3a In each memory chip, all memory cells are coupled together to form a page.

[0055] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0056] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0057] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0058] like Figure 3bAs shown, each memory string 308 may include a lower selection transistor 310 (also referred to as a source selection transistor BSG, which includes a source selection gate) at its source end and an upper selection transistor 312 (also referred to as a drain selection transistor TSG, which includes a drain selection gate) at its drain end. The source selection transistor BSG 310 and the drain selection transistor TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0059] like Figure 3b As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304 can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, in conjunction with the foregoing... Figure 3aMultiple memory cells are isolated from each other by an upselect gate isolation structure and a gate isolation structure. The memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each row being parallel to both the gate isolation structure and the upselect gate isolation structure. Memory cells in a memory chip sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page according to the memory mode of the corresponding memory cell 306 (e.g., SLC or MLC as mentioned above). Logical pages can constitute the basic data unit for programming and reading operations.

[0060] refer to Figure 3a , Figure 3b Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0061] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301, including a memory string 308 exemplified by NAND, is shown according to some aspects of this disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0062] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0063] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0064] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0065] Return to reference Figure 3b The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0066] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory cell array 301 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0067] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0068] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0069] In practical applications, 3D NAND flash memory can include at least one array of memory cells. This array can include multiple stacked memory cell layers arranged vertically, each layer comprising multiple memory cells, which can be coupled to a word line. These multiple memory cell layers can be further divided into multiple blocks. With the development of 3D NAND flash memory, the number of memory cell layers is increasing, and the size of individual blocks is also growing, frequently resulting in open blocks. However, when reading from an open block, various problems affecting read performance may arise. For example, as the number of stacked layers increases and device size decreases, the distance between memory cell layers becomes smaller. When a read voltage is applied to a selected word line, coupling effects easily occur between the selected word line and adjacent word lines, and the closer the selected word line is to adjacent word lines, the more severe the coupling effect. For example, when a read voltage is applied to a selected word line, read interference is generated on non-selected word lines, especially on unprogrammed memory cells coupled to non-selected word lines, thereby affecting the subsequent use of unprogrammed memory cells.

[0070] In response to one or more of the above-mentioned problems, this disclosure provides a memory device and a method of operating the same, wherein the memory device includes peripheral circuitry and a memory cell array coupled to the peripheral circuitry.

[0071] Peripheral circuitry may include any suitable digital, analog, and / or mixed-signal circuitry configured to facilitate various operations such as read, write, and erase operations of the memory. For example, peripheral circuitry may include control logic (e.g., control circuitry or controller), data buffers, decoders (also called decoders), drivers, and read / write circuitry. When the control logic receives read / write operation commands and address data, under the control of the control logic, the decoder can apply the corresponding voltage obtained from the driver to the corresponding bit lines and word lines based on the decoded address to realize data read / write and interact with the outside world through the data buffer.

[0072] A memory cell array may include multiple memory blocks, each memory block may include multiple memory strings, and each memory string may include multiple memory cells stacked vertically. The top memory cell (top select transistor TSG) of each memory string is coupled to the top select line SSL, and the bottom memory cell (bottom select transistor BSG) of each memory string is coupled to the ground select line GSL. The multiple memory cells located between the top and bottom memory cells are coupled to multiple word lines (WL). Here, the multiple word lines may include dummy word lines (DWL), selected word lines (Sel.WL), unselected word lines (Unsel.WL), etc.

[0073] It should be noted that, for the programming process of 3D NAND flash memory, the general programming order is to start programming from the memory cell closest to the lower select transistor (BSG) in the memory string and end from bottom to top to the memory cell closest to the upper select transistor (TSG). This programming order can be called the normal program sequence or forward programming order. In other embodiments, the programming order is to start programming from the memory cell closest to the upper select transistor (TSG) in the memory string and end from top to bottom to the memory cell closest to the lower select transistor (BSG). This programming order can be called reverse programming. In some embodiments, due to different amounts of data to be programmed, the storage states of the memory blocks in the memory cell array may be different. For example, some memory blocks in the memory cell array may be full, while others may not be full. For example, Figure 6a A schematic diagram of a storage string in a filled storage block is shown; Figure 6b and Figure 6c Each of these diagrams illustrates a storage string within an incomplete storage block (wherein, Figure 6b The programming order of the storage strings shown is reverse programming. Figure 6cThe programming order of the storage strings shown is sequential programming, which will be explained in detail below and will not be repeated here.

[0074] After programming the storage block is complete, it can be read.

[0075] It should be noted that, based on the different storage states of the aforementioned storage blocks (full or not full), the problems that may occur during the reading process are also different. Therefore, before performing a read operation on a storage block, the operation method of the memory device includes: performing a storage state detection on the selected storage block; the storage state detection result includes full storage blocks and not full storage blocks; performing the first read operation on selected word-line coupled storage cells in the not-full storage block; and performing the second read operation on selected word-line coupled storage cells in the full storage block.

[0076] refer to Figure 6a , Figure 6b , Figure 6c Based on the test results, storage blocks can be divided into fully written storage blocks (see reference). Figure 6a ) and incomplete storage blocks (see reference) Figure 6b , Figure 6c When performing a read operation, a first read operation is performed on the selected word-line-coupled memory cells in a non-full memory block, and a second read operation is performed on the selected word-line-coupled memory cells in a full memory block. It should be noted that... Figure 6b The memory string shown is programmed in reverse order, and the unprogrammed memory cells (coupled to the third word line 606) on the memory string are adjacent to the lower selection transistor BSG (such as 607a); Figure 6c The illustrated memory string is sequentially programmed, with unprogrammed memory cells (coupled to the third word line 606) adjacent to the upper selection transistor TSG (e.g., 601a). In other embodiments, depending on the programming order, unprogrammed memory cells may also be located in the middle of the memory string, i.e., the unprogrammed memory cells are surrounded by programmed memory cells (not shown in the figures) on both sides. For ease of understanding, one of the memory strings of an unfilled memory block is referred to here and below as... Figure 6b The storage string shown is used as an example for illustration.

[0077] The following is combined with Figure 6a , Figure 6b , Figure 7 , Figure 8 The details of performing a first read operation on a selected word-line coupled memory cell of a memory block that is not full, and performing a second read operation on a selected word-line coupled memory cell of a full memory block are explained.

[0078] refer to Figure 6a , Figure 7 , Figure 7 This is a schematic flowchart illustrating a method for performing a first read operation on a selected word-line-coupled memory cell of an unfilled memory block, as provided in an embodiment of this disclosure. Figure 7 As shown, the method for performing the first read operation includes the following steps:

[0079] Step S701: When performing a first read operation on a memory cell coupled to a selected word line, a first pass voltage is applied to the first word line, a second pass voltage is applied to the second word line, and a third pass voltage is applied to the third word line; the first word line is at least one word line physically located above and below the selected word line; the second and third word lines are both word lines physically located on the side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different.

[0080] It should be noted that the first, second, and third character lines are all non-selected character lines; among them, the first character line is the non-selected character line adjacent to the selected character line, which may include one, two, or three character lines physically located above or below the selected character line. For ease of understanding, this explanation will only use the example of the first character line including one character line physically located above or below the selected character line. (Reference) Figure 6a That is, the first word line 604 is one non-selected word line adjacent to the selected word line 605 above and below it. The second and third word lines are physically located further away from the selected word line than the first word line; here, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell. It should be noted that due to different programming orders of the memory string (sequential programming and / or reverse programming), the relative positions of the second and third word lines on the memory string are different. For example, reverse programming is used here. (Refer to...) Figure 6b The second character line 603 is located between the third character line 606 and the first character line 604. That is, the third character line 606 is physically located on the side of the second character line 603 furthest from the first character line 604. In other words, the distance between the third character line 606 and the selected character line 605 is greater than the distance between the second character line 603 and the selected character line 605. Furthermore, it should be noted that the following descriptions of the number of first character lines and the relative positions of the second and third character lines are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0081] For example, refer to Figure 6b , Figure 7 , Figure 9aIn step S701, when performing the first read operation, a read voltage Vread is applied to the selected word line 605 (to distinguish it from the read voltage in the second read operation, the read voltage here is named the first read voltage Vread1), a first pass voltage Vpass1 is applied to the first word line 604 adjacent to the selected word line 605, a second pass voltage Vpass2 is applied to the second word line 603, and a third pass voltage Vpass3 is applied to the third word line 606. The first pass voltage Vpass1, the second pass voltage Vpass2, and the third pass voltage Vpass3 are all different based on the different distances between the first word line, the second word line, and the third word line and the selected word line.

[0082] In some embodiments, reference Figure 6b The distances between the first word line, the second word line, and the third word line and the selected word line gradually increase. A first pass voltage Vpass1 is applied to the first word line 604, a second pass voltage Vpass2 is applied to the second word line 603, and a third pass voltage Vpass3 is applied to the third word line 606, which gradually decreases in sequence. For example, the first pass voltage Vpass1 is greater than the second pass voltage Vpass2, i.e., Vpass1 > Vpass2; the second pass voltage Vpass2 is greater than the third pass voltage Vpass3, i.e., Vpass2 > Vpass3.

[0083] Thus, applying a first pass voltage Vpass1 to the first word line 604 adjacent to the selected word line 605 reduces the voltage difference between the selected word line 605 and the first word line 604, thereby reducing the coupling effect between the selected word line 605 and the first word line 604. Furthermore, it should be understood that during the first read operation, the channel is applied a voltage of 0V, and a first read voltage Vread1 is applied to the selected word line 605. At this time, an electric field is formed between the memory cells coupled to the non-selected word lines (second word line 603 and third word line 606) and the channel, which easily causes read interference. Based on this, applying a second pass voltage Vpass2 to the second word line 603 coupled to the programmed memory cell, and applying a third pass voltage Vpass3 to the third word line 606 coupled to the unprogrammed memory cell, reduces the read interference (weak programming) caused by the read voltage to both programmed and unprogrammed memory cells; thus, the read performance and reliability of the memory device can be improved. In addition, based on the different distances between the unselected word lines (first word line, second word line, third word line) and the selected word lines, applying different through voltages to the unselected word lines can more accurately solve the problem of read interference and coupling effect superposition in the read operation.

[0084] It should be noted that in the embodiments of this disclosure, all memory cells coupled to the selected word line are programmed memory cells. In a non-full memory block, when the memory cell coupled to the selected word line is the last group (layer) of programmed memory cells, a first word line adjacent to the selected word line overlaps with a third word line coupled to an unprogrammed memory cell; that is, the selected word line is adjacent to the third word line. In this case, when performing the first read operation, a first pass voltage is applied to the same word line where the first and third word lines overlap.

[0085] For example, refer to Figure 8 Word line 605 is selected as the word line coupled to the last group (layer) of memory cells in the programmed memory cells. A first word line 604 and a third word line 606 adjacent to word line 605 overlap, meaning they are the same word line. In this case, when performing the first read operation, a first pass voltage Vpass1 is applied to this overlapping word line. Here, the first pass voltage Vpass1 is greater than the third pass voltage Vpass3, i.e., Vpass1 > Vpass3. This reduces the coupling effect of the first read voltage on adjacent word lines (such as the first word line) and also reduces read interference caused by the first read voltage on unprogrammed memory cells (coupled to the third word line).

[0086] In some embodiments, a dummy unit is further provided in the memory block, and the dummy unit is coupled to a dummy word line; the physical location of the dummy unit in the memory block can be selected and set according to actual conditions; in other words, the relative position of the dummy word line with the first word line, the second word line, and the third word line is different depending on the position of the dummy unit in the memory block; that is, a dummy word line can be set between at least any two word lines of the first word line, the second word line, and the third word line. In this embodiment of the present disclosure, when performing the first read operation, a second pass voltage is applied to the dummy word line. For example, refer to Figure 6b The dummy cell is coupled to the dummy word line 602. Here, the dummy word line 602 is located between the second word line 603 and the upper selection transistor (such as 601a). When the first read operation is performed, a second pass voltage Vpass2 is applied to the dummy word line 602 to reduce the coupling effect between the dummy word line 602 and its adjacent word line (such as the second word line 603).

[0087] The following is combined with Figure 6a , Figure 9b The following describes the scenario where a second read operation is performed on a full storage block.

[0088] In some embodiments, the operation method further includes: when performing a second read operation on a memory cell coupled to a selected word line in a filled memory block, applying a first through voltage on a fourth word line and applying a second through voltage on a fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

[0089] refer to Figure 6a Both the fourth and fifth word lines are non-selected word lines. The fourth word line can include one, two, or three word lines physically located above or below the selected word line. Taking the fourth word line as an example (one word line physically located above or below the selected word line), the fifth word line refers to all word lines physically located on the side of the fourth word line furthest from the selected word line. Here, "all word lines" refers to all non-selected word lines except for the select lines coupled to the upper and lower select transistors, and the fourth word line. Examples include non-selected word lines coupled to programmed memory cells, and dummy word lines coupled to dummy cells. Figure 6a (The dummy character line is not marked). It should be understood that, compared to the fourth character line, the fifth character line is physically located further away from the selected character line; for example, refer to... Figure 6a The fourth word line 609 is located between the selected word line 608 and the fifth word line 610. Furthermore, it should be noted that the following description of the number of fourth word lines is for illustrative purposes only and is not intended to limit the scope of this disclosure. It should be understood that, apart from dummy word lines, the memory cells coupled to the selected word line, fourth word line, and fifth word line in a filled memory block are all programmed memory cells.

[0090] For example, refer to Figure 6a When performing the second read operation, a second read voltage Vread2 is applied to the selected word line 608, a first pass voltage Vpass1 is applied to the fourth word line 609, and a second pass voltage Vpass2 is applied to the fifth word line 610; here, the first pass voltage Vpass1 is greater than the second pass voltage Vpass2, i.e., Vpass1 > Vpass2. In this embodiment of the present disclosure, when performing the second read operation, applying the first pass voltage to a non-selected word line (such as the fourth word line) adjacent to the selected word line can reduce the coupling effect between the selected word line and the adjacent word line (such as the fourth word line). Applying the second pass voltage to the fifth word line can reduce the read interference caused by the second read voltage to the fifth word line.

[0091] It should be noted that the second read voltage Vread2 can be the same as or different from the first read voltage Vread1.

[0092] As mentioned earlier, the memory block also includes an up-select transistor (TSG) and a down-select transistor (BSG), and the number of TSGs and BSGs can be arbitrarily set. (Reference) Figure 6a , Figure 6b The upper selection transistor TSG includes a selected upper selection transistor 601b and an unselected upper selection transistor 601a; the lower selection transistor BSG includes a selected lower selection transistor 607a and an unselected lower selection transistor 607b.

[0093] refer to Figure 6b , Figure 9a When performing the first read operation, a first selection voltage Vtsg is applied to the selected upper selection transistor 601b, and a second selection voltage Vss is applied to the unselected upper selection transistor 601a. ​​A third selection voltage Vbsg is applied to the selected lower selection transistor 607a, and a fourth selection voltage Vss is applied to the unselected lower selection transistor 607b; here, the fourth selection voltage is the same as the second selection voltage.

[0094] refer to Figure 6a , Figure 9b When performing the second read operation, a first selection voltage Vtsg is applied to the selected upper selection transistor 601b, and a second selection voltage Vss is applied to the unselected upper selection transistor 601a. ​​A third selection voltage Vbsg is applied to the selected lower selection transistor 607a, and a fourth selection voltage Vss is applied to the unselected lower selection transistor 607b; here, the fourth selection voltage is the same as the second selection voltage.

[0095] In some embodiments, the memory device further includes a plurality of bit lines, wherein, during a read operation, the plurality of bit lines may be further divided into selected bit lines and unselected bit lines. For example, refer to... Figure 9a , Figure 9b During the first or second read operation, a bit line voltage Vdd is applied to the selected positioning line 611, and a disable voltage is applied to the unselected positioning line. Figure 9a , Figure 9b (Not shown in the image).

[0096] In some specific embodiments, the memory device further includes a counter; the counter is used to count the number of read operations performed on the memory cell, and the counter accumulates the number of reads; when the counter value reaches a certain threshold (such as a preset threshold), a read scan of the corresponding memory block is triggered, that is, a reliability test is performed on the corresponding memory block; at this time, the operation method further includes: detecting / checking the reliability of the memory block; and after each detection, the counter value is reset to zero. However, when the number of read operations frequently reaches the preset threshold, the frequency (or number) of reliability testing (i.e., read scan) of the memory block increases; wherein, the more times the test is performed, the greater the impact on the read performance of the memory device.

[0097] It should be understood that each read operation performed on a storage cell of a storage block increases the wear of the storage block by one. When the method of performing the first read operation in the above embodiments of this disclosure is used to read a storage block that is not full, the wear of the corresponding storage block is improved. Based on this, in some embodiments of this disclosure, different counting methods are used for different storage blocks.

[0098] In some embodiments, the operation method further includes: after performing a first read operation, incrementing the read count by a first count value; after performing a second read operation, incrementing the read count by a second count value; wherein the first count value is less than the second count value.

[0099] For example, the first count value is 0.7, meaning that the counter value increases by 0.7 after each first read operation. The first count value can also be set according to actual conditions, such as 0.6, 0.8, etc. The second count value is 1, meaning that the counter value increases by 1 after each second read operation. In other embodiments, for both full and incomplete storage blocks, the counter value can increase by 1 after each read operation. Thus, in the above embodiments of this disclosure, when performing a first read operation on an incomplete storage block, setting the corresponding counter value to less than 1 can reduce the frequency and number of read scans, thereby reducing the number of checks on the corresponding storage block and improving the read performance and lifespan of incomplete storage blocks.

[0100] Based on this, in this embodiment of the disclosure, when performing the first read operation, a first pass voltage is applied to the non-selected word line (such as the first word line) adjacent to the selected word line to reduce the coupling effect between the selected word line and its adjacent word lines. Simultaneously, a third conduction voltage is applied to the non-selected word line (such as the third word line) coupled to the unprogrammed memory cell, which can reduce read interference caused by the first read operation to the unprogrammed memory cell, thereby improving the read performance and reliability of the memory device. Furthermore, in this embodiment of the disclosure, the counter value after each first read operation is set to be less than the counter value after each second read operation. This reduces the frequency at which the counter value reaches a preset threshold when counting the number of first read operations, reducing the number of read scans triggered, thereby improving the read performance and lifespan of the unwritten memory block.

[0101] To facilitate understanding, the following will be combined with... Figure 10 This disclosure will be further described in detail. Figure 10 This is a schematic diagram illustrating the read operation implementation process of a memory device according to an embodiment of this disclosure. Figure 10 As shown, after receiving the read command, step S1001 is executed, and the read operation begins.

[0102] In step S1002, the judgment module in the memory device, such as the judge, makes a judgment on the storage state of the currently selected memory block; and determines whether the storage state of the selected memory block is not full based on the detection result.

[0103] When the selected storage block is in a not-full state, step S1003 is executed to perform a first read operation on the selected storage block; and after each first read operation, the counter value is incremented by a first count value, such as 0.7.

[0104] When the selected storage block is in a full state, step S1004 is executed to perform a second read operation on the selected storage block; and after each second read operation, the counter value is incremented by a second count value, such as 1.

[0105] After the first or second read operation is completed, step S1005 is executed, and the read operation ends.

[0106] Based on the above-described operation method of the memory device, this disclosure also provides a memory device comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array comprising a plurality of memory blocks; each memory block comprising a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; the peripheral circuitry being configured to: when performing a first read operation on a memory cell coupled to a selected word line, apply a first through voltage to a first word line, apply a second through voltage to a second word line, and apply a third through voltage to a third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on the side of the first word line away from the selected word line, the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first through voltage, the second through voltage, and the third through voltage are all different.

[0107] In some embodiments, the first through voltage is greater than the second through voltage; the second through voltage is greater than the third through voltage.

[0108] In some embodiments, the peripheral circuit is further configured to: perform storage status detection on selected memory blocks; the storage status detection result includes full memory blocks and incomplete memory blocks; perform a first read operation on selected word-line coupled memory cells in incomplete memory blocks; and perform a second read operation on selected word-line coupled memory cells in full memory blocks.

[0109] In some embodiments, the peripheral circuitry is further configured to: apply a first pass voltage to a fourth word line and a second pass voltage to a fifth word line when performing a second read operation on a memory cell coupled to a selected word line in a filled memory block; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the first word line away from the selected word line.

[0110] In some embodiments, the peripheral circuit is further configured to: after performing a first read operation, increment the read count by a first count value; after performing a second read operation, increment the read count by a second count value; wherein the first count value is less than the second count value.

[0111] In some embodiments, when the first word line and the third word line are the same word line, a first pass voltage is applied to the same word line.

[0112] In some embodiments, a dummy word line is provided between at least two of the first word line, the second word line, and the third word line; the peripheral circuit is further configured to apply a second pass voltage to the dummy word line when performing a first read operation.

[0113] In some embodiments, the peripheral circuitry is further configured to: apply a read voltage to a selected word line during the execution of a first read operation; wherein the memory cell coupled to the selected word line is a programmed memory cell.

[0114] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0115] Based on the above-described memory devices and their operating methods, this disclosure also provides a memory system, including: one or more memory devices as described in the above embodiments of this disclosure; and a memory controller coupled to the memory devices for controlling the memory devices.

[0116] This disclosure also provides a storage medium storing executable instructions, which, when executed by a peripheral circuit, can implement the steps of the method described in the above embodiments of this disclosure.

[0117] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0118] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0119] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0120] It should be noted that terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0121] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, include: A memory cell array and peripheral circuitry coupled to the memory cell array; The storage cell array includes multiple storage blocks; each storage block includes multiple storage cells and multiple word lines coupled to the multiple storage cells; The peripheral circuit is configured as follows: When performing a first read operation on a memory cell coupled to a selected word line, a first pass voltage is applied to a first word line, a second pass voltage is applied to a second word line, and a third pass voltage is applied to a third word line; the first word line is at least one word line physically located above and below the selected word line. Both the second word line and the third word line are word lines whose physical location is on the side of the first word line away from the selected word line. The memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell. The first through voltage, the second through voltage, and the third through voltage are all different.

2. The memory device according to claim 1, characterized in that, The first through voltage is greater than the second through voltage; the second through voltage is greater than the third through voltage.

3. The memory device according to claim 2, characterized in that, The peripheral circuit is also configured to: Perform storage status detection on the selected storage blocks; the storage status detection results include full storage blocks and incomplete storage blocks; The first read operation is performed on the selected word-line-coupled memory cell in the unfilled memory block; A second read operation is performed on the selected word-line-coupled memory cell in the filled memory block.

4. The memory device according to claim 3, characterized in that, The peripheral circuit is also configured to: When performing the second read operation on the memory cell coupled to the selected word line in the filled memory block, the first pass voltage is applied to the fourth word line and the second pass voltage is applied to the fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

5. The memory device according to claim 4, characterized in that, The peripheral circuit is also configured to: After performing the first read operation, the read count is incremented by a first count value; after performing the second read operation, the read count is incremented by a second count value; the first count value is less than the second count value.

6. The memory device according to claim 1, characterized in that, When the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

7. The memory device according to claim 1, characterized in that, A dummy character line is provided between at least any two of the first character line, the second character line, and the third character line; The peripheral circuit is also configured to: When the first read operation is performed, the second pass voltage is applied to the dummy word line.

8. The memory device according to claim 1, characterized in that, The peripheral circuit is also configured as follows: During the execution of the first read operation, a read voltage is applied to the selected word line; The selected word-line coupled memory cell is a programmed memory cell.

9. The memory device according to claim 1, characterized in that, The memory device includes a three-dimensional NAND type memory.

10. A memory system, characterized in that, include: One or more memory devices as described in any one of claims 1 to 9; as well as A memory controller, coupled to the memory device, for controlling the memory device.

11. A method of operating a memory device, characterized in that, The operation method includes: When performing a first read operation on a memory cell coupled to a selected word line, a first pass voltage is applied to a first word line, a second pass voltage is applied to a second word line, and a third pass voltage is applied to a third word line; the first word line is at least one word line physically located above and below the selected word line; the second word line and the third word line are both word lines physically located on the side of the first word line away from the selected word line; the memory cell coupled to the second word line is a programmed memory cell, and the memory cell coupled to the third word line is an unprogrammed memory cell; the first pass voltage, the second pass voltage, and the third pass voltage are all different; The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks; each memory block includes multiple memory cells and multiple word lines coupled to the multiple memory cells.

12. The operating method according to claim 11, characterized in that, The first through voltage is greater than the second through voltage; the second through voltage is greater than the third through voltage.

13. The operating method according to claim 12, characterized in that, The operation method further includes: Perform storage status detection on the selected storage blocks; the storage status detection results include full storage blocks and incomplete storage blocks; The first read operation is performed on the selected word-line-coupled memory cell in the unfilled memory block; A second read operation is performed on the selected word-line-coupled memory cell in the filled memory block.

14. The operating method according to claim 13, characterized in that, The operation method further includes: When performing the second read operation on the memory cell coupled to the selected word line in the filled memory block, the first pass voltage is applied to the fourth word line and the second pass voltage is applied to the fifth word line; the fourth word line is at least one word line physically located above and below the selected word line; the fifth word line is all word lines physically located on the side of the fourth word line away from the selected word line.

15. The operating method according to claim 14, characterized in that, The operation method further includes: After performing the first read operation, the read count is incremented by a first count value; after performing the second read operation, the read count is incremented by a second count value; the first count value is less than the second count value.

16. The operating method according to claim 11, characterized in that, When the first word line and the third word line are the same word line, the first pass voltage is applied to the same word line.

17. The operating method according to claim 11, characterized in that, A dummy character line is provided between at least any two of the first character line, the second character line, and the third character line; The operation method further includes: When the first read operation is performed, the second pass voltage is applied to the dummy word line.

18. The operating method according to claim 11, characterized in that, The operation method further includes: During the execution of the first read operation, a read voltage is applied to the selected word line; The selected word-line coupled memory cell is a programmed memory cell.

19. A storage medium, characterized in that, The storage medium stores executable instructions, which, when executed by the memory controller, can implement the steps of the method as described in any one of claims 11-18.

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