Decoding method and storage device

Abstract

The invention provides a decoding method and a storage device. The method comprises the following steps: sending a reading instruction sequence to a memory module, wherein the reading instruction sequence indicates to read first data from a first entity unit in the memory module; after the first data is obtained, decoding operation is performed on the first data, and the decoding operation comprises the following steps: obtaining channel information corresponding to the first data; executing channel information updating operation to update the channel information; determining a numerical interval to which the first type of channel information in the channel information belongs according to the execution condition of the channel information updating operation; obtaining a correction factor corresponding to the numerical value interval; and reflecting the correction factor into the channel information updating operation. Therefore, the decoding efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory control, and in particular to a decoding method and a storage device. Background Art

[0002] In solid-state storage devices (SSDs), due to the characteristics of their internal flash memory technology, data is susceptible to various types of errors during storage, especially bit flip errors, which requires the memory controller to integrate error checking and correction (ECC) circuits to ensure data integrity.

[0003] In solid-state drives (SSDs), the Error Correction Code (ECC) circuit is a key component used to detect and correct bit errors that occur within storage cells. The ECC circuit adds redundant information to the original data, allowing the memory controller to detect and repair a certain number of bit errors when reading data, thereby maintaining data integrity and reliability. Although the ECC circuit can significantly improve data reliability, its correction capability is upper bounded, i.e., the ECC circuit can only correct the number of erroneous bits within a specific range. If the errors occurring in a certain storage block exceed the maximum error rate that the ECC algorithm can tolerate (usually referred to as the "erasure correction capability" of the erasure code), then even with the existence of the ECC mechanism, the data of the block cannot be recovered, which will result in irrecoverable data loss.

[0004] Therefore, how to improve the error correction efficiency of the storage device for the stored data is a problem that needs to be solved urgently. Summary of the invention

[0005] The invention provides a decoding method and a storage device, which can improve the decoding efficiency of the storage device.

[0006] An embodiment of the present invention provides a decoding method, which is used for a storage device, wherein the storage device includes a memory module, and the decoding method includes: sending a read instruction sequence to the memory module, wherein the read instruction sequence indicates reading first data from a first physical unit in the memory module; after obtaining the first data, performing a decoding operation on the first data, wherein the decoding operation includes: step a: obtaining channel information corresponding to the first data; step b: performing a channel information update operation to update the channel information; step c: determining a numerical interval to which a first type of channel information in the channel information belongs according to the execution status of the channel information update operation; step d: obtaining a correction factor corresponding to the numerical interval; and step e: reflecting the correction factor in the channel information update operation to affect the decoding result of the decoding operation on the first data.

[0007] The embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: send a read instruction sequence to the memory module, wherein the read instruction sequence indicates to read first data from a first physical unit in the memory module; after obtaining the first data, perform a decoding operation on the first data, wherein the decoding operation includes: step a: obtaining channel information corresponding to the first data; step b: performing a channel information update operation to update the channel information; step c: determining the numerical interval to which the first type of channel information in the channel information belongs according to the execution status of the channel information update operation; step d: obtaining a correction factor corresponding to the numerical interval; and step e: reflecting the correction factor in the channel information update operation to affect the decoding result of the decoding operation on the first data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of verifying a bit sequence in first data according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of a message transmission structure according to an embodiment of the present invention;

[0013] Figure 6 is a flowchart of a decoding method according to an embodiment of the present invention;

[0014] Figure 7 is a flowchart of a decoding method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash storage (Universal Flash Storage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions and / or data).

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0021] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0025] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0026] In one embodiment, a physical unit may include one or more physical programming units. In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0027] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0028] In one embodiment, a physical erase unit may include a plurality of physical programming units. A plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to a plurality of physical programming units in the physical erase unit to change the threshold voltage of at least a portion of the storage cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared. In one embodiment, a physical erase unit may be regarded as a physical block.

[0029] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0030] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0033] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0035] In one embodiment, the memory control circuit 23 may send a read instruction sequence to the memory module 122. The read instruction sequence may be used to instruct to read data (also referred to as first data) from at least one physical unit (also referred to as a first physical unit) in the memory module 122. For example, the read instruction sequence may carry address information corresponding to the first physical unit. The memory module 122 may perform data read on the first physical unit according to the read instruction sequence to obtain the first data. For example, according to the read instruction sequence, the memory module 122 may apply at least one read voltage level to each storage unit in the first physical unit to read the first data. Then, the memory module 122 may transmit the read first data to the memory control circuit 23.

[0036] In one embodiment, after obtaining the first data, the memory control circuit 23 may perform a decoding operation on the first data through the decoding circuit 25. This decoding operation may be used to attempt to correct errors (i.e., error bits) in the first data. In the following embodiment, it is assumed that the decoding circuit 25 performs a decoding operation on the first data based on a low-density parity check code (LDPC code). In one embodiment, the decoding circuit 25 may also perform a decoding operation on the first data based on other types of decoding algorithms, which are not limited by the present invention.

[0037] In one embodiment, the first data includes a bit sequence. The bit sequence includes a plurality of bits. After obtaining the first data, based on a low-density parity check code, a matrix (also referred to as a check matrix) can be used to verify the bit sequence in the first data to determine whether there is an error (i.e., an error bit) in the bit sequence.

[0038] In one embodiment, if the following formula (1.1) holds true, it means that the bit sequence is a valid codeword and there is no error in the bit sequence. However, if the following formula (1.1) does not hold true, it means that the bit sequence is not a valid codeword and there is an error in the bit sequence.

[0039]

[0040] In formula (1.1), H is used to represent a check matrix, and X is used to represent a bit sequence in the first data.

[0041] Figure 4 FIG. 1 is a schematic diagram of verifying a bit sequence in first data according to an embodiment of the present invention. Figure 4 , assuming that matrix 41 is a check matrix, and bit sequence 42 is a bit sequence in the first data. For example, bit sequence 42 includes bits V(1) to V(8). After performing modulo 2 matrix multiplication (mod 2) on matrix 41 and bit sequence 42 according to formula (1.1), vector 43 can be obtained.

[0042] In one embodiment, vector 43 includes elements S(1) to S(3). If elements S(1) to S(3) are all "0" (i.e., vector 43 is a zero vector), it indicates that bit sequence 42 is a valid codeword and there is no error in bit sequence 42. However, if at least one of elements S(1) to S(3) is not "0" (i.e., vector 43 is not a zero vector), it indicates that bit sequence 42 is not a valid codeword and there is an error in bit sequence 42.

[0043] It should be noted that Figure 4The matrix 41, bit sequence 42 and vector 43 are all examples and are not intended to limit the present invention. In one embodiment, the formats of the matrix 41, bit sequence 42 and vector 43 can be adjusted according to practical requirements.

[0044] In one embodiment, if there is no error (i.e., error bit) in the first data, the memory control circuit 23 may output the first data. For example, assuming that the first data is the data instructed to be read by the host system 11, the memory control circuit 23 may transmit the first data to the host system 11. Alternatively, the first data may also be used for other purposes, such as garbage collection (GC), etc., which is not limited by the present invention. However, if there is an error (i.e., error bit) in the first data, the decoding circuit 25 may attempt to correct the error (i.e., error bit) in the first data by performing the decoding operation.

[0045] Figure 5 Schematic diagram of a message transmission structure according to an embodiment of the present invention. Figure 5 In the decoding operation of the low-density parity-check code, channel information is transmitted and updated based on the message passing structure 51. For example, in the message passing structure 51, the channel information R(km) is used to represent the channel information transmitted from the variable node 502(k) to the check node 501(m), the channel information Q(mn) is used to represent the channel information transmitted from the check node 501(m) to the variable node 502(n), and so on.

[0046] In one embodiment, the connection (or connection relationship) between the check nodes 501 (1) to 501 (j) and the variable nodes 502 (1) to 502 (p) in the message passing structure 51 may correspond to the position of the element "1" in the aforementioned check matrix. For example, if the element at the position of the mth row and the kth column in the check matrix is ​​"1", then there may be a connection (or connection relationship) between the check node 501 (m) and the variable node 502 (k). In addition, each bit in the first data may correspond to the variable nodes 502 (1) to 502 (p), respectively.

[0047] In one embodiment, in the decoding operation of the low-density parity check code, after each iteration, the channel information can be transmitted and updated once along each line (or connection relationship) in the message transmission structure 51. Taking the channel information Q (mn) as an example, the channel information Q (mn) can be updated according to the following formula (1.2) and transmitted to the variable node 502 (n).

[0048]

[0049] In formula (1.2), N(m) is used to represent the set of all variable nodes connected to the check node 501(m). In addition, sing(R(km)) is used to represent whether the channel information R(km) is a positive number or a negative number.

[0050] In one embodiment, each bit in the first data may be decoded as "1" or "0" in each iteration according to the updated channel information. Taking variable node 502(n) as an example, the bit corresponding to variable node 502(n) may be decoded according to the following formula (1.3).

[0051]

[0052] In formula (1.3), x(n) is used to represent the bit (eg, the nth bit) corresponding to the variable node 502 (n) in the first data, and Ly(n) is used to represent the current channel information corresponding to x(n).

[0053] In one embodiment, in the decoding operation, after each iteration, the decoded first data can be confirmed whether it is a valid codeword. If the decoded first data becomes a valid codeword, the decoding operation can be stopped. However, if the decoded first data is still not a valid codeword, the next iteration can be performed. In addition, if the number of iterations of the decoding operation performed on the first data reaches (e.g., is the same as or greater than) a critical number (also referred to as the first critical number), the decoding operation for the first data can be forced to stop.

[0054] In one embodiment, in a low density parity check code, the channel information includes a log likelihood ratio (LLR). However, for other algorithms, the data type or format of the channel information can be adjusted according to practical needs, and the present invention is not limited thereto.

[0055] It should be noted that in the traditional LDPC decoding algorithm, the update amplitude of the check node for the channel information is ignored, resulting in the check node's update value for the channel information being often too large, thereby affecting the decoding performance. For example, according to statistics, when the update value of the check node for the channel information is too large, it is easy to cause a relatively high bit error rate in the current decoding. In addition, when the update value of the check node for the channel information is too large, it is also easy to cause the iterative convergence speed in the current decoding process to be slow, thereby reducing the decoding efficiency. However, through the decoding method proposed in the embodiment of the present invention, the above problems can be effectively improved, thereby improving the decoding efficiency of the storage device 12.

[0056] In one embodiment, after obtaining the first data from the memory module 122, the memory control circuit 23 may synchronously obtain channel information corresponding to the first data (also referred to as initial channel information). In a decoding operation for the first data, the memory control circuit 23 may perform an update operation (also referred to as a channel information update operation) to update the channel information. For example, in a decoding operation for the first data, starting from the initial channel information, the memory control circuit 23 may continuously update the channel information according to each iteration. The decoding circuit 25 may decode the first data based on the updated channel information. For details on the channel information update operation and the decoding operation for the first data, please refer to Figure 5 The embodiments of the present invention will not be repeated here.

[0057] In one embodiment, after starting to decode the first data, the memory control circuit 23 may continuously record the execution status of the channel information update operation. According to the execution status of the channel information update operation, the memory control circuit 23 may determine the value interval to which a specific type of channel information (also referred to as the first type of channel information) in the channel information belongs. For example, the first type of channel information is the channel information transmitted from the variable node to the check node in the executed decoding operation. Figure 5 For example, the first type of channel information may include channel information R(km) transmitted from variable node 502(k) to check node 501(m). In one embodiment, the execution status of the channel information update operation may reflect the distribution status of the values ​​of the first type of channel information transmitted in the first few iterations of the decoding operation.

[0058] In one embodiment, according to the execution status of the channel information update operation, the memory control circuit 23 can obtain the value distribution interval of the first type of channel information. For example, this value distribution interval can be defined by the maximum value and the minimum value of the first type of channel information transmitted in the previous rounds of iterations in the decoding operation. For example, the memory control circuit 23 can determine the upper limit value and the lower limit value of this value distribution interval according to the maximum value and the minimum value of the first type of channel information transmitted in the previous rounds of iterations. According to the execution status of the channel information update operation recorded under different channel conditions, the value distribution interval of the first type of channel information can be dynamically changed (i.e., not a fixed interval).

[0059] In one embodiment, after obtaining the numerical distribution interval of the aforementioned first-category channel information, the memory control circuit 23 may divide the numerical distribution interval into a plurality of numerical intervals (also referred to as candidate numerical intervals). These candidate numerical intervals are all located within the aforementioned numerical distribution interval and do not overlap with each other. For example, the memory control circuit 23 may divide the numerical distribution interval into three candidate numerical intervals in sequence based on 25%, 50% and 75% of the numerical range of the numerical distribution interval. These three candidate numerical intervals may respectively cover different numerical ranges within the numerical distribution interval. However, the division method of these candidate numerical intervals and / or the total number of divided candidate numerical intervals may also be adjusted according to practical needs, and the present invention is not limited thereto.

[0060] In one embodiment, after the numerical distribution interval is divided into the plurality of candidate numerical intervals, the memory control circuit 23 may determine the numerical interval to which the first type of channel information transmitted in the current iteration belongs from the plurality of candidate numerical intervals. For example, the memory control circuit 23 may compare the first type of channel information transmitted in the current iteration with at least one of the plurality of candidate numerical intervals to obtain a comparison result. Then, the memory control circuit 23 may determine the numerical interval to which the first type of channel information transmitted in the current iteration belongs based on the comparison result. For example, if the comparison result reflects that the numerical value of the first type of channel information transmitted in the current iteration is within a numerical interval (also referred to as a target numerical interval) among the plurality of candidate numerical intervals, the memory control circuit 23 may determine the target numerical interval as the numerical interval to which the first type of channel information belongs.

[0061] In one embodiment, after determining the numerical interval to which the first type of channel information belongs, the memory control circuit 23 may obtain a correction factor corresponding to the numerical interval. For example, after determining the numerical interval to which the first type of channel information belongs, the memory control circuit 23 may obtain a numerical value (also referred to as a target value) corresponding to the numerical interval (i.e., the target numerical interval) from a plurality of numerical values ​​(also referred to as candidate target values). For example, each candidate numerical interval may correspond to a unique correction factor. Then, the memory control circuit 23 may obtain the correction factor according to the target value and the first type of channel information.

[0062] In one embodiment, in response to the numerical interval (i.e., the target numerical interval) being a numerical interval (also referred to as the first numerical interval) among the aforementioned multiple candidate numerical intervals, the memory control circuit 23 may determine the candidate target value (also referred to as the first candidate target value) corresponding to the first numerical interval among the aforementioned multiple candidate numerical intervals as the target value. Alternatively, in response to the numerical interval (i.e., the target numerical interval) being another numerical interval (also referred to as the second numerical interval) among the aforementioned multiple candidate numerical intervals, the memory control circuit 23 may determine the candidate target value (also referred to as the second candidate target value) corresponding to the second numerical interval among the aforementioned multiple candidate numerical intervals as the target value. It should be noted that the first numerical interval is different from the second numerical interval, and the first candidate target value may be the same as or different from the second candidate target value.

[0063] In one embodiment, after obtaining the target value, the memory control circuit 23 may obtain an expected value information (also referred to as first expected value information) and another expected value information (also referred to as second expected value information) according to the target value and the first type of channel information. For example, the first expected value information may reflect the expected value of the product of the target value and the first type of channel information. For example, the second expected value information reflects the expected value of the square of the first type of channel information. Then, the memory control circuit 23 may obtain the correction factor according to the first expected value information and the second expected value information.

[0064] In one embodiment, the memory control circuit 23 may obtain the correction factor according to the following formula (2.1).

[0065]

[0066] In formula (2.1), T is used to represent the target value, E(1) is used to represent the first expected value information (i.e., the expected value of the product of the target value T and the first type of channel information transmitted in the current iteration), E(2) is used to represent the second expected value information (i.e., the expected value of the square of the first type of channel information transmitted in the current iteration), and β(t) is the correction factor obtained for the first type of channel information transmitted in the tth iteration. It should be noted that formula (2.1) can also be adjusted according to practical needs, and the present invention is not limited thereto.

[0067] In one embodiment, after obtaining the correction factor, the memory control circuit 23 may reflect the correction factor to the channel information update operation performed in the current decoding operation, so as to affect the decoding result of the first data in the decoding operation through the correction factor. For example, according to the correction factor, the memory control circuit 23 may adjust the update result of another type of channel information (also referred to as the second type of channel information) in the channel information update operation in the current iteration. For example, the second type of channel information is the channel information transmitted from the check node to the variable node in the decoding operation. Figure 5 For example, the second type of channel information may include channel information Q(mn) transmitted from the check node 501(m) to the variable node 502(n).

[0068] In one embodiment, after obtaining the correction factor, the memory control circuit 23 (or the decoding circuit 25) may obtain (or update) the second type of channel information according to the following formula (2.2).

[0069]

[0070] In one embodiment, by reflecting this correction factor in the channel information update operation performed in the current decoding operation (for example, according to formula (2.2), the correction factor β(t) can be used to adjust the update result of the second type of channel information Q(mn)), the technical problem that the decoding performance is traditionally affected by the excessive update value of the check node for the channel information can be improved, thereby improving the decoding efficiency of the storage device 12.

[0071] In one embodiment, after starting to perform the aforementioned decoding operation on the first data, the memory control circuit 23 may also obtain iteration number information, which may reflect the iteration number of the decoding operation that has been performed on the first data.

[0072] In one embodiment, the memory control circuit 23 may determine whether the iteration number information meets the preset condition. If the iteration number information meets the preset condition, the memory control circuit 23 may perform the aforementioned execution status of the channel information update operation, determine the value interval to which the first type of channel information in the channel information belongs, obtain the correction factor corresponding to the value interval, and reflect the correction factor in the channel information update operation to affect the operation of the decoding operation on the decoding result of the first data. However, if the iteration number information does not meet the preset condition, the memory control circuit 23 may not perform these operations to save system resources.

[0073] In one embodiment, the iteration number information may carry a count value. This count value may reflect the number of iterations of the decoding operation that has been performed on the first data since the start of the aforementioned decoding operation on the first data. In one embodiment, the memory control circuit 23 may compare this count value with a critical number (also referred to as a second critical number). It should be noted that the second critical number may be less than the aforementioned first critical number. If this count value reaches (e.g., is the same as or greater than) the second critical number, the memory control circuit 23 may determine that the iteration number information meets the preset condition. However, if this count value does not reach (e.g., is less than) the second critical number, the memory control circuit 23 may determine that the iteration number information does not meet the preset condition.

[0074] In one embodiment, only when the iteration number information meets the preset conditions, the correction factor is obtained in real time and reflected in the channel information update operation, which can ensure that the system only performs additional control on the channel information update operation through the correction factor after sufficient channel information is collected, avoiding hasty and invalid adjustment of the channel information when insufficient decoding information is collected in the early stage of decoding. In this way, in addition to saving system resources, the accuracy of the dynamically generated correction factor can be effectively improved, thereby further improving the decoding efficiency of the storage device 12.

[0075] Figure 6 is a flowchart of a decoding method according to an embodiment of the present invention. Figure 6 In step S610, a read instruction sequence is sent to the memory module, wherein the read instruction sequence indicates to read first data from a first physical unit in the memory module. After obtaining the first data, in step S620, a decoding operation is performed on the first data.

[0076] Specifically, the decoding operation includes steps S621 to S625. In step S621, the channel information corresponding to the first data is obtained. In step S622, the channel information update operation is performed to update the channel information. In step S623, the numerical interval to which the first type of channel information in the channel information belongs is determined according to the execution status of the channel information update operation. In step S624, a correction factor corresponding to the numerical interval is obtained. In step S625, the correction factor is reflected in the channel information update operation to affect the decoding result of the decoding operation on the first data.

[0077] Figure 7 is a flowchart of a decoding method according to an embodiment of the present invention. Figure 7In step S701, the first data is decoded according to the channel information. In step S702, it is determined whether the decoding of the first data is successful. If the decoding of the first data is successful, in step S703, the successfully decoded first data is output.

[0078] If the decoding of the first data fails, in step S704, it is determined whether the number of iterations of the current decoding operation reaches a first critical number. If the number of iterations has reached the first critical number, in step S705, it is determined that the iterative decoding of the first data has failed, and the decoding of the first data is stopped. In addition, in step S705, error processing may be performed continuously. For example, the error processing includes transmitting read failure information to the host system 11 and / or recording relevant information of the decoding failure, etc., which are not limited by the present invention.

[0079] On the other hand, if the number of iterations does not reach the first critical number, in step S706, it is determined whether the number of iterations of the current decoding operation reaches the second critical number. The second critical number may be less than the first critical number. If the number of iterations does not reach the second critical number, it is possible to return to step S701, update the channel information in the next iteration, and decode the first data according to the channel information.

[0080] On the other hand, if the number of iterations has reached the second critical number (i.e., the number of iterations is between the first critical number and the second critical number), then in step S707, the numerical interval to which the first type of channel information in the channel information belongs is determined according to the execution status of the channel information update operation. In step S708, a correction factor corresponding to the numerical interval is obtained. In step S709, the correction factor is reflected in the channel information update operation. Then, the process can also return to step S701, update the channel information in the next iteration, and decode the first data according to the channel information.

[0081] However, Figure 6 and Figure 7 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 6 and Figure 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 6 and Figure 7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0082] In summary, the decoding method and storage device proposed in the embodiment of the present invention can dynamically generate a correction factor that can be used to affect the channel information update operation according to the execution status of the channel information update operation. Therefore, the technical problem that the decoding performance is affected by the excessive update value of the check node for the channel information can be effectively improved, thereby improving the decoding efficiency of the storage device.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A decoding method, characterized in that: For use in a storage device, wherein the storage device comprises a memory module, and the decoding method comprises: Sending a read instruction sequence to the memory module, wherein the read instruction sequence instructs to read first data from a first physical unit in the memory module; After obtaining the first data, performing a decoding operation on the first data, The decoding operation includes: Step a: obtaining channel information corresponding to the first data; Step b: performing a channel information update operation to update the channel information; Step c: determining the numerical range to which the first type of channel information in the channel information belongs according to the execution status of the channel information update operation; Step d: obtaining a correction factor corresponding to the numerical range; and Step e: reflecting the correction factor into the channel information updating operation to affect the decoding result of the decoding operation on the first data. The decoding method according to claim 1 , wherein the channel information comprises a log-likelihood ratio value. 3 . The decoding method according to claim 1 , wherein the first type of channel information is channel information transmitted from a variable node to a check node in the decoding operation.

4. The decoding method according to claim 1, wherein the step of determining the numerical interval to which the first type of channel information in the channel information belongs according to the execution status of the channel information update operation comprises: According to the execution status of the channel information updating operation, obtaining a value distribution interval of the first type of channel information; Dividing the numerical distribution interval into a plurality of candidate numerical intervals, wherein the plurality of candidate numerical intervals are all located within the numerical distribution interval and do not overlap with each other; as well as The numerical interval to which the first-category channel information belongs is determined from the multiple candidate numerical intervals.

5. The decoding method according to claim 1, wherein the step of obtaining the correction factor corresponding to the numerical interval comprises: Obtaining a target value corresponding to the numerical range from a plurality of candidate target values; as well as The correction factor is obtained according to the target value and the first type of channel information.

6. The decoding method according to claim 5, wherein the step of obtaining the target value corresponding to the numerical interval comprises: In response to the numerical interval being a first numerical interval among a plurality of candidate numerical intervals, determining a first candidate target value among the plurality of candidate target values ​​corresponding to the first numerical interval as the target value; as well as In response to the numerical interval being a second numerical interval among the plurality of candidate numerical intervals, determining a second candidate target value among the plurality of candidate target values ​​corresponding to the second numerical interval as the target value, The first numerical interval is different from the second numerical interval, and the first candidate target value is different from the second candidate target value.

7. The decoding method according to claim 5, wherein the step of obtaining the correction factor according to the target value and the first type of channel information comprises: Obtaining first expected value information and second expected value information according to the target value and the first type of channel information; as well as The correction factor is obtained according to the first expected value information and the second expected value information. 8 . The decoding method according to claim 7 , wherein the first expected value information reflects an expected value of a product of the target value and the first type of channel information, and the second expected value information reflects an expected value of a square of the first type of channel information.

9. The decoding method according to claim 1, wherein the step of reflecting the correction factor into the channel information updating operation to affect the decoding result of the first data by the decoding operation comprises: adjusting, according to the correction factor, an update result of the second type of channel information in the channel information in the channel information update operation; The second type of channel information is channel information transmitted from the check node to the variable node in the decoding operation.

10. The decoding method according to claim 1, further comprising: Obtaining iteration number information, wherein the iteration number information reflects the number of iterations of the decoding operation that has been performed on the first data; as well as Steps c to e are executed only when the iteration number information meets the preset conditions.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory controller is used to: Sending a read instruction sequence to the memory module, wherein the read instruction sequence instructs to read first data from a first physical unit in the memory module; After obtaining the first data, performing a decoding operation on the first data, The decoding operation includes: Step a: obtaining channel information corresponding to the first data; Step b: performing a channel information update operation to update the channel information; Step c: determining the numerical range to which the first type of channel information in the channel information belongs according to the execution status of the channel information update operation; Step d: obtaining a correction factor corresponding to the numerical range; and Step e: reflecting the correction factor into the channel information updating operation to affect the decoding result of the decoding operation on the first data. The storage device according to claim 11 , wherein the channel information comprises a log-likelihood ratio value. 13 . The storage device according to claim 11 , wherein the first type of channel information is channel information transmitted from a variable node to a check node in the decoding operation.

14. The storage device according to claim 11, wherein the operation of determining the numerical range to which the first type of channel information in the channel information belongs according to the execution status of the channel information update operation comprises: According to the execution status of the channel information updating operation, obtaining a value distribution interval of the first type of channel information; Dividing the numerical distribution interval into a plurality of candidate numerical intervals, wherein the plurality of candidate numerical intervals are all located within the numerical distribution interval and do not overlap with each other; as well as The numerical interval to which the first-category channel information belongs is determined from the multiple candidate numerical intervals.

15. The storage device according to claim 11, wherein the operation of obtaining the correction factor corresponding to the numerical range comprises: Obtaining a target value corresponding to the numerical range from a plurality of candidate target values; as well as The correction factor is obtained according to the target value and the first type of channel information.

16. The storage device according to claim 15, wherein the operation of obtaining the target value corresponding to the numerical interval comprises: In response to the numerical interval being a first numerical interval among a plurality of candidate numerical intervals, determining a first candidate target value among the plurality of candidate target values ​​corresponding to the first numerical interval as the target value; as well as In response to the numerical interval being a second numerical interval among the plurality of candidate numerical intervals, determining a second candidate target value among the plurality of candidate target values ​​corresponding to the second numerical interval as the target value, The first numerical interval is different from the second numerical interval, and the first candidate target value is different from the second candidate target value.

17. The storage device according to claim 15, wherein the operation of obtaining the correction factor according to the target value and the first type of channel information comprises: Obtaining first expected value information and second expected value information according to the target value and the first type of channel information; as well as The correction factor is obtained according to the first expected value information and the second expected value information. 18 . The storage device according to claim 17 , wherein the first expected value information reflects an expected value of a product of the target value and the first type of channel information, and the second expected value information reflects an expected value of a square of the first type of channel information.

19. The storage device according to claim 11, wherein the operation of reflecting the correction factor into the channel information update operation to affect the decoding result of the first data by the decoding operation comprises: adjusting, according to the correction factor, an update result of the second type of channel information in the channel information in the channel information update operation; The second type of channel information is channel information transmitted from the check node to the variable node in the decoding operation.

20. The storage device according to claim 11, wherein the memory controller is further configured to: Obtaining iteration number information, wherein the iteration number information reflects the number of iterations of the decoding operation that has been performed on the first data; and Only when the iteration number information meets the preset conditions, operations c to e are performed.

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