Semiconductor Structure and Method of Manufacturing the Same

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. After forming a first doped region at the bottom of a first trench, a first filling layer with inclined sidewalls is formed on the first doped region. The inclined sidewalls gradually extend from the notch of the first trench towards the bottom of the trench. A first ion is implanted into the inclined sidewalls to form a second doped region on the inclined sidewalls. The second doped region gradually extends from the notch of the first trench towards the bottom of the trench. Then, a second filling layer is deposited to cover the second doped region and fill the first trench. A third doped region is formed on the top of the second filling layer. Then, thermal annealing is performed to push and diffuse the first ions in the first doped region, the second doped region, and the third doped region into the first filling layer and the second filling layer, so as to form a semiconductor doped layer in the first trench. The second doped region increases the diffusion uniformity of the first ions. The first ions in the semiconductor doped layer are uniformly distributed, and the overall resistance of the semiconductor doped layer is small, and the electrical performance of the semiconductor structure is better.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] A power management integrated circuit (PMIC) is an integrated circuit chip that integrates multiple power management functions. It is a key component specifically used to manage and distribute power in electronic devices. It can perform power conversion and also undertakes important tasks such as power management, battery management, and protection mechanisms.

[0003] Power management integrated circuits need to form deep trenches through the Deep Trench Oxide Isolation (DTI) process, and fill the deep trenches with a boron-doped polysilicon layer to connect with the bottom substrate to achieve the electrostatic discharge (ESD) function. The application of the polysilicon layer boron doping process is relatively rare, and the cost of configuring a boron-doped polysilicon machine for the DTI polysilicon layer is too high. At present, the process of making a boron-doped polysilicon layer in a deep trench using an ion doping process is limited, and the concentration of boron ions doped in the polysilicon is uneven, resulting in unstable polysilicon resistance; and due to the limited ion diffusion distance, the ion diffusion in the middle of the polysilicon is small, resulting in a very large overall polysilicon resistance, which is not conducive to conduction. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same to address the problem in the prior art of manufacturing a boron-doped polysilicon layer in a deep trench, where the concentration of boron ions doped in the polysilicon is uneven, resulting in unstable resistance of the polysilicon.

[0005] In a first aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0006] providing a substrate, wherein the substrate is formed with a first trench;

[0007] Implanting first ions into the bottom of the first trench to form a first doped region;

[0008] forming a first filling layer, wherein the first filling layer covers the first doping region and fills a portion of the first trench, the first filling layer having an inclined sidewall, and the inclined sidewall extends from a notch of the first trench to a bottom of the first trench;

[0009] Implanting first ions into the inclined sidewall to form a second doping region;

[0010] forming a second filling layer, wherein the second filling layer covers the second doping region and fills an unfilled region of the first trench;

[0011] Implanting first ions on the top of the second filling layer to form a third doping region;

[0012] Annealing treatment is performed to diffuse first ions in the first doping region, the second doping region, and the third doping region into the first filling layer and the second filling layer, so as to form a semiconductor doping layer in the first trench.

[0013] Optionally, forming a first filling layer includes:

[0014] Depositing a first filling material layer to fill the first trench, wherein the first filling material layer forms a filling gap in the first trench;

[0015] The first filling material layer is obliquely etched to form the inclined sidewall and remove the filling gap, and the retained first filling material layer is etched to form the first filling layer.

[0016] Optionally, during the process of obliquely etching the first filling material layer, the oblique etching angle is gradually reduced, and the inclined sidewall is formed into a concave surface that is sunken toward the bottom of the groove.

[0017] Optionally, in the second doping region formed by implanting the first ions into the inclined sidewall, a concentration of the first ions on a side close to the groove bottom is greater than a concentration of the first ions on a side close to the groove opening.

[0018] Optionally, the depth of the first filling material layer being obliquely etched is less than the depth of the first groove, and while forming the inclined sidewall, a first plane connected to the inclined sidewall is formed; and the second filling layer covers the inclined sidewall and the first plane.

[0019] Optionally, before forming the first doped region, an insulating layer covering the sidewalls of the first trench is formed.

[0020] Optionally, the implantation concentration of the first ions in the first doping region is greater than 1×10 15 ion / cm 2 , the implantation concentration of the first ions in the second doping region is greater than 1×10 15 ion / cm 2 The implantation concentration of the first ions in the third doping region is greater than 1×10 15 ion / cm 2 ;

[0021] The implantation concentration of the first ions in the second doping region is greater than the implantation concentration of the first ions in the first doping region and the implantation concentration of the first ions in the third doping region.

[0022] Optionally, the annealing treatment is performed at a temperature of 900° C.-1200° C. and lasts for 2 min-120 min.

[0023] Optionally, the first ions include boron ions.

[0024] In a second aspect, the present disclosure provides a semiconductor structure, comprising:

[0025] a substrate having a first trench;

[0026] A semiconductor doping layer is filled in the first groove, the semiconductor doping layer is doped with first ions, the semiconductor doping layer includes a first filling layer doped with the first ions and a second filling layer doped with the first ions, the first filling layer covers the bottom surface of the first groove and fills part of the first groove, the first filling layer has an inclined side wall, the inclined side wall extends from the notch of the first groove to the bottom of the first groove, and the second filling layer covers the inclined side wall and fills the area of ​​the first groove not filled by the first filling layer.

[0027] Optionally, the inclined sidewall is a concave surface that is recessed toward the bottom surface of the first groove.

[0028] Optionally, the second filling layer continuously covers the inclined sidewall of the first filling layer, and the semiconductor doping layer has no filling gap.

[0029] The unexpected technical effect of the present disclosure is: after forming a first doping region at the bottom of the first trench, covering and filling part of the first trench on the first doping region to form a first filling layer with an inclined sidewall, the inclined sidewall gradually extends from the notch of the first trench to the bottom of the trench, first ions are injected into the inclined sidewall, and a second doping region is formed on the inclined sidewall, the second doping region gradually extends from the notch of the first trench to the bottom of the trench, and then a second filling layer is deposited to cover the second doping region and fill the first trench, and a third doping region is formed on the top of the second filling layer, and then thermal annealing is performed to promote the diffusion of the first ions of the first doping region, the second doping region, and the third doping region into the first filling layer and the second filling layer to form a semiconductor doping layer in the first trench, the second doping region increases the diffusion uniformity of the first ions, the first ions of the semiconductor doping layer are evenly distributed, the overall resistance of the semiconductor doping layer is small, and the electrical performance of the semiconductor structure is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 is a process flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0032] Figure 2 A schematic structural diagram of a substrate provided in an embodiment, wherein a first groove is formed on the substrate;

[0033] Figure 3 is a schematic diagram of a structure after forming an insulating layer and a first doping region provided in an embodiment;

[0034] Figure 4 is a schematic diagram of a structure after a first filling material layer is formed provided in an embodiment;

[0035] Figure 5 A schematic diagram of a structure after a first filling layer is formed provided in an embodiment;

[0036] Figure 6 A schematic diagram of a structure after a second doping region is formed on an inclined sidewall provided in an embodiment;

[0037] Figure 7 A schematic diagram of a structure after a second filling layer is formed to fill an unfilled area of ​​the first trench provided in an embodiment;

[0038] Figure 8 is a schematic diagram of a structure after a third doping region is formed on top of the second filling layer provided in an embodiment;

[0039] Fig. 9 is a schematic diagram of a semiconductor structure formed in one embodiment;

[0040] Fig.10 A schematic diagram of a structure after a first filling layer is formed provided in another embodiment;

[0041] Fig.11 A schematic diagram of a structure after forming a first filling layer provided in another embodiment;

[0042] Fig.12 It is a schematic diagram of the structure after forming the first filling layer provided in yet another embodiment.

[0043] Description of reference numerals:

[0044] 11. substrate; 12. first trench; 13. insulating layer; 21. first doped region; 22. second doped region; 23. third doped region; 31. first filling layer; 31a. first filling material layer; 310. inclined side wall; 3101. first inclined plane; 3102. second inclined plane; 312. first plane; 32. second filling layer; 30. semiconductor doped layer; 40. filling gap. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0047] Power management integrated circuits need to form deep trenches through the deep trench isolation (DTI) process, and fill the deep trenches with boron-doped polysilicon layers to connect with the bottom substrate to achieve electrostatic discharge (ESD) function. The application of polysilicon layer boron doping process is relatively rare, and it is too expensive to configure a boron-doped polysilicon machine for DTI polysilicon layer boron doping.

[0048] In the related technology, the filling process of deep trench isolation is to first inject ions (Ion Implantation, IMP) at the bottom of the deep trench, then fill it with non-doped polysilicon (poly), and then inject ions at the top of the polysilicon, and then diffuse it at ultra-high temperature and ultra-long time (drive in) so that the ions at the bottom and top of the deep trench diffuse into the polysilicon to achieve the purpose of polysilicon doping and conduction. This method requires ultra-high temperature and ultra-long time high temperature diffusion (1200℃, 900min can only diffuse 12μm), which can easily cause other devices to fail, and due to the limited diffusion distance, the ion diffusion in the middle of the polysilicon filling layer is small, resulting in a very large overall polysilicon resistance, which is not conducive to conduction. In addition, the top area of ​​the deep trench filled with polysilicon (the maximum aspect ratio is 40:1) is prone to premature closing to produce void / crack defects (Void / Seam defect), resulting in unstable resistance.

[0049] According to an exemplary embodiment, this embodiment provides a method for manufacturing a semiconductor structure, such as Figure 1A process flow chart of a method for manufacturing a semiconductor structure is shown, Figure 1 As shown, the method for manufacturing a semiconductor structure comprises the following steps:

[0050] Step S10: providing a substrate, wherein a first groove is formed on the substrate;

[0051] Step S20: implanting first ions into the bottom of the first trench to form a first doped region;

[0052] Step S30: forming a first filling layer, the first filling layer covers the first doping region and fills a portion of the first trench, the first filling layer has an inclined sidewall, and the inclined sidewall extends from the notch of the first trench to the bottom of the first trench;

[0053] Step S40: injecting first ions into the inclined sidewall to form a second doping region;

[0054] Step S50: forming a second filling layer, wherein the second filling layer covers the second doping region and fills an unfilled region of the first trench;

[0055] Step S60: implanting first ions on the top of the second filling layer to form a third doping region;

[0056] Step S70: Annealing treatment to diffuse the first ions in the first doping region, the second doping region and the third doping region into the first filling layer and the second filling layer, so as to form a semiconductor doping layer in the first trench.

[0057] The manufacturing method of the semiconductor structure of the present embodiment is as follows: after forming a first doping region at the bottom of a first trench, the first doping region is covered and filled with a portion of the first trench to form a first filling layer with an inclined sidewall, the inclined sidewall gradually extends from the notch of the first trench to the bottom of the trench, first ions are injected into the inclined sidewall, a second doping region is formed on the inclined sidewall, the second doping region gradually extends from the notch of the first trench to the bottom of the trench, then a second filling layer is deposited to cover the second doping region and fill the first trench, a third doping region is formed on the top of the second filling layer, and then thermal annealing is performed to promote the diffusion of the first ions of the first doping region, the second doping region, and the third doping region into the first filling layer and the second filling layer to form a semiconductor doping layer in the first trench, the second doping region increases the diffusion uniformity of the first ions, the first ions of the semiconductor doping layer are evenly distributed, the overall resistance of the semiconductor doping layer is small, and the electrical performance of the semiconductor structure is better.

[0058] Figure 2-Figure 12 Schematic diagrams showing various stages of a method for manufacturing a semiconductor structure of some embodiments of this example are shown below. Figure 2-Figure 12 The manufacturing methods of the semiconductor structures of some embodiments of this example are introduced.

[0059] In step S10, referring to Figure 2 As shown, the substrate 11 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. In this embodiment, the substrate 11 is a silicon substrate.

[0060] Conductive ions are doped in the substrate 11. The substrate 11 can be a P-type substrate or an N-type substrate. When the substrate is a P-type substrate, the doped ions are trivalent ions such as boron (B), aluminum (Al), gallium (Ga) or indium (In); when the substrate 11 is an N-type substrate, the doped ions are pentavalent ions such as phosphorus (P), arsenic (As) or antimony (Sb).

[0061] Reference Figure 2 As shown, the substrate 11 is formed with a first trench 12, a mask layer may be formed on the top surface of the substrate 11, the mask layer may be patterned to form a pattern of the first trench 12, and the substrate 11 may be etched according to the patterned mask layer to form the first trench 12. The aspect ratio of the first trench 12 is set according to actual production conditions, for example, it may be 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, etc.

[0062] In this embodiment, refer to Figure 3 As shown, before forming the first doping region 21, the following steps are performed: forming an insulating layer 13 covering the sidewalls of the first trench 12. The insulating layer 13 is used to protect the sidewalls of the first trench 12, define the structure of the semiconductor doping layer 30 formed in the first trench 12, and prevent the first ions from diffusing to the sidewalls of the first trench 12 to cause the size of the semiconductor doping layer 30 to increase, so as to improve the accuracy of the size of the semiconductor doping layer 30.

[0063] For example, the material of the insulating layer 13 may include silicon dioxide.

[0064] For example, the thickness of the insulating layer 13 may be 4000 angstroms to 6000 angstroms; for example, the thickness of the insulating layer 13 may be 4000 angstroms, 5000 angstroms, or 6000 angstroms.

[0065] The insulating layer 13 covering the sidewalls of the first trench 12 may be formed by using the following implementation: using tetraethylorthosilicate (TEOS) as a silicon source, a chemical vapor deposition (CVD) process is used to deposit the insulating layer 13, and the insulating layer 13 covers the sidewalls and bottom wall of the first trench 12. Then, the insulating layer 13 on the bottom wall of the first trench 12 is removed by etching back.

[0066] In step S20, refer to Figure 3 As shown, first ions are implanted into the substrate 11 exposed by the bottom wall of the first trench 12, and the insulating layer 13 on the sidewall of the first trench 12 blocks the first trench 12 from being implanted into other areas of the substrate 11, forming a first doping region 21 at the bottom of the first trench 12. For example, the first ions include boron ions.

[0067] For example, the first ions may be implanted with an energy of 20 KeV to form the first doping region 21 .

[0068] For example, the implantation concentration of the first ions in the first doping region 21 is greater than 1×10 15 ion / cm 2 For example, the implantation concentration of the first ions in the first doping region 21 may be 1×10 15 ion / cm 2 , 5×10 15 ion / cm 2 , 8×10 15 ion / cm 2 or 1×10 16 ion / cm 2 wait.

[0069] In step S30 , a first filling layer 31 partially filling the first trench 12 is formed in the first trench 12 . The first filling layer 31 has an inclined sidewall 310 extending from the notch of the first trench 12 to the bottom of the first trench 12 .

[0070] In this embodiment, forming the first filling layer 31 includes the following steps:

[0071] Step S301 : depositing a first filling material layer 31 a to fill the first trench 12 , wherein the first filling material layer 31 a forms a filling gap 40 in the first trench 12 ;

[0072] Reference Figure 4As shown, CVD deposition can be used to form the first filling material layer 31a, and the first filling material layer 31a includes amorphous silicon. The first filling material layer 31a covers the first doped region 21 and fills the first trench 12. In some embodiments, due to the large aspect ratio of the first trench 12, the first filling layer 31 forms a filling gap 40 in the first trench 12, and there is no semiconductor material at the filling gap 40.

[0073] Step S302 : etching the first filling material layer 31 a obliquely to form an inclined sidewall 310 and removing the filling gap 40 , and etching the retained first filling material layer 31 a to form a first filling layer 31 .

[0074] Reference Figure 5 As shown, plasma is used to etch the first filling material layer 31a. By controlling the bombardment angle of plasma, the plasma etches the first filling material layer 31a obliquely. It is blocked by the substrate 11. As the etching depth increases, the area of ​​the first filling material layer 31a that can be etched by the plasma gradually decreases, so that the formed first filling layer 31 has an inclined side wall 310.

[0075] In this embodiment, during the etching process of the first filling material layer 31 a , the filling gaps 40 in the first filling material layer 31 a can also be removed by etching, and the formed first filling layer 31 does not have the filling gaps 40 .

[0076] In this embodiment, the first filling material layer 31a is etched at a first preset angle, and the first preset angle is designed according to the first trench 12. For example, the first trench 12 has a depth-to-width ratio of 40:1, and the first preset angle is less than 1.4°.

[0077] It should be noted that the first preset angle refers to the angle between the etching angle of the plasma and the extension direction of the first trench 12 (the direction from the top surface to the bottom surface of the substrate 11 ).

[0078] In step S40, referring to Figure 6 As shown, first ions are implanted into the inclined sidewall 310 to form the second doping region 22. The implantation concentration of the first ions in the second doping region 22 is greater than 1×10 15 ion / cm 2 For example, the implantation concentration of the first ions in the second doping region 22 may be 1×10 15 ion / cm 2 , 5×10 15 ion / cm 2 , 8×10 15 ion / cm 2 or 1×10 16 ion / cm 2 wait.

[0079] In step S50, referring to Figure 7 As shown, CVD deposition can be used to form the second filling layer 32, which covers the inclined sidewall 310 and fills the unfilled area of ​​the first trench 12. The second filling layer 32 includes amorphous silicon.

[0080] It can be understood that part of the first groove 12 has been filled with the first filling layer 31, and the unfilled area of ​​the first groove 12 is reduced, which reduces the impact of the aspect ratio on the deposition process and reduces the difficulty of filling the second filling layer 32. There is no filling gap in the second filling layer 32 filled in the first groove 12.

[0081] In step S60, first, the second filling layer 32 on the top surface of the substrate 11 is polished and removed by chemical mechanical polishing (CMP). Figure 8 As shown, first ions are implanted into the second filling layer 32 at the opening of the first trench 12 to form the third doping region 23. For example, the first ions include boron ions.

[0082] For example, the implantation concentration of the first ions in the third doping region 23 is greater than 1×10 15 ion / cm 2 For example, the implantation concentration of the first ions in the third doping region 23 may be 1×10 15 ion / cm 2 , 5×10 15 ion / cm 2 , 8×10 15 ion / cm 2 or 1×10 16 ion / cm 2 wait.

[0083] In step S70, refer to Fig. 9 As shown, after the third doping region 23 is formed, a thermal annealing treatment is performed on the structure so that the first ions in the first doping region 21 diffuse into the first filling layer 31, the first ions in the second doping region 22 diffuse into the first filling layer 31 and the second filling layer 32 respectively, the first ions in the third doping region 23 diffuse into the second filling layer 32, and the crystal orientation of the amorphous silicon in the first filling layer 31 and the second filling layer 32 is rearranged to form polycrystalline silicon to form a semiconductor doping layer 30 in the first trench 12, the concentration of the first ions in each region of the semiconductor doping layer 30 is uniform, and the resistance of the semiconductor doping layer 30 is stable, which is beneficial to improving the electrical performance of the semiconductor structure.

[0084] For example, the thermal annealing process may be performed in a furnace.

[0085] The temperature of the annealing treatment is 900°C-1200°C, and the duration of the annealing treatment is 2min-120min.

[0086] For example, the temperature of the thermal annealing may be 900°C, 950°C, 1000°C, 1050°C, 1100°C, 1150°C, or 1200°C.

[0087] For example, the duration of thermal annealing can be 2 min, 4 min, 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min, 60 min, 80 min, 90 min, 100 min, 110 min or 120 min.

[0088] In some embodiments, the first trench 12 has a trench width of 1 um. When forming the second doping region 22, the first ions may be implanted with an energy of 20 KeV to reduce the doping depth of the second doping region 22 to less than 0.2 um. The second doping region 22 is positioned as close to the inclined sidewall 310 as possible to avoid the second doping region 22 having a too large doping range, which is beneficial to improving the doping uniformity of the first ions in the semiconductor doping layer 30 formed subsequently.

[0089] During the thermal annealing process, the annealing treatment can be performed at a temperature of 1100° C. for 45 minutes, and the diffusion size of the first ions is 1 μm, so that the semiconductor doping layer 30 with uniform distribution of the first ions can be obtained.

[0090] In some embodiments, the implantation concentration of the first ions in the second doping region 22 is greater than the implantation concentration of the first ions in the first doping region 21 and the implantation concentration of the first ions in the third doping region 23. This is beneficial to improve the concentration uniformity of the first ions in the semiconductor doping layer 30 formed in the first trench, so that the resistance of the semiconductor doping layer 30 is more stable.

[0091] In some embodiments, during the process of obliquely etching the first filling material layer 31 a , the oblique etching angle is gradually reduced, and the inclined sidewall 310 is formed into a concave surface that is sunken toward the bottom of the groove.

[0092] For example, the first filling material layer 31a may be obliquely etched at a first preset angle, and during the etching of the first filling material layer 31a, the oblique etching angle is reduced to a second preset angle, wherein the first preset angle is less than 1.4°, and the second preset angle is less than 1°.

[0093] In some examples, the first filling material layer 31a in the first trench 12 is etched at an angle of a first preset angle, and during the etching of the first filling material layer 31a, the etching angle is gradually reduced to a second etching angle. Fig.10 As shown, the formed inclined side wall 310 is a concave surface that is sunken toward the groove bottom, and the inclined side wall 310 is a curved surface.

[0094] In this way, the inclined side wall 310 is a concave surface that is sunken toward the bottom of the groove. The second doping region 22 formed by injecting the first ions into the inclined side wall 310 has a concentration of the first ions near the bottom of the groove greater than the concentration of the first ions near the groove mouth. The concentration distribution of the first ions in the semiconductor doping layer 30 formed by annealing is more uniform, the resistance of the semiconductor doping layer 30 is more stable, and the electrical performance of the semiconductor structure is better.

[0095] In some examples, reference Fig.11 As shown, the first filling material layer 31a in the first groove 12 can be etched at an inclined angle at a first preset angle, and after etching for a period of time, the etching angle is reduced to a second preset angle. In this way, the inclined sidewall 310 formed includes a first inclined surface 3101 and a second inclined surface 3102 connected in sequence, the first inclined surface 3101 extends from the notch of the first groove 12 to the direction of the groove bottom, the second inclined surface 3102 is connected to the extended end of the first inclined surface 3101, and the second inclined surface 3102 extends to the direction of the groove bottom. The inclination of the first inclined surface 3101 is greater than the inclination of the second inclined surface 3102, that is, the second inclined surface 3102 close to the groove bottom side is more gentle, and the inclined sidewall 310 is a concave surface that is concave toward the groove bottom.

[0096] In this way, the second doping region 22 is formed by injecting the first ions into the inclined side wall 310, the concentration of the first ions on the second inclined surface 3102 is greater than the concentration of the first ions on the first inclined surface 3101, the concentration distribution of the first ions in the semiconductor doping layer 30 formed by annealing is more uniform, the resistance of the semiconductor doping layer 30 is more stable, and the electrical performance of the semiconductor structure is better.

[0097] Moreover, the inclination of the second inclined surface 3102 is gentler than that of the first inclined surface 3101, which can further reduce the difficulty of the second filling layer 32 filling the first groove 12, avoid the second filling layer 32 from forming a filling gap at the corner of the inclined side wall 310, and avoid the gap causing the resistance of the semiconductor doping layer 30 to increase. The resistance of the semiconductor doping layer 30 is more stable and the electrical performance of the semiconductor structure is better.

[0098] In some embodiments, reference Fig.12 As shown, the depth of the first filling material layer 31a is obliquely etched less than the depth of the first trench 12, forming the inclined sidewall 310 and the first plane 312 connected to the inclined sidewall 310; the second filling layer 32 covers the inclined sidewall 310 and the first plane 312.

[0099] In this way, after the first filling layer 31 is formed in the first groove 12, the unfilled portion of the first groove 12 does not have a sharp angle, which is conducive to reducing the difficulty of filling the second filling layer 32. The second filling layer 32 covers the inclined side wall 310 and the first plane 312. The second filling layer 32 will not form a filling gap in the first groove 12, thereby avoiding the gap from causing the resistance of the semiconductor doping layer 30 to increase. The resistance of the semiconductor doping layer 30 is more stable, and the electrical performance of the semiconductor structure is better.

[0100] In some embodiments, the first ions include boron ions. In the method for manufacturing the semiconductor structure of this embodiment, a boron-doped semiconductor doping layer 30 can be formed in the first trench 12 with a relatively large depth and width without using a boron doping machine, and the boron ions in the semiconductor doping layer 30 are evenly distributed, the semiconductor doping layer 30 has a low resistance, and has better electrical conductivity.

[0101] According to an exemplary embodiment, referring to Fig. 9 As shown, this embodiment provides a semiconductor structure, and the semiconductor structure is manufactured using the manufacturing method of the semiconductor structure in the above embodiment.

[0102] Reference Fig. 9 As shown, the semiconductor structure provided in this embodiment includes a substrate 11 and a semiconductor doping layer 30; wherein the substrate 11 has a first trench 12, and the aspect ratio of the first trench 12 is set according to actual production conditions, for example, it can be 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, etc. The semiconductor doping layer 30 is filled in the first trench 12, and the semiconductor doping layer 30 is doped with first ions. The semiconductor doping layer 30 includes a first filling layer 31 doped with the first ions and a second filling layer 32 doped with the first ions. The first filling layer 31 covers the bottom surface of the first trench 12 and fills part of the first trench 12. The first filling layer 31 has an inclined sidewall 310, and the inclined sidewall 310 extends from the notch of the first trench 12 to the bottom of the first trench 12. The second filling layer 32 covers the inclined sidewall 310 and fills the area of ​​the first trench 12 that is not filled by the first filling layer 31.

[0103] In this way, the first ions are evenly distributed in the semiconductor doping layer 30 filling the first trench 12, the concentration of the first ions in each region of the semiconductor doping layer 30 is uniform, the resistance of the semiconductor doping layer 30 is stable, and the electrical performance of the semiconductor structure is better.

[0104] In some embodiments, reference Fig. 9 As shown, the second filling layer 32 continuously covers the inclined sidewall 310 of the first filling layer 31, and the semiconductor doping layer 30 has no filling gap, which is beneficial to further reduce the resistance of the semiconductor doping layer 30 and further improve the electrical performance of the semiconductor structure.

[0105] In some embodiments, reference Fig. 9 As shown, the semiconductor structure also includes an insulating layer 13, which covers the side walls of the first trench 12 and is arranged between the semiconductor doping layer 30 and the substrate 11. The insulating layer 13 is used to protect the side walls of the first trench 12, define the structure of the semiconductor doping layer 30 formed in the first trench 12, and prevent the first ions from diffusing to the side walls of the first trench 12 to cause the size of the semiconductor doping layer 30 to increase, so as to improve the accuracy of the size of the semiconductor doping layer 30.

[0106] For example, the material of the insulating layer 13 may include silicon dioxide.

[0107] In some embodiments, reference Fig.10 or Fig.11 As shown, the inclined sidewall 310 of the first filling layer 31 is a concave surface that is recessed toward the bottom of the first trench 12 .

[0108] In one example, referring to Fig.10 As shown, the inclined side wall 310 of the first filling layer 31 is a curved surface that is concave toward the bottom of the groove; in another example, referring to Fig.11 As shown, the inclined sidewall 310 of the first filling layer 31 is connected in sequence to a first inclined surface 3101 and a second inclined surface 3102, the first inclined surface 3101 extends from the notch of the first groove 12 toward the groove bottom, the second inclined surface 3102 is connected to the extended end of the first inclined surface 3101, and the second inclined surface 3102 extends toward the groove bottom. The inclination of the first inclined surface 3101 is greater than the inclination of the second inclined surface 3102.

[0109] In this way, the concave morphology of the first filling layer 31 reduces the difficulty of filling the second filling layer 32, and the second filling layer 32 will not form a filling gap in the first groove 12, thereby avoiding the gap causing the resistance of the semiconductor doping layer 30 to increase. The resistance of the semiconductor doping layer 30 is more stable and the electrical performance of the semiconductor structure is better.

[0110] In some embodiments, reference Fig.12 As shown, the first filling layer 31 further includes a first plane 312 connected to the inclined sidewall 310; the second filling layer 32 covers the inclined sidewall 310 and the first plane 312. In this way, the filling difficulty of the second filling layer 32 is reduced, the second filling layer 32 will not form a filling gap in the first trench 12, and the electrical performance of the semiconductor structure is better.

[0111] The unexpected technical effect of the present disclosure is: after forming a first doping region at the bottom of the first trench, covering and filling part of the first trench on the first doping region to form a first filling layer with an inclined sidewall, the inclined sidewall gradually extends from the notch of the first trench to the bottom of the trench, first ions are injected into the inclined sidewall, and a second doping region is formed on the inclined sidewall, the second doping region gradually extends from the notch of the first trench to the bottom of the trench, and then a second filling layer is deposited to cover the second doping region and fill the first trench, and a third doping region is formed on the top of the second filling layer, and then thermal annealing is performed to promote the diffusion of the first ions of the first doping region, the second doping region, and the third doping region into the first filling layer and the second filling layer to form a semiconductor doping layer in the first trench, the second doping region increases the diffusion uniformity of the first ions, the first ions of the semiconductor doping layer are evenly distributed, the overall resistance of the semiconductor doping layer is small, and the electrical performance of the semiconductor structure is better.

[0112] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate, wherein the substrate is formed with a first trench; Implanting first ions into the bottom of the first trench to form a first doped region; forming a first filling layer, wherein the first filling layer covers the first doping region and fills a portion of the first trench, the first filling layer having an inclined sidewall, and the inclined sidewall extends from a notch of the first trench to a bottom of the first trench; Implanting first ions into the inclined sidewall to form a second doping region; forming a second filling layer, wherein the second filling layer covers the second doping region and fills an unfilled region of the first trench; Implanting first ions on the top of the second filling layer to form a third doping region; Annealing treatment is performed to diffuse the first ions in the first doping region, the second doping region and the third doping region into the first filling layer and the second filling layer, so as to form a semiconductor doping layer in the first trench.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a first filling layer, comprising: Depositing a first filling material layer to fill the first trench, wherein the first filling material layer forms a filling gap in the first trench; The first filling material layer is obliquely etched to form the inclined sidewall and remove the filling gap, and the retained first filling material layer is etched to form the first filling layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: During the process of obliquely etching the first filling material layer, the oblique etching angle is gradually reduced, and the oblique sidewall is formed into a concave surface that is sunken toward the bottom of the groove.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: In the second doping region formed by implanting the first ions into the inclined sidewall, the concentration of the first ions on the side close to the groove bottom is greater than the concentration of the first ions on the side close to the groove opening.

5. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The first filling material layer is obliquely etched to a depth less than the first groove, and the inclined sidewall is formed, and a first plane connected to the inclined sidewall is formed; the second filling layer covers the inclined sidewall and the first plane.

6. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: Before forming the first doping region, an insulating layer covering the sidewalls of the first trench is formed.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The implantation concentration of the first ions in the first doping region is greater than 1×10 15 ion / cm 2 , the implantation concentration of the first ions in the second doping region is greater than 1×10 15 ion / cm 2 The implantation concentration of the first ions in the third doping region is greater than 1×10 15 ion / cm 2 ; The implantation concentration of the first ions in the second doping region is greater than the implantation concentration of the first ions in the first doping region and the implantation concentration of the first ions in the third doping region.

8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The temperature of the annealing treatment is 900° C.-1200° C., and the duration of the annealing treatment is 2 min-120 min.

9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The first ions include boron ions.

10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 9, wherein the semiconductor structure comprises: a substrate having a first trench; A semiconductor doping layer is filled in the first groove, the semiconductor doping layer is doped with first ions, the semiconductor doping layer includes a first filling layer doped with the first ions and a second filling layer doped with the first ions, the first filling layer covers the bottom surface of the first groove and fills part of the first groove, the first filling layer has an inclined side wall, the inclined side wall extends from the notch of the first groove to the bottom of the first groove, and the second filling layer covers the inclined side wall and fills the area of ​​the first groove not filled by the first filling layer.

11. The semiconductor structure according to claim 10, characterized in that: The inclined side wall is a concave surface that is recessed toward the bottom surface of the first trench.

12. The semiconductor structure according to claim 10, characterized in that The second filling layer continuously covers the inclined sidewall of the first filling layer, and the semiconductor doping layer has no filling gap.

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