A semiconductor structure and a method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises: providing a substrate; sequentially forming a dielectric layer and a conductive layer on the substrate; forming a patterned target mask layer on the conductive layer, an edge of the target mask layer at least exposing an edge of a part of the conductive layer; removing, based on the target mask layer, a region of the target mask layer exposing the conductive layer; and forming a passivation layer on the substrate on a side of the substrate having the conductive layer. The forming method of the semiconductor structure provided by the embodiments of the present application improves the yield of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and a method for forming the same. Background Technology

[0002] During the manufacturing process of integrated circuits, arcing often occurs on the front side of the device when etching the dielectric layer. Arcing can damage the conductive structure in the dielectric layer, reduce the device yield, and even cause the device to be scrapped.

[0003] Therefore, how to improve the yield of devices has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor structure and a method for forming the same, in order to improve the yield of the device.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a method for forming a semiconductor structure, including:

[0007] Provide substrate;

[0008] A dielectric layer and a conductive layer are sequentially formed on the substrate;

[0009] A patterned target mask layer is formed on the conductive layer, wherein the edge of the target mask layer exposes at least a portion of the edge of the conductive layer;

[0010] Based on the target mask layer, remove the area of ​​the target mask layer that exposes the conductive layer;

[0011] A passivation layer is formed on the side of the substrate where the conductive layer is formed.

[0012] Optionally, the step of forming a patterned target mask layer on the conductive layer includes:

[0013] A target photolithography layer is formed on the conductive layer;

[0014] Remove the photoresist at a predetermined distance from the edge of the target photolithography layer, and use the remaining target photolithography layer as the target mask layer.

[0015] Optionally, the preset distance is greater than 2mm.

[0016] Optionally, the target mask layer also exposes a portion of the conductive layer in the middle region.

[0017] Optionally, after forming a passivation layer on the side of the substrate where the conductive layer is formed, the method further includes:

[0018] The passivation layer is patterned to expose a portion of the conductive layer.

[0019] Optionally, the step of sequentially forming a dielectric layer and a conductive layer on the substrate includes:

[0020] A dielectric layer is formed on the substrate;

[0021] Multiple through-holes are formed on the dielectric layer, and the through-holes penetrate the dielectric layer;

[0022] Forming a conductive plug that fills the through-hole;

[0023] A conductive layer is formed that is electrically connected to the conductive plug.

[0024] Optionally, the steps of sequentially forming a dielectric layer and a conductive layer on the substrate, forming a patterned target mask layer on the conductive layer, and removing the area of ​​the target mask layer that exposes the conductive layer based on the target mask layer are performed once as one cycle, wherein the cycle is repeated at least twice.

[0025] Optionally, in the step of removing the area of ​​the target mask layer that exposes the conductive layer based on the target mask layer, an etching process is used to remove the area of ​​the target mask layer that exposes the conductive layer.

[0026] Optionally, the etching process is one or both of dry etching and wet etching.

[0027] Secondly, embodiments of this application provide a semiconductor structure formed based on the semiconductor structure formation method described in the first aspect above.

[0028] Compared with the prior art, the technical solution of this application has the following advantages:

[0029] This application provides a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: providing a substrate; sequentially forming a dielectric layer and a conductive layer on the substrate; forming a patterned target mask layer on the conductive layer, wherein the edge of the target mask layer exposes at least a portion of the edge of the conductive layer; removing the area of ​​the target mask layer that exposes the conductive layer based on the target mask layer; and forming a passivation layer on the side of the substrate where the conductive layer is formed.

[0030] As can be seen, the semiconductor structure formation method provided in this application involves forming a patterned target mask layer on the conductive layer, with the edge of the target mask layer exposing at least a portion of the edge of the conductive layer. Then, based on the target mask layer, the area of ​​the target mask layer exposing the conductive layer is removed, so that the edge of the conductive layer is etched away. This avoids the situation where the edge of the conductive layer is exposed during subsequent etching, so that electrons cannot form a conductive circuit in the device under the action of plasma charging, thereby avoiding the occurrence of "arson" and improving the yield of the device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a device forming a conductive circuit in the prior art;

[0033] Figures 2-4 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to the embodiments of this application.

[0034] The accompanying figure is labeled as follows:

[0035] 100 - Substrate; 110 - Dielectric layer; 120 - Conductive layer; 130 - Passivation layer; 01 - Through hole. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] As described in the background section, during the manufacturing process of integrated circuits, "arcing" often occurs on the front side of the device when etching the dielectric layer. This "arcing" damages the conductive structure within the dielectric layer. For ease of understanding, Figure 1 An exemplary schematic diagram of a device forming a conductive circuit in the prior art is shown, with reference to... Figure 1As the device approaches its edge, the dielectric layer 110 becomes thinner. With etching, a conductive layer 120 is exposed at the device edge. Under plasma charging, electrons form a conductive circuit through the conductive structure and the plasma. Excessive current causes the conductive structure to overheat, resulting in arcing. The conductive structure refers to the physical structure within the device that conducts electricity, typically composed of materials such as metals, semiconductors, or electrolytes. These materials contain freely moving electrons or ions, allowing current to pass through.

[0038] The "arson" phenomenon can damage the conductive structure in the dielectric layer of a device, reducing device yield and even causing the device to be scrapped. The inventors believe that etching away the edges of the conductive layer during its formation can prevent these edges from being exposed during subsequent etching processes. This prevents electrons from forming a conductive circuit with the plasma during plasma charging, thus avoiding the "arson" phenomenon and improving device yield.

[0039] To address the aforementioned problems, embodiments of this application provide a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: providing a substrate; sequentially forming a dielectric layer and a conductive layer on the substrate; forming a patterned target mask layer on the conductive layer, wherein the edge of the target mask layer at least exposes a portion of the edge of the conductive layer; removing the area of ​​the target mask layer that exposes the conductive layer based on the target mask layer; and forming a passivation layer on the side of the substrate where the conductive layer is formed.

[0040] As can be seen, the semiconductor structure formation method provided in this application involves forming a patterned target mask layer on the conductive layer, with the edge of the target mask layer exposing at least a portion of the edge of the conductive layer. Then, based on the target mask layer, the area of ​​the target mask layer exposing the conductive layer is removed, causing the edge of the conductive layer to be etched away. This avoids the situation where the edge of the conductive layer is exposed during subsequent etching, so that under the action of plasma charging, electrons cannot form a conductive circuit through the conductive structure of the device and the plasma, thereby avoiding the occurrence of "arson" and improving the yield of the device.

[0041] The following describes in detail a method for forming a semiconductor structure provided by the embodiments of this application.

[0042] Figures 2-4 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of this application. Since the "arc" phenomenon occurs at the edge of the device, the following is an exemplary description of the edge structure corresponding to each step in the method for forming a semiconductor structure.

[0043] refer to Figure 2 Substrate 100 is provided.

[0044] The substrate 100 is used to provide structural support for the device.

[0045] The substrate 100 can be made of silicon. In other embodiments, the substrate 100 can be made of one or more of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium ionide. Alternatively, the substrate can be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Those skilled in the art can select materials according to actual needs, and this application does not impose any limitations on this.

[0046] refer to Figure 3 A dielectric layer 110 and a conductive layer 120 are sequentially formed on the substrate 100.

[0047] The process for forming the dielectric layer 110 may include, but is not limited to, one or more of the following processes: chemical vapor deposition, atomic layer deposition, high-density plasma deposition, plasma-enhanced deposition, and spin-coating of dielectric layers. The material of the dielectric layer 110 includes, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.

[0048] The step of sequentially forming a dielectric layer and a conductive layer on the substrate includes: forming a dielectric layer 110 on the substrate 100; forming a plurality of through holes 01 on the dielectric layer 110, the through holes 01 penetrating the dielectric layer 110; forming a conductive plug filling the through holes 01; and forming a conductive layer 120 electrically connected to the conductive plug.

[0049] In this embodiment, the conductive plug in the through hole 01 can be a tungsten plug, and the conductive layer 120 can be made of aluminum. The conductive plug and the conductive layer 120 can also be made of other materials known to those skilled in the art that can achieve conductivity; this embodiment does not limit the application in this regard.

[0050] A patterned target mask layer is formed on the conductive layer, the edges of the target mask layer exposing at least a portion of the edges of the conductive layer; based on the target mask layer, the areas of the target mask layer that expose the conductive layer are removed. The target mask layer also exposes a portion of the conductive layer in the middle region.

[0051] In the step of removing the region of the conductive layer exposed by the target mask layer, an etching process can be used to remove the region of the conductive layer exposed by the target mask layer. The etching process can be one or both of dry etching and wet etching processes. That is, the etching process can be a dry etching process, a wet etching process, or a combination of dry and wet etching processes.

[0052] A patterned target mask layer is formed on the conductive layer. Then, based on the target mask layer, the area of ​​the target mask layer that exposes the conductive layer is removed, so that the edge of the conductive layer is etched away. This avoids the situation where the edge of the conductive layer is exposed during subsequent etching. Under the action of plasma charging, electrons cannot form a conductive circuit through the conductive structure of the device and the plasma, thereby avoiding the occurrence of "arson" and improving the yield of the device.

[0053] The step of forming a patterned target mask layer on the conductive layer includes: forming a target photolithography layer on the conductive layer; removing photoresist at a predetermined distance from the edge of the target photolithography layer, using the remaining target photolithography layer as the target mask layer. The predetermined distance is greater than 2 mm. In this embodiment, the predetermined distance is set to 2.2 mm. In a specific implementation, the photoresist edge removal EBR program can be set to 2.2 mm.

[0054] The steps of sequentially forming a dielectric layer and a conductive layer on the substrate, forming a patterned target mask layer on the conductive layer, and removing the area of ​​the target mask layer that exposes the conductive layer based on the target mask layer are performed once as one cycle, wherein the cycle is repeated at least twice.

[0055] In other words, each time a conductive layer is formed, a patterned target mask layer needs to be formed on the conductive layer. Then, based on the target mask layer, the area of ​​the target mask layer that exposes the conductive layer is removed. By removing the area of ​​the target mask layer that exposes the conductive layer, the edges of the conductive layer are etched away, avoiding the situation where the edges of the conductive layer are exposed during subsequent etching processes. This prevents electrons from forming a conductive circuit through the conductive structure of the device and the plasma under the action of plasma charging, thereby avoiding the occurrence of "arson" and improving the device yield.

[0056] refer to Figure 4 A passivation layer 130 is formed on the side of the substrate 100 where the conductive layer 120 is formed, and the passivation layer 130 exposes a portion of the conductive layer 120. The material of the passivation layer 130 includes, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.

[0057] After forming a passivation layer 130 on the side of the substrate 100 where the conductive layer 120 is formed, the method further includes: patterning the passivation layer 130 to expose a portion of the conductive layer 120. Exposing a portion of the conductive layer 120 can increase the contact area with external circuits or components, thereby enhancing conductivity.

[0058] In this embodiment of the application, by setting a preset distance greater than 2mm, the edge of the conductive layer 120 can be etched away. Therefore, when the passivation layer 130 is etched, even if the edge of the passivation layer 130 is etched away first, without the edge of the conductive layer 120 as a conductor, electrons cannot form a conductive circuit through the conductive structure of the device and the plasma under the action of plasma charging, thereby avoiding the occurrence of "arcing".

[0059] As can be seen, the semiconductor structure formation method provided in this application involves forming a patterned target mask layer on the conductive layer, with the edge of the target mask layer exposing at least a portion of the edge of the conductive layer; then, based on the target mask layer, the area of ​​the target mask layer exposing the conductive layer is removed, so that the edge of the conductive layer is etched away, avoiding the situation where the edge of the conductive layer is exposed during subsequent etching. This prevents electrons from forming a conductive circuit through the conductive structure of the device and the plasma under the action of plasma charging, thereby avoiding the occurrence of "arson" and improving the yield of the device.

[0060] To address the aforementioned problems, this application also provides a semiconductor structure formed based on the semiconductor structure formation method described above.

[0061] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0062] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A dielectric layer and a conductive layer are sequentially formed on the substrate. The thickness of the dielectric layer at the edge is smaller than that at the center, and the thickness of the dielectric layer decreases as it approaches the edge. A patterned target mask layer is formed on the conductive layer, wherein the edge of the target mask layer exposes at least a portion of the edge of the conductive layer; Based on the target mask layer, the area of ​​the target mask layer that exposes the conductive layer is removed, and the conductive layer at a predetermined edge distance is removed, wherein the predetermined edge distance is greater than 2mm; A passivation layer is formed on the side of the substrate where the conductive layer is formed, and the top of the passivation layer on the side away from the conductive layer is flush with the top.

2. The method as described in claim 1, characterized in that, The step of forming a patterned target mask layer on the conductive layer includes: A target photolithography layer is formed on the conductive layer; Remove the photoresist at a predetermined distance from the edge of the target photolithography layer, and use the remaining target photolithography layer as the target mask layer.

3. The method as described in claim 1, characterized in that, The target mask layer also exposes part of the conductive layer in the middle region.

4. The method as described in claim 1, characterized in that, After forming a passivation layer on the side of the substrate where the conductive layer is formed, the method further includes: The passivation layer is patterned to expose a portion of the conductive layer.

5. The method as described in claim 1, characterized in that, The step of sequentially forming a dielectric layer and a conductive layer on the substrate includes: A dielectric layer is formed on the substrate; Multiple through-holes are formed on the dielectric layer, and the through-holes penetrate the dielectric layer; Forming a conductive plug that fills the through-hole; A conductive layer is formed that is electrically connected to the conductive plug.

6. The method as described in claim 1, characterized in that, The steps of sequentially forming a dielectric layer and a conductive layer on the substrate, forming a patterned target mask layer on the conductive layer, and removing the area of ​​the target mask layer that exposes the conductive layer based on the target mask layer are performed once as one cycle, wherein the cycle is repeated at least twice.

7. The method as described in claim 1, characterized in that, In the step of removing the area of ​​the target mask layer that exposes the conductive layer based on the target mask layer, an etching process is used to remove the area of ​​the target mask layer that exposes the conductive layer.

8. The method as described in claim 7, characterized in that, The etching process is one or both of dry etching and wet etching.

9. A semiconductor structure, characterized in that, The semiconductor structure is formed based on the semiconductor structure formation method as described in any one of claims 1-8.

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