Wafer memory

Abstract

The present disclosure relates to a wafer storage device, which includes a storage chamber, a handling device, a plurality of temporary stations and a switching mechanism. The storage chamber includes a sidewall with a window. The handling device is rotatably arranged in the storage chamber about a main axis for handling wafer cassettes. The plurality of temporary stations is arranged in the storage chamber between the window and the handling device. A wafer cassette can be placed on any of the temporary stations through the window from outside, and a wafer cassette on any of the temporary stations can be taken out through the window. The switching mechanism is used to switch the plurality of temporary stations between a first state and a second state. In the first state, the plurality of temporary stations are arranged in a linear direction with equal distances to the window, so that an operator can access the wafer cassettes through the window. In the second state, the plurality of temporary stations are arranged in a direction around the main axis with equal distances to the main axis, which can reduce the moving path of the handling device when handling the wafer cassettes and improve the handling efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing equipment, and in particular, to a chip memory. Background Technology

[0002] In semiconductor manufacturing systems, wafers are loaded into wafer cassettes, which are typically temporarily stored in wafer memory. The wafer memory also includes handling devices for automated picking and placing of the wafer cassettes.

[0003] However, during the storage and retrieval of wafer cassettes, the handling device needs to be precisely aligned according to the position of each wafer cassette. This means that the equipment must be repositioned and adjusted every time it is moved, which not only increases the complexity of the operation but also prolongs the handling time, resulting in reduced efficiency of the handling process. Therefore, the need to improve the handling efficiency of wafer cassettes in wafer memory and shorten the handling time has always existed. Summary of the Invention

[0004] In view of this, the present disclosure provides a wafer memory designed to improve the handling efficiency of wafer cassettes in the wafer memory.

[0005] The wafer memory disclosed herein includes a storage compartment, a transport device, multiple temporary storage stages, and a switching mechanism. The storage compartment includes a sidewall with a window. The transport device is rotatably disposed within the storage compartment about a main axis and is used to transport wafer cassettes. Multiple temporary storage stages are disposed within the storage compartment and located between the window and the transport device. A wafer cassette can be placed on any temporary storage stage from the outside through the window, and a wafer cassette on any temporary storage stage can be removed through the window. The switching mechanism is used to switch the multiple temporary storage stages between a first state and a second state. In the first state, the multiple temporary storage stages are spaced apart along a straight line, such that the distances from the multiple temporary storage stages to the window are equal. In the second state, the multiple temporary storage stages are spaced apart along a direction surrounding the main axis, and are equidistant from the main axis.

[0006] In the first state, the operator can access wafer cassettes on multiple temporary storage platforms through a window. In the second state, the multiple temporary storage platforms are spaced apart along the main axis, allowing the transport device to continuously transport wafer cassettes on each platform by rotating around the main axis. Furthermore, since the distances from the multiple temporary storage platforms to the main axis are equal, the transport device does not need to change its distance to each platform when transporting wafer cassettes on different platforms, thus reducing the travel path of the transport device and improving transport efficiency.

[0007] In one possible implementation, in a first state, each temporary storage stage faces a plane that is parallel to both the straight line direction and the extension direction of the main axis; and / or, in a second state, each temporary storage stage faces the main axis.

[0008] In the first state, the operator only needs to face the window to ensure that each storage stage is aligned. This allows the operator to access the wafer cassette horizontally without rotating or adjusting its position, thus improving the efficiency of wafer cassette access. In the second state, after rotating around the main axis to face the storage stage, the transport device can move in a straight line to contact and remove the wafer cassette from the storage stage. This effectively reduces the travel path of the transport device, thereby improving transport efficiency.

[0009] In one possible implementation, the multiple storage stages include a central storage stage and two lateral storage stages. The central storage stage is aligned with the main axis in a straight line, and the two lateral storage stages are located on opposite sides of the central storage stage in the straight line. As the multiple storage stages switch from a first state to a second state, the central storage stage remains fixed relative to the main axis, while the two lateral storage stages move closer to the main axis.

[0010] When the central temporary storage platform is aligned with the main axis in a straight line, the position of the central temporary storage platform remains unchanged regardless of whether the multiple temporary storage platforms are in the first or second state. In this way, by setting the central temporary storage platform to be fixed relative to the main axis, and changing the state of multiple temporary storage platforms only by moving the two side temporary storage platforms closer to the main axis, the number of components required to move the temporary storage platforms can be reduced, thereby reducing the complexity of the structure.

[0011] In one possible implementation, the switching mechanism includes two connecting parts, each of which is anti-rotationally connected to two side storage stages. As the multiple storage stages switch between a first state and a second state, each connecting part moves along an arc trajectory with the side storage stage it is connected to, thereby changing the position and orientation of the side storage stage relative to the main axis.

[0012] Because of the anti-rotation connection with the connecting part, the side storage stage can face the main axis after moving along the arc trajectory with the connecting part. In other words, when the side storage stage is anti-rotationally connected with the connecting part, the movement of the connecting part can simultaneously change the position and orientation of the side storage stage relative to the main axis.

[0013] In one possible implementation, the switching mechanism includes two drive components, each used to drive two side temporary storage stages. Each drive component includes a boom and a driver. The first end of the boom is rotatably supported about a first rotation axis, and its second end forms a corresponding connection. The first end of the driver is rotatably supported about a second rotation axis, and its second end is rotatably connected to the second end of the boom. Both the first and second rotation axes are parallel to the main axis and are spaced apart from each other. The driver extends and retracts, driving the boom to rotate about the first rotation axis.

[0014] According to the above implementation, as the driver extends and retracts, the second end of the driver will drive the second end of the boom to rotate around the first rotation axis, thereby changing the position of the side temporary storage stage.

[0015] In one possible implementation, the chip memory further includes a support base, which includes a support platform and two recesses located on opposite sides of the platform in a straight direction. A center temporary storage stage is located on the support platform, and two side temporary storage stages are located above the two recesses and at the same height as the center temporary storage stage. The first end of the boom and the first end of the driver are both connected to the bottom of the support platform, and the second end of the boom and the second end of the driver extend into a corresponding recess, such that the second end of the boom is connected to the side temporary storage stage in the recess.

[0016] According to the above structure, the boom and actuator are placed at the bottom of the support platform and in two recesses, which helps to improve the space utilization of the support base. In addition, multiple temporary storage stages are located at the same height, allowing the handling device to move wafer cassettes on multiple temporary storage stages at the same height, avoiding the need for height adjustment of the handling device, thus effectively reducing the movement path of the handling device.

[0017] In one possible implementation, the wafer memory also includes multiple storage stages for placing wafer cassettes, each of which is equidistant from the main axis.

[0018] According to the above implementation, when moving wafer cassettes between the temporary storage stage and the storage stage, the transport device does not need to adjust its distance from the temporary storage stage or the storage stage, thereby reducing the movement path of the transport device and improving transport efficiency.

[0019] In one possible implementation, multiple storage stations are supported on the sidewalls, with the multiple storage stations located above or below multiple temporary storage stations.

[0020] Multiple storage stages and multiple temporary storage stages are located between the side wall and the transport device. In other words, multiple storage stages and multiple temporary storage stages are located on the same side of the transport device. This means that the transport device does not need to rotate to the other side when transporting wafer cassettes between the temporary storage stages and the storage stages, thus effectively reducing the movement path of the transport device.

[0021] In one possible implementation, the multiple temporary storage stages include N temporary storage stages, and the multiple storage stages include N columns of storage stages, with each of the N columns of storage stages corresponding to one of the N temporary storage stages. In the second state, the orthographic projections of each column of storage stages and its corresponding temporary storage stage on a plane perpendicular to the main axis coincide.

[0022] According to the above implementation, in the second state, when the transport device moves wafer cassettes between each column of storage stations and the corresponding temporary storage station, it only needs to move in the vertical direction and does not need to change its horizontal position. This effectively reduces the movement path of the transport device, thereby improving transport efficiency.

[0023] This disclosure also provides a wafer memory, including a storage compartment, a transport device, a plurality of temporary storage stages, and a switching mechanism. The storage compartment includes a sidewall with a window. The transport device is rotatably disposed within the storage compartment about a main axis for transporting wafer cassettes. The plurality of temporary storage stages are disposed within the storage compartment and located between the window and the transport device. A wafer cassette can be placed on any temporary storage stage from the outside through the window, and a wafer cassette on any temporary storage stage can be removed through the window. The switching mechanism is used to move at least one of the plurality of temporary storage stages to switch the plurality of temporary storage stages between a first state and a second state. In the first state, each temporary storage stage faces a plane parallel to both the linear direction and the extension direction of the main axis. In the second state, each temporary storage stage faces the main axis.

[0024] In the first state, the operator only needs to face the window to ensure that each storage stage is directly in front of them. This allows the operator to access the wafer cassette horizontally without rotating or adjusting its position, thus improving the efficiency of wafer cassette access. In the second state, the transport device can continuously transport the wafer cassettes on each storage stage by rotating around the main axis. Furthermore, after rotating around the main axis to face the storage stage, the transport device can contact and remove the wafer cassettes on the storage stage by moving in a straight line, thus effectively reducing the travel path of the transport device. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below.

[0026] It should be understood that the following figures only illustrate certain embodiments of this disclosure and should not be construed as limiting the scope.

[0027] It should also be understood that the same or similar reference numerals are used in the accompanying drawings to denote the same or similar elements.

[0028] It should also be understood that the accompanying drawings are only schematic, and the dimensions and scales of the elements in the drawings are not necessarily precise.

[0029] Figure 1 This is a schematic diagram illustrating an application scenario of a chip memory according to an embodiment of the present disclosure.

[0030] Figure 2 yes Figure 1 A schematic diagram of the structure of the chip memory.

[0031] Figure 3yes Figure 2 A schematic diagram of a part of the structure.

[0032] Figure 4 yes Figure 2 A schematic diagram of the transport device.

[0033] Figure 5 yes Figure 2 A schematic diagram of the structure of the chip box.

[0034] Figure 6 yes Figure 2 Schematic diagram of the switching mechanism of the chip memory

[0035] Figure 7A and Figure 7B yes Figure 2 A schematic top view of the temporary storage stage of a mid-chip memory. Figure 7A The temporary storage platform is in the first state. Figure 7B The temporary storage platform is in the second state.

[0036] Figure 8 yes Figure 2 A schematic diagram of the support structure for the chip memory.

[0037] Figure 9A and Figure 9B This is a schematic top view of a chip memory staging platform provided according to another embodiment of the present disclosure. Figure 9A The temporary storage platform is in the first state. Figure 9B The temporary storage platform is in the second state. Detailed Implementation

[0038] The embodiments of this disclosure are described below with reference to the accompanying drawings. It should be understood that there are many ways to implement this disclosure, and it should not be construed as being limited to the embodiments set forth herein. The embodiments set forth herein are only for a more thorough and clear understanding of this disclosure.

[0039] Figure 1 A wafer manufacturing system is shown; see [link / reference]. Figure 1 The wafer manufacturing system includes a wafer memory 100, a wafer transport device 200, and a processing area 300. The wafer memory 100 stores wafer cassettes. The wafer transport device 200 transports wafer cassettes to the wafer memory 100. As an example, the wafer transport device 200 can circulate along the path shown by the dashed line in the figure and stop when passing the wafer memory 100, where an operator (or automated handling equipment) stores the wafer cassettes into the wafer memory 100. One side of the wafer memory 100 faces the movement path of the wafer transport device 200, and the other side faces the processing area 300. The wafer memory 100 can store multiple wafer cassettes, and the wafers in the wafer cassettes can be loaded into the processing area 300 for processing.

[0040] To ensure a smooth and efficient manufacturing process, the wafer memory 100 needs to continuously feed wafers to the processing area 300. This necessitates frequent handling of the wafer cassettes within the wafer memory 100 to load the wafers from the cassettes into the processing area 300. Therefore, the need to improve the handling efficiency of the wafer cassettes within the wafer memory has always existed.

[0041] In view of this, refer to Figure 2 and Figure 3 This disclosure provides a wafer memory 100, which includes a storage compartment 10, a transport device 20, a wafer cassette 30, and a plurality of temporary storage stages 40. The storage compartment 10 includes a sidewall 11 with a window 12. The transport device 20 is rotatably disposed within the storage compartment 10 about a main axis AA and is used to transport the wafer cassette 30. The plurality of temporary storage stages are disposed within the storage compartment 10 and located between the window 12 and the transport device 20. The wafer cassette 30 can be placed on any of the temporary storage stages 40 from the outside through the window 12, and the wafer cassette 30 on any of the temporary storage stages 40 can be removed through the window 12. Figure 6 The chip memory 100 also includes a switching mechanism 50, which is used to switch the plurality of temporary storage stages 40 between a first state and a second state. Figure 7A In the first state, multiple temporary storage stations 40 are arranged at intervals along a straight line BB, such that the distances from the multiple temporary storage stations 40 to the window 12 are equal. Combined with... Figure 7B In the second state, multiple temporary storage stations 40 are arranged at intervals along the direction surrounding the main axis AA, and are equidistant from the main axis AA.

[0042] In the first state, the operator can access the wafer cassettes 30 on multiple temporary storage stages 40 through window 12. In the second state, the multiple temporary storage stages 40 are arranged at intervals along the direction surrounding the main axis AA, so the transport device 20 can continuously transport the wafer cassettes 30 on each temporary storage stage 40 by rotating around the main axis AA. Furthermore, since the multiple temporary storage stages 40 are equidistant from the main axis AA, the transport device 20 does not need to change its distance from each temporary storage stage 40 when transporting wafer cassettes 30 on different temporary storage stages 40, thus reducing the travel path of the transport device 20 and improving transport efficiency.

[0043] refer to Figure 4 The conveying device 20 may include a spindle 21, a first rotating arm 22, a second rotating arm 23, and a clamping member 24. The first end of the first rotating arm 22 is rotatably connected to the spindle 21 about the spindle axis AA. One end of the second rotating arm 23 is rotatably connected to the second end of the first rotating arm 22, and the other end of the second rotating arm 23 is anti-rotatingly connected to the clamping member 24. The clamping member 24 is capable of clamping and releasing the wafer cassette 30.

[0044] In one possible implementation, the spindle 21 may be equipped with a lifting element (not shown in the figure). Through the lifting element, the conveying device 20 can change its height in the vertical direction. At the same time, the rotation of the first rotating arm 22 and the second rotating arm 23 can precisely adjust the position and angle of the clamping member 24 in the horizontal direction. In this way, the clamping member 24 can move in three-dimensional space to complete the conveying of the wafer cassette 30.

[0045] Continue to refer to Figure 4 The clamping member 24 includes two arms 241, which can be driven to move in a straight line direction perpendicular to the vertical direction. Each arm 241 is provided with a clamping part 242 extending in the vertical direction. The two clamping parts 242 are arranged opposite to each other, and each clamping part 242 is recessed in a direction away from the other clamping part 242 to form a groove 2421.

[0046] Combination Figure 5 The wafer cassette 30 includes an opening 31 and two mating portions 32. The opening 31 allows wafers to be removed from or placed into the wafer cassette 30, and the opening direction of the opening 31 is the direction in which the wafer is removed from or placed into the wafer cassette 30. The two mating portions 32 are located on one side of the opening direction and can respectively engage with two clamping portions 242 to realize the transport of the wafer cassette 30. Specifically, when the wafer cassette 30 is placed between the two clamping portions 242, the two arms 241 move towards each other, so that the two mating portions 32 are respectively placed in the two grooves 2421, thereby enabling the clamping member 24 to stably clamp the wafer cassette 30. When the wafer cassette 30 is transported to the target position, the two arms 241 move in opposite directions, so that the two mating portions 32 disengage from the two grooves 2421, thereby enabling the clamping member 24 to release the wafer cassette 30.

[0047] It is understood that there are many ways to drive the arm 241 to move; for example, the arm 241 can be driven to move by hydraulic, pneumatic, or electric means. This disclosure does not impose any particular limitation on this.

[0048] refer to Figure 7A In the first state, each temporary storage stage 40 faces a plane parallel to both the direction of line BB and the extension direction of the main axis AA. That is, the first end face 401 of each temporary storage stage 40 is parallel to the plane containing window 12. Therefore, the operator only needs to face window 12 to ensure that it is aligned with each temporary storage stage 40. This allows the operator to access the wafer cassette 30 horizontally without rotating or adjusting its position, thereby improving the efficiency of accessing the wafer cassette 30.

[0049] refer to Figure 7BIn the second state, each temporary storage stage 40 is directly facing the main axis AA, and the wafer cassette 30 on each temporary storage stage 40 is also directly facing the main axis AA. Combined Figure 5 When a plane is perpendicular to the opening direction, that plane is directly opposite the wafer cassette 30. Assuming that the transport device 20 has a plane, namely the plane defined by the two clamping parts 242 mentioned above, when the transport device 20 rotates around the main axis AA so that the plane is perpendicular to the opening direction of the wafer cassette 30, the transport device 20 can move along the opening direction of the wafer cassette 30 to clamp and remove the wafer cassette 30. In this way, the movement path of the transport device 20 can be effectively reduced, thereby improving the transport efficiency.

[0050] refer to Figure 7A and Figure 7B The multiple temporary storage platforms 40 include a central temporary storage platform 41 and two lateral temporary storage platforms 42. The central temporary storage platform 41 is aligned with the main axis AA in a straight line, and the two lateral temporary storage platforms 42 are located on opposite sides of the central temporary storage platform 41 in a straight line. As the multiple temporary storage platforms 40 switch from a first state to a second state, the central temporary storage platform 41 is fixed relative to the main axis AA, while the two lateral temporary storage platforms 42 move closer to the main axis AA. When the central temporary storage platform 41 is aligned with the main axis AA in a straight line, the position of the central temporary storage platform 41 remains unchanged regardless of whether the multiple temporary storage platforms 40 are in the first or second state. In this way, by setting the central temporary storage platform 41 to be fixed relative to the main axis AA, and changing the state of the multiple temporary storage platforms 40 only by moving the two lateral temporary storage platforms 42 closer to the main axis AA, the number of components required to move the temporary storage platforms 40 can be reduced, thereby reducing the complexity of the structure.

[0051] It is understood that the number of temporary storage platforms can also be other values, and this disclosure does not make any special settings for this. For example, when the number of temporary storage platforms is still odd, the middle temporary storage platform can be set to be aligned with the main axis AA in the straight line direction and fixed relative to the main axis AA, thereby reducing the number of components required to move the temporary storage platform.

[0052] refer to Figure 3 and Figure 6 The switching mechanism 50 includes two connecting parts 51, each of which is anti-rotatingly connected to two side storage stages 42. As the multiple storage stages 40 switch between a first state and a second state, each connecting part 51 moves along an arc trajectory with the side storage stage 42 it is connected to, thereby changing the position and orientation of the side storage stage 42 relative to the main axis AA. Because it is anti-rotatingly connected to the connecting part 51, the side storage stage 42 can face the main axis AA after moving along the arc trajectory with the connecting part 51. In other words, when the side storage stage 42 is anti-rotatingly connected to the connecting part 51, the movement of the connecting part 51 can simultaneously change the position and orientation of the side storage stage 42 relative to the main axis AA.

[0053] refer to Figure 6 The switching mechanism 50 includes two drive components 52, which drive two side temporary storage stages 42 respectively. Each drive component 52 includes a boom 521 and a driver 522. The first end of the boom 521 is rotatably supported about a first rotation axis CC, and its second end forms a corresponding connecting part 51. The first end of the driver 522 is rotatably supported about a second rotation axis DD, and its second end is rotatably connected to the second end of the boom 521. Both the first rotation axis CC and the second rotation axis DD are parallel to the main axis AA, and the first rotation axis CC and the second rotation axis DD are spaced apart from each other. The driver 522 extends and retracts, driving the boom 521 to rotate about the first rotation axis CC. According to the above implementation, as the driver 522 extends and retracts, the second end of the driver 522 will drive the second end of the boom 521 to rotate about the first rotation axis CC, thereby changing the position of the side temporary storage stage 42.

[0054] It is understood that there are many ways to implement the actuator 522. For example, the actuator 522 can be an electric actuator or a cylinder. This disclosure does not impose any particular limitation on this.

[0055] It is understood that the drive component 52 can also be implemented in other forms, and this disclosure does not impose any particular limitation on it. As an example, the drive component 52 may include a slider and a driver, the slider being anti-rotationally connected to the side temporary storage stage, and the driver driving the slider to move along an arc trajectory.

[0056] refer to Figure 6 and Figure 8 The chip memory 100 may further include a support base 60, which includes a support platform 61 and two recesses 62 located on opposite sides of the platform in a straight line. A center temporary storage stage 41 is located on the support platform 61, and two side temporary storage stages 42 are located above the two recesses 62 and at the same height as the center temporary storage stage 41. The first end of the boom 521 and the first end of the driver 522 are both connected to the bottom of the support platform 61, and the second end of the boom 521 and the second end of the driver 522 extend into a corresponding recess 62, so that the second end of the boom 521 is connected to the side temporary storage stage 42 in the recess 62. According to the above structure, the boom 521 and the driver 522 are placed at the bottom of the support platform 61 and in the two recesses 62, which helps to improve the space utilization of the support base 60. In addition, the multiple temporary storage stages 40 are located at the same height, which allows the transport device 20 to transport the wafer cassettes 30 on the multiple temporary storage stages 40 at the same height, avoiding the need for the transport device 20 to make height adjustments, thus effectively reducing the movement path of the transport device 20.

[0057] Back Figure 3The wafer memory 100 may further include multiple storage stages 70 for placing wafer cassettes 30. Each of the multiple storage stages 70 and multiple temporary storage stages 40 is equidistant from the main axis AA. According to the above implementation, when moving wafer cassettes 30 between temporary storage stages 40 and storage stages 70, the transport device 20 does not need to adjust its distance from either the temporary storage stage 40 or the storage stage 70, thereby reducing the travel path of the transport device 20 and improving transport efficiency.

[0058] Continue to refer to Figure 3 Multiple storage stages 70 are supported on the side wall 11, and are located above or below multiple temporary storage stages 40. Both the storage stages 70 and the temporary storage stages 40 are located between the side wall 11 and the transport device 20. In other words, the storage stages 70 and the temporary storage stages 40 are located on the same side of the transport device 20. This allows the transport device 20 to move the wafer cassette 30 between the temporary storage stages 40 and the storage stages 70 without having to rotate to the other side, thus effectively reducing the movement path of the transport device 20.

[0059] Continue to refer to Figure 3 The system includes multiple temporary storage stages 40, comprising three temporary storage stages 40, and multiple storage stages 70, comprising three columns of storage stages 70, with each column of storage stages 70 corresponding to one of the three temporary storage stages 40. In the second state, the orthographic projections of each column of storage stages 70 and its corresponding temporary storage stage 40 on a plane perpendicular to the main axis AA coincide. According to the above implementation, in the second state, when the transport device 20 transports the wafer cassette 30 between each column of storage stages 70 and its corresponding temporary storage stage 40, it only needs to move in the vertical direction without changing its horizontal position. This effectively reduces the travel path of the transport device 20, thereby improving transport efficiency.

[0060] It is understandable that the number of temporary storage stations and the number of columns of storage stations can be other values, as long as the number of temporary storage stations and the number of storage stations satisfy the condition that N columns of storage stations correspond to N temporary storage stations respectively.

[0061] It should be understood that there are various ways to implement the chip memory of this disclosure, and it should not be construed as being limited to the embodiments described above. The following, in conjunction with... Figure 9A and Figure 9B The following are illustrative examples of variations of this disclosure. It should be noted that the foregoing embodiments and the following variations share some common elements. In the following variations, these elements will use the same reference numerals as in the foregoing embodiments to omit repeated descriptions.

[0062] In a variation of this disclosure, a switching mechanism 50a (not shown) in the wafer memory 100a (not shown) is used to move at least one of a plurality of temporary storage stages 40a to switch the plurality of temporary storage stages 40a between a first state and a second state. (In conjunction with...) Figure 9AIn the first state, each temporary storage stage 40a faces a plane parallel to both the straight direction and the extension direction of the main axis AA. Combined with... Figure 9A In the second state, each temporary storage stage 40a is directly facing the main axis AA. In the first state, the operator only needs to face the window 12 to ensure it is directly facing each temporary storage stage 40a. This allows the operator to access the wafer cassette 30 horizontally without rotating or adjusting its position, thus improving the efficiency of accessing the wafer cassette 30. In the second state, the transport device 20 can continuously transport the wafer cassette 30 on each temporary storage stage 40a by rotating around the main axis AA. Furthermore, after rotating around the main axis AA to be directly facing the temporary storage stage 40a, the transport device 20 can contact and remove the wafer cassette 30 by moving in a straight line, which effectively reduces the travel path of the transport device 20.

[0063] It should be understood that the term "comprising" and its variations as used in this disclosure are open-ended, meaning "including but not limited to". The term "according to" means "at least in part according to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least another embodiment".

[0064] The scope of protection of this disclosure is not limited to the above embodiments. Any variations or substitutions that can be conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip memory, characterized in that, include: Storage compartment, including a side wall with a window; A handling device, rotatably disposed within the storage compartment about a main axis, is used to handle wafer cassettes; Multiple temporary storage stages are disposed within the storage compartment and located between the window and the transport device; a wafer cassette can be placed on any temporary storage stage from the outside through the window, and a wafer cassette on any temporary storage stage can be removed through the window; the multiple temporary storage stages include a central temporary storage stage and two side temporary storage stages; and A switching mechanism is used to switch the plurality of temporary storage platforms between a first state and a second state. In the first state, the plurality of temporary storage platforms are arranged at intervals along a straight line, such that the distances from the windows to the platforms are equal. The center temporary storage platform is aligned with the main axis along the straight line, and the two side temporary storage platforms are located on opposite sides of the center platform along the straight line. In the second state, the plurality of temporary storage platforms are arranged at intervals around the main axis, and are equidistant from the main axis. The switching mechanism includes two connecting parts, which are respectively anti-rotationally connected to the two side temporary storage platforms. As the plurality of temporary storage platforms switch between the first state and the second state, the center temporary storage platform is fixed relative to the main axis, and the two side temporary storage platforms move closer to the main axis. Each connecting part moves along an arc trajectory with the side temporary storage platform connected to it to change the position and orientation of the side temporary storage platform relative to the main axis.

2. The chip memory according to claim 1, characterized in that, In the first state, each temporary storage stage faces a plane that is parallel to both the straight line direction and the extension direction of the main axis; and / or, in the second state, each temporary storage stage faces the main axis.

3. The chip memory according to claim 1 or 2, characterized in that, The switching mechanism includes two drive components, which are used to drive the two side temporary storage stages respectively. Each drive component includes a boom and a driver. The first end of the boom is rotatably supported about a first rotation axis and its second end forms a corresponding connecting part. The first end of the driver is rotatably supported about a second rotation axis and its second end is rotatably connected to the second end of the boom. The first rotation axis and the second rotation axis are both parallel to the main axis and are spaced apart from each other. The driver extends and retracts to drive the boom to rotate about the first rotation axis.

4. The chip memory according to claim 3, characterized in that, It also includes a support base, which includes a support platform and two recesses located on opposite sides of the platform in the straight direction. The center storage platform is located on the support platform, and the two side storage platforms are located above the two recesses and at the same height as the center storage platform. The first end of the boom and the first end of the driver are both connected to the bottom of the support platform, and the second end of the boom and the second end of the driver extend into a corresponding recess, so that the second end of the boom is connected to the side storage platform in the recess.

5. The chip memory according to claim 1 or 2, characterized in that, It also includes multiple storage stations for placing wafer cassettes, and each of the multiple storage stations and multiple temporary storage stations is equidistant from the main axis.

6. The chip memory according to claim 5, characterized in that, The plurality of storage platforms are supported on the side wall and are located above or below the plurality of temporary storage platforms.

7. The chip memory according to claim 6, characterized in that, The plurality of temporary storage stations include N temporary storage stations, and the plurality of storage stations include N columns of storage stations, with the N columns of storage stations corresponding to the N temporary storage stations respectively; in the second state, the orthographic projections of each column of storage station and the corresponding temporary storage station on a plane perpendicular to the main axis coincide.

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