A semiconductor structure and a method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises: providing a substrate; forming an isolation trench in the substrate; forming an isolation dielectric layer in the isolation trench in a first reaction cavity, the isolation dielectric layer conformally covering the isolation trench; after forming the isolation dielectric layer, removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench in a second reaction cavity; repeating the steps of forming the isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation dielectric layer, wherein the isolation dielectric layer completely filling the isolation trench is the isolation dielectric layer. The semiconductor structure formed by the forming method of the semiconductor structure provided by the embodiments of the present application improves the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the production of wafers, an isolation trench is generally filled with an isolation medium layer. The isolation medium layer is used to prevent electromagnetic interference and noise between different circuits due to potential difference, current, etc., thereby ensuring the normal operation of the device. In addition, the isolation medium layer can also prevent short circuit and failure between circuits, improve the reliability and safety of the device.

[0003] However, in the prior art, the device performance of the semiconductor structure obtained after forming the isolation medium layer needs to be improved. SUMMARY

[0004] Therefore, the embodiments of the present application provide a semiconductor structure and a forming method thereof to improve the performance of the device.

[0005] To solve the above problems, the embodiments of the present application provide a forming method of a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming an isolation trench in the substrate;

[0008] forming an isolation ion medium layer in the isolation trench in a first reaction cavity, the isolation ion medium layer conformally covering the isolation trench;

[0009] after forming the isolation ion medium layer, removing part of the isolation ion medium layer on the top of the sidewall of the isolation trench in a second reaction cavity;

[0010] repeating the steps of forming an isolation ion medium layer in the isolation trench and removing part of the isolation ion medium layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation ion medium layer, wherein the isolation ion medium layer completely filling the isolation trench is the isolation medium layer.

[0011] Optionally, the step of forming an isolation ion medium layer in the isolation trench is specifically: forming the isolation ion medium layer under a preset electric field, wherein the electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolation ion medium layer is less than a second preset value.

[0012] Optionally, the first preset value is 1800-2000W, and the second preset value is 1500-1700kg / m 3 .

[0013] Optionally, in the step of forming the isolation dielectric layer in the isolation trench, the isolation dielectric layer is formed by using a high-density plasma process (HDP).

[0014] Optionally, the reaction gas used in the high-density plasma process (HDP) includes O2, SiH4, SiH4-TOP, H2 and He, the flow rate of the reaction gas O2 is 70-110 sccm, the flow rate of the reaction gas SiH4 is 30-60 sccm, the flow rate of the reaction gas SiH4-TOP is 10-20 sccm, the flow rate of the reaction gas H2 is 110-150 sccm, and the flow rate of the reaction gas He is 200-400 sccm.

[0015] Optionally, the thickness of the isolation dielectric layer is 1-3 μm.

[0016] Optionally, in the step of removing the part of the isolation dielectric layer on the top of the sidewall of the isolation trench, the part of the isolation dielectric layer on the top of the sidewall of the isolation trench is removed by using a SiCoNi etching process.

[0017] Optionally, the reaction gas used in the SiCoNi etching process includes NH3 and NF3, the flow rate of the reaction gas NH3 is 120-160 sccm, the flow rate of the reaction gas NF3 is 50-90 sccm, the effective power is 20-60 W, and the etching rate is 100-200 A / min.

[0018] Optionally, the thickness of the part of the isolation dielectric layer removed on the top of the sidewall of the isolation trench is 0.5-1.5 μm.

[0019]

[0020] Optionally, the steps of forming the isolation dielectric layer in the isolation trench and removing the part of the isolation dielectric layer on the top of the sidewall of the isolation trench are performed once as a cycle, and the steps of repeatedly performing the steps of forming the isolation dielectric layer in the isolation trench and removing the part of the isolation dielectric layer on the top of the sidewall of the isolation trench are performed three times.

[0021] Optionally, after the step of repeatedly performing the steps of forming the isolation dielectric layer in the isolation trench and removing the part of the isolation dielectric layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation dielectric layer, the method further comprises:

[0022] depositing a sacrificial layer, the sacrificial layer completely covering the isolation dielectric layer;

[0023] planarizing the sacrificial layer and the isolation dielectric layer.

[0024] To solve the above problems, the embodiment of the present application also provides a semiconductor structure formed based on the forming method of the semiconductor structure.

[0025] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0026] The embodiment of the present application provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: providing a substrate; forming an isolation trench in the substrate; forming an isolation dielectric layer in the isolation trench in a first reaction cavity, the isolation dielectric layer conformally covers the isolation trench; after forming the isolation dielectric layer, removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench in a second reaction cavity; repeating the steps of forming the isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation dielectric layer, wherein the isolation dielectric layer is the isolation dielectric layer for completely filling the isolation trench.

[0027] It can be seen that the forming method of the semiconductor structure provided by the embodiment of the present application deposits the isolation dielectric layer in the first reaction cavity, and etches part of the isolation dielectric layer on the top of the sidewall of the isolation trench in the second reaction cavity, so that the etching is not affected by the electric field in the first reaction cavity, avoiding the influence of ions on electrons in the isolation dielectric layer when etching, thereby reducing the possibility of electron migration of the device, and improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0029] Figure 1 is a flowchart of the forming method of the semiconductor structure provided by the embodiment of the present application;

[0030] Figures 2-6 is a structure schematic diagram corresponding to the forming method of the semiconductor structure provided by the embodiment of the present application;

[0031] Figure 7 is another optional flowchart of the forming method of the semiconductor structure provided by the embodiment of the present application;

[0032] Figures 8-9is a schematic diagram of an optional structure corresponding to a forming method of a semiconductor structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the protection scope of the present application.

[0034] As described in the background, in the prior art, the device performance of the semiconductor structure obtained after forming the isolation medium layer needs to be improved.

[0035] In the prior art forming method of the semiconductor structure, the isolation trench in the reaction cavity is generally filled by using multiple deposition and etching cycles. In the deposition process, the isolation trench top is easily closed due to the decreasing line width and the increasing aspect ratio of the isolation trench, which causes the formation of holes in the lower part of the isolation trench. Therefore, an electric field is applied in the vertical direction during the etching process to accelerate the ion bombardment on the top after ionization, thereby inhibiting the deposition and closure of the top of the isolation trench. The specific process parameters are shown in Table 1, which is an example of the process parameters in the prior art.

[0036] Table 1

[0037]

[0038] In the table, the corresponding Chinese names of the English names are as follows:

[0039] DEP: deposition; ETCH: etching; TOP RF: reaction chamber top radio frequency; SIDE RF: reaction chamber edge radio frequency; BIAS RF: vertical direction bias radio frequency; Dep rate: deposition rate; ETCH rate: etching rate; SiH4-TOP: gas SiH4 introduced from the top of the reaction chamber; He-TOP: gas He introduced from the top of the reaction chamber.

[0040] The inventor believes that due to the high energy deposition and sputtering ratio set in the vertical direction, the higher the energy, the smaller the deposition and sputtering ratio, and thus a higher sputtering is generated. The higher sputtering allows part of the ions to pass through the surface layer of the deposition, thereby remaining in the lower deposition. During the etching process, NF3 is used to etch the sidewall of the top of the isolation trench. NF3 is ionized and accelerated under the vertical electric field, and at the same time of etching, part of the F element is buried in the deposition, i.e.: SiO2+ NF3→ SIF4+ N xO, since F element is very active and easy to precipitate, if such precipitation occurs in the working process of the chip, it is easy to cause electron migration, affecting the electrical properties of the chip.

[0041] Therefore, the application provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: providing a substrate; forming an isolation trench in the substrate; forming an isolation dielectric layer in the isolation trench in a first reaction cavity, the isolation dielectric layer conformally covers the isolation trench; after the isolation dielectric layer is formed, removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench in a second reaction cavity; repeating the steps of forming the isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation dielectric layer, wherein the isolation dielectric layer is a plurality of isolation dielectric layers for completely filling the isolation trench.

[0042] It can be seen that the forming method of the semiconductor structure provided by the application can deposit the isolation dielectric layer in the first reaction cavity, and etch part of the isolation dielectric layer on the top of the sidewall of the isolation trench in the second reaction cavity, so that the etching is not affected by the electric field in the first reaction cavity, avoiding the influence of ions on the electrons in the isolation dielectric layer during etching, thereby reducing the possibility of electron migration of the device, and improving the performance of the device.

[0043] The forming method of the semiconductor structure provided by the application will be described in detail below.

[0044] Reference Figure 1 , Figure 1 The forming method of the semiconductor structure provided by the application is shown in the flowchart. Figure 1 It can be seen that the forming method of the semiconductor structure provided by the application comprises the following steps.

[0045] Step S1: providing a substrate;

[0046] Step S2: forming an isolation trench in the substrate;

[0047] Step S3: forming an isolation dielectric layer in the isolation trench in a first reaction cavity;

[0048] The isolation dielectric layer conformally covers the isolation trench.

[0049] Step S4: removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench in a second reaction cavity;

[0050] Step S5: Determine whether the isolation trench is completely filled.

[0051] Specifically: if the isolation trench is not completely filled, steps S3 and S4 are repeated; if the isolation trench is completely filled, the process ends. It can be understood that step S5 involves repeatedly performing the steps of forming an isolation sub-medium layer within the isolation trench and removing a portion of the isolation sub-medium layer from the top of the sidewall of the isolation trench until the isolation trench is completely filled by the formed isolation sub-medium layer, wherein the plurality of isolation sub-medium layers that completely fill the isolation trench are considered as the isolation medium layer.

[0052] The following is combined Figures 2-6 The method for forming the semiconductor structure provided in the embodiments of this application is described in detail.

[0053] refer to Figure 2 Perform step S1 to provide substrate 100;

[0054] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate 100 may also be a germanium-silicon substrate, a group III-V compound substrate, a silicon carbide substrate or its stacked structure, or a silicon-on-insulator structure, or a diamond substrate or other semiconductor material substrates known to those skilled in the art. This invention does not specifically limit the substrate in this regard.

[0055] refer to Figure 3 Step S2 is performed to form an isolation trench 200 in the substrate 100;

[0056] The isolation trenches can be implemented using an etching process, such as wet etching, dry etching, or a combination of wet and dry etching. The number, shape, and depth of the isolation trenches 200 can be adjusted according to specific needs, and this invention does not impose specific limitations on them.

[0057] refer to Figure 4 Step S3 is executed, in which an isolation sub-medium layer 300 is formed in the isolation trench 200 within the first reaction chamber;

[0058] The isolator dielectric layer conformally covers the isolation trench, and the material of the isolator dielectric layer can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0059] It should be noted that step S3 specifically involves: forming the isolator dielectric layer under a preset electric field, wherein the electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolator dielectric layer is less than a second preset value.

[0060] The electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolation dielectric layer is less than a second preset value. The first preset value is 1800-2000 W, and the second preset value is 1500-1700 kg / m 3 .

[0061] The electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolation dielectric layer is less than a second preset value. The first preset value is 1800-2000 W, and the second preset value is 1500-1700 kg / m

[0062] In a specific embodiment, the high-density plasma process HDP is used to form the isolation dielectric layer 300. The thickness of the formed isolation dielectric layer is in the range of The thickness of the isolation dielectric layer is set to

[0063] The reaction gas used by the high-density plasma process HDP includes O2, SiH4, SiH4-TOP, H2, and He. The flow rate of the reaction gas O2 is 70-110 sccm, the flow rate of the reaction gas SiH4 is 30-60 sccm, the flow rate of the reaction gas SiH4-TOP is 10-20 sccm, the flow rate of the reaction gas H2 is 110-150 sccm, and the flow rate of the reaction gas He is 200-400 sccm.

[0064] Referring to Figure 5 , step S4 is performed to remove part of the isolation dielectric layer 300 on the top of the side wall of the isolation trench 200 in the second reaction cavity.

[0065] It should be noted that the thickness of the part of the isolation dielectric layer removed on the top of the side wall of the isolation trench is in the range of The thickness of the removed isolation dielectric layer is set to

[0066] In a specific embodiment, the SiCoNi etching process is used in the second reaction cavity to remove part of the isolation dielectric layer 300 on the top of the side wall of the isolation trench. The reaction gas used by the SiCoNi etching process includes NH3 and NF3. The flow rate of the reaction gas NH3 is in the range of 120-160 sccm, the flow rate of the reaction gas NF3 is in the range of 50-90 sccm, the effective power is 20-60 W, and the etching rate is in the range of

[0067] The reaction gas NF3 and NH3 chemically react with the oxide on the surface of the semiconductor structure, thereby achieving etching of the isolation dielectric layer 300,

[0068] Namely: SiO2+ NF3+ NH3→ (NH4)2SiF6.

[0069] (NH4)2SiF6 generated on the surface of the semiconductor structure is decomposed into gaseous SiF4, NH3 and HF by high temperature and removed, namely: (NH4)2SiF6→ SiF4(g)+ NH3(g)+ HF(g).

[0070] Since (NH4)2SiF6 is decomposed into gaseous SiF4 and NH3, the residual F element is avoided, and the quality of the grown isolation dielectric layer is improved.

[0071] By depositing the isolation dielectric layer in the first reaction cavity and etching part of the isolation dielectric layer on the top of the side wall of the isolation trench in the second reaction cavity, the etching is not affected by the electric field in the first reaction cavity, avoiding the influence of ions on the electrons in the deposited isolation dielectric layer during etching, thereby reducing the possibility of electron migration of the device, and improving the performance of the device.

[0072] The process parameters of the above HDP deposition process and SiCoNi etching process are shown in Table 1, and the specific process parameters are shown in Table 2, which is an example table of process parameters of the present application.

[0073] Table 2

[0074]

[0075] Among them, the corresponding Chinese name of the English in the table is as follows:

[0076] DEP: deposition; ETCH: etching; TOP RF: reaction cavity top radio frequency; SIDE RF: reaction cavity edge radio frequency; BIAS RF: vertical direction bias radio frequency; Dep rate: deposition rate; HF POWER: high frequency radio frequency power; ETCH rate: etching rate; SiH4-TOP: gas SiH4 introduced from the top of the reaction cavity.

[0077] Reference Figure 6If the isolation trench 200 is not completely filled, the steps of forming an isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench are repeated until the isolation trench is completely filled with the formed isolation dielectric layer, wherein the isolation dielectric layer 310 is formed by a plurality of isolation dielectric layers 300 completely filling the isolation trench 200.

[0078] In a specific embodiment, the steps of forming an isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench are performed once as a cycle, and the steps of repeating the steps of forming an isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench are performed three times.

[0079] Reference Figure 7 , Figure 7 Another optional flowchart of the method for forming a semiconductor structure provided by the embodiments of the present application is shown in FIG. 6.

[0080] Reference Figure 7 It can be understood that after the step of repeating the steps of forming an isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation dielectric layer, the method further comprises:

[0081] Step S6: depositing a sacrificial layer, wherein the sacrificial layer completely covers the isolation dielectric layer.

[0082] Specifically, the sacrificial layer can be formed by deposition, spin coating or other processes, and the sacrificial layer is used to provide a buffer for subsequent planarization.

[0083] Reference Figure 8 After the isolation trench 200 is completely filled with the formed isolation dielectric layer, wherein the isolation dielectric layer 310 is formed by a plurality of isolation dielectric layers completely filling the isolation trench 200. A sacrificial layer 400 is deposited, wherein the sacrificial layer 400 completely covers the isolation dielectric layer 310.

[0084] Step S7: planarizing the sacrificial layer and the isolation dielectric layer.

[0085] Specifically, the step S7 can be performed by a planarization process such as a chemical mechanical polishing process to polish the sacrificial layer and the isolation dielectric layer.

[0086] Reference Figure 9 planarizing the sacrificial layer and the isolation medium layer.

[0087] It can be seen that the method for forming a semiconductor structure provided by the embodiments of the present application forms an isolation medium layer in the isolation groove in the first reaction cavity, and the isolation medium layer conformally covers the isolation groove; after forming the isolation medium layer, part of the isolation medium layer on the top of the sidewall of the isolation groove is removed in the second reaction cavity; the isolation medium layer is deposited in the first reaction cavity, and part of the isolation medium layer on the top of the sidewall of the isolation groove is etched in the second reaction cavity, so that the etching is not affected by the electric field in the first reaction cavity, and the influence of ions on electrons in the isolation medium layer during etching is avoided, thereby reducing the possibility of electron migration of the device, and improving the performance of the device.

[0088] To solve the foregoing problems, the embodiments of the present application also provide a semiconductor structure formed based on the method for forming a semiconductor structure as described above.

[0089] The above describes the multiple embodiment schemes provided by the embodiments of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending multiple possible embodiment schemes, which can all be considered as the embodiment schemes disclosed and disclosed by the embodiments of the present application.

[0090] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application relates to a method for forming an isolation medium layer in a substrate. The method comprises the following steps: providing a substrate; forming an isolation trench in the substrate; forming an isolation dielectric layer in the isolation trench in a first reaction chamber, the isolation dielectric layer conformally covering the isolation trench; after forming the isolation dielectric layer, removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench in a second reaction chamber, wherein the SiCoNi etching process is used to remove part of the isolation dielectric layer on the top of the sidewall of the isolation trench; 2. The method of claim 1, wherein, repeating the steps of forming the isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation dielectric layer, wherein the isolation dielectric layer completely filling the isolation trench is the isolation medium layer.

3. The method of claim 2, wherein, The first preset value is 1800-2000W, and the second preset value is 1500-1700kg / m 3 .

4. The method of claim 1, wherein, The step of forming the isolation dielectric layer in the isolation trench is specifically forming the isolation dielectric layer under a preset electric field, wherein the electric field power of the preset electric field is less than a first preset value, so that the ion density in the formed isolation dielectric layer is less than a second preset value.

5. The method of claim 4, wherein, In the step of forming the isolation dielectric layer in the isolation trench, the high-density plasma process HDP is used to form the isolation dielectric layer.

6. The method of claim 4, wherein, The reaction gas used in the high-density plasma process HDP comprises O2, SiH4, SiH4-TOP, H2 and He, the flow rate of the reaction gas O2 is 70-110 sccm, the flow rate of the reaction gas SiH4 is 30-60 sccm, the flow rate of the reaction gas SiH4-TOP is 10-20 sccm, the flow rate of the reaction gas H2 is 110-150 sccm, and the flow rate of the reaction gas He is 200-400 sccm.

7. The method of claim 1, wherein, The thickness of the isolation dielectric layer is 2000-2500 angstroms.

8. The method of claim 1, wherein, The reaction gas used in the SiCoNi etching process comprises NH3 and NF3, the flow rate of the reaction gas NH3 is 120-160 sccm, the flow rate of the reaction gas NF3 is 50-90 sccm, the effective power is 20-60 W, and the etching rate is 400-800 angstroms / min.

9. The method of claim 1, wherein, The thickness of the part of the isolation dielectric layer removed on the top of the sidewall of the isolation trench is 300-400 angstroms.

10. The method of claim 1, wherein, One cycle is formed by executing the steps of forming the isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench, and the steps of repeating the steps of forming the isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench are executed for three cycles. After the step of repeating the steps of forming the isolation dielectric layer in the isolation trench and removing part of the isolation dielectric layer on the top of the sidewall of the isolation trench until the isolation trench is completely filled with the formed isolation dielectric layer, the method further comprises the following steps: depositing a sacrifice layer, the sacrifice layer completely covering the isolation medium layer; planarizing the sacrificial layer and the isolation medium layer.

11. A semiconductor structure, characterized by forming based on the method of forming the semiconductor structure according to any one of claims 1-10.

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