Formation method of semiconductor structure

Abstract

The embodiment of the invention provides a method for forming a semiconductor structure. The method comprises the following steps: providing a substrate; forming a mask lamination layer on the substrate, wherein the mask lamination layer comprises a plurality of hard mask layers which are stacked in sequence; a first opening is formed in the top hard mask layer in the multiple hard mask layers, the first opening exposes the top of the next hard mask layer adjacent to the top hard mask layer, and the upper hard mask layer and the lower hard mask layer adjacent to each other in the multiple hard mask layers have an etching selection ratio; forming openings in other hard mask layers below the top hard mask layer along the first opening layer by layer until a second opening exposing the top of the substrate is formed; and removing a part of thickness of the substrate along the second opening so as to form an isolation groove in the substrate. By adopting the technical scheme, the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As the integration of semiconductor devices increases, tens of millions of semiconductor elements are formed on a single chip. In order for each semiconductor element to perform its own function, the semiconductor elements need to be electrically insulated from each other.

[0003] Shallow trench isolation (STI) is a commonly used electrical isolation technology that achieves isolation between semiconductor components by forming an insulating material in a substrate.

[0004] However, the electrical performance of semiconductor devices formed so far still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which can improve the electrical performance of the semiconductor structure.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0007] providing a substrate;

[0008] forming a mask stack on the substrate, the mask stack comprising a plurality of hard mask layers stacked in sequence;

[0009] forming a first opening in a top hard mask layer in the multi-layer hard mask layer, wherein the first opening exposes a top portion of a next hard mask layer adjacent to the top hard mask layer, wherein adjacent upper hard mask layers and lower hard mask layers in the multi-layer hard mask layer have an etching selectivity ratio;

[0010] Forming openings in other hard mask layers below the top hard mask layer layer by layer along the first opening until a second opening exposing the top of the substrate is formed;

[0011] A portion of the thickness of the substrate is removed along the second opening to form an isolation trench in the substrate.

[0012] Optionally, before forming the first opening in the top hard mask layer in the multi-layer hard mask layer, the method further includes:

[0013] forming a photolithography layer covering the top hard mask layer on the substrate, wherein the photolithography layer has a third opening exposing the top of the top hard mask layer;

[0014] The step of forming a first opening in a top hard mask layer in the multi-layer hard mask layer comprises:

[0015] removing the top hard mask layer exposed by the third opening along the third opening until the top of the next hard mask layer adjacent to the top hard mask layer is exposed to form a first opening;

[0016] Before forming the second opening exposing the top of the substrate, the method further includes:

[0017] The photoresist layer is removed.

[0018] Optionally, in the step of forming the first opening, a portion of the thickness of the photolithography layer is also removed.

[0019] Optionally, the thickness of the removed photolithography layer is 0 angstroms to 1800 angstroms.

[0020] Optionally, a first dry etching process is used to form a first opening in a top hard mask layer in the multi-layer hard mask layer, and in the step of performing the first dry etching process, the first dry etching process has an etching selectivity ratio for the top hard mask layer and the photolithography layer.

[0021] Optionally, parameters of the first dry etching process include: etching gas includes CF4, CHF3 and HE, energy RF power is 200W to 400W, and bias power is 50W to 300W.

[0022] Optionally, a second dry etching process is used to form openings in other hard mask layers below the top hard mask layer layer by layer, and in the step of performing the second dry etching process, the second dry etching process has an etching selectivity ratio for adjacent upper hard mask layers and lower hard mask layers in the multi-layer hard mask layers.

[0023] Optionally, process parameters of the second dry etching process include: etching gas includes CHF3, HE and O2, energy RF power is 800W to 1200W, and bias power is 50W to 300W.

[0024] Optionally, a third dry etching process is used to remove a portion of the thickness of the substrate to form an isolation groove in the substrate.

[0025] Optionally, process parameters of the third dry etching process include: etching gases include CL2, HBR, N2, HE and O2, energy RF power is 300W to 800W, and bias power is 50W to 400W.

[0026] Optionally, along the normal direction of the substrate, the depth of the isolation groove is 250 nm to 450 nm.

[0027] Optionally, a buffer layer is provided on the substrate;

[0028] In the step of forming the second opening exposing the top of the substrate, a portion of the buffer layer is removed.

[0029] Optionally, the multi-layer hard mask layer includes: a first hard mask layer located on the substrate, and a second hard mask layer located on the first hard mask layer, wherein the second hard mask layer is the top hard mask layer.

[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0031] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first opening is formed in a top hard mask layer in a multi-layer hard mask layer, and the first opening exposes the top of a next hard mask layer adjacent to the top hard mask layer; along the first opening, openings can be formed layer by layer in other hard mask layers below the top hard mask layer until a second opening is formed that exposes the top of the substrate; and then along the second opening, a portion of the thickness of the substrate can be removed to form an isolation groove in the substrate. In the process of forming the second opening, by making the adjacent upper hard mask layer and the lower hard mask layer in the multi-layer hard mask layer have an etching selectivity, and the bottom hard mask layer in the multi-layer hard mask layer has an etching selectivity, the flatness of the side wall of the formed second opening can be improved, and then the flatness of the side wall of the isolation groove can be improved, and the generation of holes in the subsequent formation of the isolation structure can be reduced or avoided, thereby improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 6 It is a schematic cross-sectional structure diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of forming semiconductor structures currently needs to be improved. Specifically, when forming an isolation trench in a substrate, an opening is usually formed in one step to expose the top of the substrate, and then a portion of the thickness of the substrate is etched along the opening to form the isolation trench.

[0034] The inventors found that in the step of forming an opening to expose the top of the substrate in one step, the flatness of the sidewalls of the opening is poor, resulting in rough sidewalls of the opening, which is prone to produce holes when an isolation structure is subsequently formed, thereby reducing the working performance of the semiconductor structure.

[0035] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a mask stack on the substrate, the mask stack comprising a plurality of hard mask layers stacked in sequence; forming a first opening in a top hard mask layer among the plurality of hard mask layers, the first opening exposing the top of a next hard mask layer adjacent to the top hard mask layer, wherein the adjacent upper hard mask layer and lower hard mask layer in the plurality of hard mask layers have an etching selectivity; along the first opening, openings are formed in other hard mask layers below the top hard mask layer layer by layer until a second opening exposing the top of the substrate is formed; along the second opening, removing a portion of the thickness of the substrate to form an isolation groove in the substrate, wherein the bottom hard mask layer in the plurality of hard mask layers has an etching selectivity.

[0036] In the process of forming the second opening, the present invention can improve the flatness of the side wall of the formed second opening by making the adjacent upper hard mask layer and lower hard mask layer in the multi-layer hard mask layer have an etching selectivity ratio, and the bottom hard mask layer in the multi-layer hard mask layer has an etching selectivity ratio, thereby improving the flatness of the side wall of the isolation groove, reducing or avoiding the generation of holes in the subsequent formation of the isolation structure, and thus improving the electrical performance of the semiconductor structure.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.

[0038] Figures 1 to 6 A schematic cross-sectional structural diagram of a semiconductor device formation process provided by an embodiment of the present invention.

[0039] See also Figure 1 , providing a substrate 100.

[0040] In this embodiment, the substrate 100 may provide a process operation basis for a formation process of a semiconductor structure, wherein the semiconductor structure may include a fin field effect transistor (FinFET) or a gate all around transistor (GAA).

[0041] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0042] In some embodiments, the base may further include a substrate, and a plurality of discrete fins located above the substrate.

[0043] See next Figure 1 The substrate 100 also has a buffer layer 102 .

[0044] The buffer layer 102 is used to protect the substrate 100 to reduce or avoid damage to the surface of the substrate 100 .

[0045] In this embodiment, the buffer layer 102 may be formed on the substrate 100 by using at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0046] In this embodiment, the material of the buffer layer 102 may include one or more of silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride oxycarbon, boron nitride and boron carbonitride.

[0047] As an example, the material of the buffer layer 102 is silicon oxide.

[0048] See also Figure 2 , a mask stack 108 is formed on the substrate 100, and the mask stack 108 includes a plurality of hard mask layers stacked in sequence.

[0049] The mask stack 108 is used to provide an opening to expose the top of the substrate 100 .

[0050] In this embodiment, at least one deposition process selected from the group consisting of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process may be used to form a plurality of hard mask layers stacked sequentially on the substrate 100 .

[0051] In a specific embodiment, see Figure 2 The multi-layer hard mask layer may include a first hard mask layer 104 located on the substrate 100 , and a second hard mask layer 106 located on the first hard mask layer 104 .

[0052] In the present embodiment, when the multi-layer hard mask layer may include a first hard mask layer 104 and a second hard mask layer 106, the second hard mask layer 106 serves as a top hard mask layer, and the first hard mask layer 104 serves as a bottom hard mask layer; and, the second hard mask layer 106 and the first hard mask layer 104 are adjacent hard mask layers, that is, the second hard mask layer 106 is an upper hard mask layer among the adjacent hard mask layers, and the first hard mask layer 104 is a lower hard mask layer among the adjacent hard mask layers.

[0053] In this embodiment, the first hard mask layer 104 and the second hard mask layer 106 are both made of insulating materials.

[0054] For example, the material of the first hard mask layer 104 may include one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbon oxynitride, boron nitride, and boron carbon nitride.

[0055] As an example, the material of the first hard mask layer 104 is silicon nitride.

[0056] The material of the second hard mask layer 106 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbon oxynitride, boron nitride, and boron carbonitride.

[0057] As an example, the material of the second hard mask layer 106 is silicon oxide.

[0058] In some other embodiments, the multi-layer hard mask layer may further include more than three hard mask layers. The embodiment of the present invention does not impose any limitation on the number of layers of the multi-layer hard mask layer.

[0059] See also Figure 3 and Figure 4 A first opening K1 is formed in a top hard mask layer among the multiple hard mask layers, and the first opening K1 exposes a top of a next hard mask layer adjacent to the top hard mask layer.

[0060] The first opening K1 is used to form a second opening K2 (see Figure 5 ) provides space.

[0061] In a specific embodiment, a first opening K1 exposing a top portion of the first hard mask layer 104 may be formed in the second hard mask layer 106 .

[0062] See also Figure 3 and Figure 4 Before forming the first opening K1 in the top hard mask layer of the multi-layer hard mask layer, the method for forming the semiconductor structure further includes:

[0063] See also Figure 3 A photoresist layer 114 covering the top hard mask layer is formed on the substrate 100 , and the photoresist layer 114 has a third opening K3 exposing the top of the top hard mask layer.

[0064] In this embodiment, the photoresist layer 114 may include an anti-reflective coating layer 110 located on the second hard mask layer 106 and a photoresist layer 112 located on the anti-reflective coating layer 110 .

[0065] In this embodiment, the material of the anti-reflective coating 110 includes: a dielectric anti-reflective coating (DARC) material or a bottom anti-reflective coating (BARC) material.

[0066] In a specific embodiment, a photoresist layer 114 may be formed on the second hard mask layer 106 , and the photoresist layer 114 has a third opening K3 exposing the top of the second hard mask layer 106 .

[0067] In this case, the step of forming the first opening K1 includes: removing the top hard mask layer exposed by the third opening K3 along the third opening K3 until the top of the next hard mask layer adjacent to the top hard mask layer is exposed to form the first opening K1.

[0068] In a specific embodiment, the second hard mask layer 106 exposed by the third opening K3 may be removed along the third opening K3 until the top of the next first hard mask layer 104 is exposed, so as to form a first opening K1 in the second hard mask layer 106 to expose the top of the first hard mask layer 104 .

[0069] In this embodiment, a first dry etching process may be used to form a first opening K1 in a top hard mask layer among the multiple hard mask layers.

[0070] In a specific embodiment, a first dry etching process may be used to remove a portion of the second hard mask layer 106 along the third opening K3 and expose the top of the next first hard mask layer 104 to form a first opening K1 in the second hard mask layer 106 .

[0071] In this embodiment, in the step of performing the first dry etching process, the first dry etching process has an etching selectivity ratio to the top hard mask layer and the photoresist layer.

[0072] In the present embodiment, in the step of executing the first dry etching process, the first dry etching process has an etching selectivity ratio for the top hard mask layer and the photolithography layer, wherein "the first dry etching process has an etching selectivity ratio for the top hard mask layer and the photolithography layer" means that by adjusting the process parameters of the first dry etching process, the etching selectivity ratios of the first dry etching process for the top hard mask layer and the photolithography layer respectively can be changed, so that the top hard mask layer and the photolithography layer have a higher etching selectivity ratio, so as to reduce the consumption of the photolithography layer, thereby reducing the problem of rough lines of the isolation groove caused by insufficient photoresist protection.

[0073] In a specific embodiment, the first dry etching process has an etching selectivity ratio between the second hard mask layer 106 and the photoresist layer 112 , so that the consumption of the photoresist layer 112 can be reduced.

[0074] This is because, in this embodiment, as the technology nodes continue to shrink, this requires the use of smaller and smaller wavelength light and matching photoresists during the photolithography process. The continuous reduction in wavelength also limits the upper limit of the optimal thickness of the photoresist. For example, in this embodiment, the maximum thickness of the photoresist used does not exceed 200nm.

[0075] Moreover, the characteristics of the photoresist determine the size of the etching rate. The photoresist used in the present invention has a very fast etching rate. Therefore, during the etching process, if there is not enough photoresist thickness as protection, the uneven etching rate will cause uneven photoresist residue on a line, which will easily cause uneven line roughness.

[0076] In this case, by making the first dry etching process have an etching selectivity ratio for the top hard mask layer and the photoresist layer, consumption of the photoresist layer can be reduced, thereby reducing the problem of rough lines of the isolation grooves caused by insufficient photoresist protection.

[0077] In this embodiment, the parameters of the first dry etching process include: etching gas includes CF4, CHF3 and HE, energy RF power is 200W to 400W, and bias power is 50W to 300W.

[0078] See next Figure 3 and Figure 4 In the step of forming the first opening K1 , a portion of the thickness of the photoresist layer 114 is also removed.

[0079] In this embodiment, the thickness of the removed photoresist layer 114 cannot be too large or too small. If the thickness of the removed photoresist layer 114 is too large, the remaining photoresist layer 114 will be too small to provide protection. If the thickness of the removed photoresist layer 114 is too small, it will increase the difficulty of subsequent removal of the photoresist layer 114. Therefore, in this embodiment, the thickness of the removed photoresist layer 114 is 0 angstroms to 1800 angstroms.

[0080] In this embodiment, the removal thickness of the photoresist layer 112 may be used to represent the removal thickness of the photoresist layer 114 .

[0081] In a specific embodiment, see Figure 3 and Figure 4 In the step of forming the first opening K1 , a portion of the photoresist layer 112 is also removed.

[0082] See also Figure 5 , along the first opening K1 , openings are formed layer by layer in other hard mask layers below the top hard mask layer until a second opening K2 is formed to expose the top of the substrate 100 .

[0083] The second opening K2 is used to provide a process window for forming an isolation trench in the substrate 100 .

[0084] In this embodiment, a second dry etching process may be used to form openings in other hard mask layers below the top hard mask layer layer by layer until a second opening K2 is formed.

[0085] In the present embodiment, in the step of executing the second dry etching process, the second dry etching process has an etching selectivity ratio for adjacent upper hard mask layers and lower hard mask layers in the multi-layer hard mask layers, wherein "the second dry etching process has an etching selectivity ratio for adjacent upper hard mask layers and lower hard mask layers in the multi-layer hard mask layers" means that by adjusting the process parameters of the second dry etching process, the etching selectivity ratio of the second dry etching process to adjacent upper hard mask layers and lower hard mask layers in the multi-layer hard mask layers can be changed, so that the upper hard mask layer and the lower hard mask layer have a higher etching selectivity ratio to reduce the consumption of the upper hard mask layer, so that more upper hard mask layers can be retained, and the flatness of the side wall of the isolation groove is further improved.

[0086] It should be noted that adjacent hard mask layers refer to any two adjacent hard mask layers in a multi-layer hard mask layer, wherein the hard mask layer located at the upper layer in the adjacent hard mask layers is the upper hard mask layer in the adjacent hard mask layers, and the hard mask layer located at the lower layer in the adjacent hard mask layers is the lower hard mask layer in the adjacent hard mask layers.

[0087] In this embodiment, the process parameters of the second dry etching process include: etching gas includes CHF3, HE and O2, energy RF power is 800W to 1200W, and bias power is 50W to 300W.

[0088] In some embodiments, when a buffer layer 102 is formed on the substrate 100 , a portion of the buffer layer 102 needs to be removed in the step of forming the second opening K2 exposing the top of the substrate 100 .

[0089] In a specific embodiment, a second dry etching process may be used to remove the first hard mask layer 104 below the second hard mask layer 106 and the buffer layer 102 below the first hard mask layer 104 along the first opening K1 to form a second opening K2 exposing the top of the substrate 100 .

[0090] Furthermore, in the step of performing the second dry etching process, by making the second dry etching process have an etching selectivity ratio between the second hard mask layer 106 and the first hard mask layer 104 , consumption of the second hard mask layer 106 can be reduced.

[0091] In this embodiment, see Figure 5 Before forming the second opening K2 exposing the top of the substrate 100 , the photoresist layer 114 is removed to expose the top of the second hard mask layer 106 .

[0092] In this embodiment, after forming the first opening, the oxygen content and the values ​​of the energy RF power and bias power can be switched, and the carbon-containing photoresist can be oxidized by oxygen to generate CO2, CO and other substances which are taken away by the vacuum system to remove the photoresist layer 114.

[0093] That is, in this embodiment, the step of forming the first opening K1 and the step of removing the photoresist layer 114 are performed in the same processing equipment.

[0094] After forming the second opening K2, see Figure 6 , a portion of the thickness of the substrate 100 is removed along the second opening K2 to form an isolation groove 120 in the substrate 100 , and the isolation groove 120 is used to provide space for forming an isolation structure.

[0095] In the process of forming the second opening, by making the adjacent upper hard mask layer and lower hard mask layer in the multi-layer hard mask layer have an etching selectivity ratio, and the bottom hard mask layer in the multi-layer hard mask layer has an etching selectivity ratio, the flatness of the side wall of the formed second opening can be improved, and then the flatness of the side wall of the isolation groove can be improved, reducing or avoiding the generation of holes in the subsequent formation of the isolation structure, thereby improving the electrical performance of the semiconductor structure.

[0096] In this embodiment, a third dry etching process may be used to remove a portion of the thickness of the substrate 100 to form an isolation trench 120 in the substrate 100 .

[0097] In this embodiment, the process parameters of the third dry etching process include: etching gases include CL2, HBR, N2, HE and O2, energy RF power is 300 to 800W, and bias power is 50W to 400W.

[0098] In this embodiment, the thickness of the removed substrate 100 cannot be too large or too small. If the thickness of the removed substrate 100 is too large, it will occupy a larger area in the substrate 100 along the normal direction of the substrate 100, affecting the growth of other structures; if the thickness of the removed substrate 100 is too small, that is, the depth of the isolation groove 120 is small, it is easy to cause the isolation structure formed subsequently to fail to play an isolation role. For this reason, in this embodiment, along the normal direction of the substrate 100, the depth of the isolation groove 120 is 250nm to 450nm.

[0099] In this embodiment, after the isolation trench 120 is formed, an isolation structure may be formed in the isolation trench 120 , and the isolation structure plays a role in electrically isolating adjacent fins.

[0100] In some embodiments, the material of the isolation structure may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbon oxynitride.

[0101] In this embodiment, the material of the isolation structure may be silicon oxide.

[0102] In some embodiments, the substrate 100 may further have a gate structure, and the substrate at both sides of the gate structure has source and drain doping regions, and the gate structure exposes the source and drain doping regions.

[0103] When the device is working, the gate structure is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure is a metal gate structure, and the gate structure may include a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0104] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0105] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0106] In this embodiment, the gate electrode layer may include one or both of a work function layer and an electrode layer.

[0107] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and silicon titanium nitride.

[0108] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0109] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0110] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0111] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0112] In this embodiment, the gate structure is described by taking a metal gate structure as an example. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0113] In some embodiments, a gate sidewall is formed on the sidewall of the gate structure, and the gate sidewall can be used to protect the gate structure.

[0114] In this embodiment, the material of the gate spacer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbon oxynitride, boron nitride or boron carbon nitride.

[0115] As an example, the material of the gate spacer is silicon nitride.

[0116] In this embodiment, the source-drain doped region can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the source-drain doped region can provide a carrier source.

[0117] The process of forming the source-drain doped regions includes: forming grooves in the substrate on both sides of the gate structure; forming a stress layer that fills the grooves; in the process of forming the stress layer, in-situ doping the stress layer to form the source-drain doped regions; or, after forming the stress layer, doping the stress layer to form the source-drain doped regions.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a mask stack on the substrate, the mask stack comprising a plurality of hard mask layers stacked in sequence; forming a first opening in a top hard mask layer in the multi-layer hard mask layer, wherein the first opening exposes a top portion of a next hard mask layer adjacent to the top hard mask layer, wherein adjacent upper hard mask layers and lower hard mask layers in the multi-layer hard mask layer have an etching selectivity ratio; Forming openings in other hard mask layers below the top hard mask layer layer by layer along the first opening until a second opening exposing the top of the substrate is formed; A portion of the thickness of the substrate is removed along the second opening to form an isolation trench in the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first opening in the top hard mask layer of the multi-layer hard mask layer, the method further includes: forming a photolithography layer covering the top hard mask layer on the substrate, wherein the photolithography layer has a third opening exposing the top of the top hard mask layer; The step of forming a first opening in a top hard mask layer in the multi-layer hard mask layer comprises: removing the top hard mask layer exposed by the third opening along the third opening until the top of the next hard mask layer adjacent to the top hard mask layer is exposed to form a first opening; Before forming the second opening exposing the top of the substrate, the method further comprises: The photoresist layer is removed.

3. The method for forming a semiconductor structure according to claim 2, wherein: In the step of forming the first opening, a portion of the thickness of the photoresist layer is also removed.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: The thickness of the removed photoresist layer is 0 angstroms to 1800 angstroms.

5. The method for forming a semiconductor structure according to claim 2, wherein: A first dry etching process is used to form a first opening in a top hard mask layer in the multi-layer hard mask layer, and in the step of performing the first dry etching process, the first dry etching process has an etching selectivity ratio for the top hard mask layer and the photolithography layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that: The parameters of the first dry etching process include: etching gas includes CF4, CHF3 and HE, energy RF power is 200W to 400W, and bias power is 50W to 300W.

7. The method for forming a semiconductor structure according to claim 1, wherein: A second dry etching process is adopted to form openings in other hard mask layers below the top hard mask layer layer by layer, and in the step of performing the second dry etching process, the second dry etching process has an etching selectivity ratio for adjacent upper hard mask layers and lower hard mask layers in the multi-layer hard mask layers.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The process parameters of the second dry etching process include: etching gas includes CHF3, HE and O2, energy RF power is 800W to 1200W, and bias power is 50W to 300W.

9. The method for forming a semiconductor structure according to claim 1, wherein: A third dry etching process is used to remove a portion of the thickness of the substrate to form an isolation groove in the substrate.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: The process parameters of the third dry etching process include: etching gases include CL2, HBR, N2, HE and O2, energy RF power is 300W to 800W, and bias power is 50W to 400W.

11. The method for forming a semiconductor structure according to claim 1, 9 or 10, characterized in that: Along the normal direction of the substrate, the depth of the isolation groove is 250nm to 450nm.

12. The method for forming a semiconductor structure according to claim 1, wherein: The substrate has a buffer layer; In the step of forming the second opening exposing the top of the substrate, a portion of the buffer layer is removed.

13. The method for forming a semiconductor structure according to claim 1, wherein: The multi-layer hard mask layer includes: a first hard mask layer located on the substrate, and a second hard mask layer located on the first hard mask layer, wherein the second hard mask layer is the top hard mask layer.

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