Semiconductor Structure and Method of Fabricating the Same

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. A recessed area is formed on the top surface of the isolation structure by means of a grinding process for forming the isolation structure. A protective layer is formed in the recessed area to protect the isolation structure. The hard mask layer is etched away by using the protective layer to protect the isolation structure, avoiding etching the isolation structure during the process of removing the hard mask layer, which may cause height differences in the isolation structures in different regions. After removing the hard mask layer, an epitaxial layer is epitaxially formed on the top surface of the substrate in the present disclosure. The substrate between the epitaxial layer and the isolation structure serves as the active region together, so that the top surface of the active region is flush with the top surface of the isolation structure, realizing the adjustment of the height of the active region, eliminating the step height between the isolation structure and the active region, and being beneficial to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] A shallow trench isolation (STI) structure is used to isolate active regions from each other to prevent leakage and the like. The STI structure is crucial for the performance and yield of the finally formed semiconductor structure. The manufacturing process of the STI structure results in a step height of the shallow trench isolation structure, that is, the height of the STI structure above the surface of the semiconductor substrate, and the step height of the STI structure has a significant impact on the performance of the semiconductor structure.

[0003] In particular, the pattern densities of the STI structures in different regions are different. During the manufacturing process of the STI structure, the step heights of the STI structures in different pattern density regions may be different, affecting the performance of the semiconductor structure. As the critical dimensions of the semiconductor structure continue to shrink, it becomes more and more difficult to control the step heights of the STI structures in different pattern density regions, and the step height difference between the STI structures in different pattern density regions has a greater impact on the performance of the semiconductor structure. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof to solve the problem that the manufacturing process of the shallow trench isolation structure in the prior art results in different step heights of the shallow trench isolation structures in different pattern density regions, affecting the performance of the semiconductor structure.

[0005] In a first aspect, the present disclosure provides a manufacturing method of a semiconductor structure, including:

[0006] Providing an initial structure, where the initial structure includes a substrate and an isolation structure formed in the substrate, the top surface of the substrate is covered by a hard mask layer, the top surface of the isolation structure is higher than the top surface of the substrate, and the top surface of the isolation structure is recessed relative to the hard mask layer;

[0007] Forming a protective layer to cover the top surface of the isolation structure and fill the recessed area of the isolation structure;

[0008] Etching and removing the hard mask layer to expose the top surface of the substrate;

[0009] Epitaxially growing an epitaxial layer on the top surface of the substrate, where the epitaxial layer is used as an active region, and the top surface of the active region is flush with the top surface of the protective layer.

[0010] Optionally, forming a protective layer to cover the top surface of the isolation structure and fill the recessed area of the isolation structure includes:

[0011] A protective material layer is formed, covering the top surface of the isolation structure, the top surface of the hard mask layer, and filling the recess at the top of the isolation structure;

[0012] The protective material layer is polished to expose the top surface of the hard mask layer, and the remaining protective material layer in the recess at the top of the isolation structure forms the protection layer.

[0013] Optionally, the material of the protection layer includes at least one of silicon oxycarbide, silicon carbonitride, or silicon oxynitride.

[0014] Optionally, an oxide layer is formed on the top surface of the substrate, and the oxide layer is disposed between the substrate and the hard mask layer;

[0015] After etching away the hard mask layer, the oxide layer is etched away to expose the top surface of the substrate.

[0016] Optionally, providing an initial structure, including:

[0017] Providing an initial substrate, forming the hard mask layer on the top surface of the initial substrate, and the hard mask layer defines the pattern of the isolation structure;

[0018] Etching the initial substrate according to the hard mask layer to form isolation trenches in the initial substrate, and the remaining etched initial substrate forms the substrate;

[0019] Forming an isolation layer, the isolation layer filling the isolation trenches and covering the top surface of the hard mask layer;

[0020] Polishing away the isolation layer on the hard mask layer, and the remaining isolation layer in the isolation trenches forms the isolation structure.

[0021] Optionally, the manufacturing method further includes:

[0022] Forming a pad oxide layer, the pad oxide layer covering at least the top surface of the active region.

[0023] Optionally, the substrate includes a first region and a second region, and the sizes of the isolation structures in the first region and the second region are different;

[0024] After epitaxially forming the epitaxial layer, the top surfaces of the first region and the second region are flush.

[0025] In a second aspect, the present disclosure provides a semiconductor structure, including:

[0026] A substrate;

[0027] An isolation structure is arranged in the substrate to divide the substrate into active areas arranged at intervals, and a top surface of the isolation structure has a concave area;

[0028] A protective layer, covering the top surface of the isolation structure and filling a recessed area of ​​the isolation structure;

[0029] An epitaxial layer is arranged on the top surface of the substrate, the epitaxial layer and the substrate between the isolation structure serve together as the active area, and the top surface of the active area is flush with the top surface of the protective layer.

[0030] Optionally, the material of the protective layer includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

[0031] Optionally, the substrate includes a first region and a second region, the isolation structure in the first region and the isolation structure in the second region have different sizes; and the top surfaces of the first region and the second region are flush.

[0032] The semiconductor structure and the manufacturing method thereof disclosed in the present invention utilize a recessed area formed on the top surface of the isolation structure during the grinding process of forming the isolation structure, form a protective layer in the recessed area to protect the isolation structure, and utilize the protective layer to protect the isolation structure to etch and remove the hard mask layer, thereby preventing the isolation structure from being etched during the process of removing the hard mask layer, resulting in height differences in the isolation structures in different areas. After removing the hard mask layer, the present invention forms an epitaxial layer on the top surface of the substrate by epitaxial growth, and the substrate between the epitaxial layer and the isolation structure serves as an active area together, so that the top surface of the active area is flush with the top surface of the isolation structure, thereby achieving adjustment of the height of the active area, eliminating the step height between the isolation structure and the active area, and facilitating improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a process flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0035] Figure 2 is a schematic diagram of a structure after a hard mask layer is formed on an initial substrate provided in an embodiment;

[0036] Figure 3 is a schematic diagram of a structure after an isolation trench is formed in an initial substrate provided in an embodiment;

[0037] Figure 4 Schematic diagram of the structure after forming the isolation layer in an embodiment;

[0038] Figure 5 Schematic diagram of the initial structure provided in an embodiment;

[0039] Figure 6 Schematic diagram of the structure after forming the protective material layer in an embodiment;

[0040] Figure 7 Schematic diagram of the structure after forming the protective layer in an embodiment;

[0041] Figure 8 Schematic diagram of the structure after etching and removing the hard mask layer in an embodiment;

[0042] Figure 9 Schematic diagram of the structure after etching to expose the top surface of the substrate in an embodiment;

[0043] Figure 10 Schematic diagram of the structure after forming the epitaxial layer in an embodiment;

[0044] Figure 11 Schematic diagram of the structure after forming the pad oxide layer in an embodiment.

[0045] Description of reference numerals:

[0046] 100, initial structure; 10, substrate; 11, active region; 101, initial substrate; 102, isolation trench; 103, oxide layer; 20, isolation structure; 120, first isolation structure; 220, second isolation structure; 21, isolation layer; 30, hard mask layer; 40, protective layer; 41, protective material layer; 60, epitaxial layer; 70, pad oxide layer; A1, first region; A2, second region. Detailed implementation manners

[0047] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0049] In the related art, the manufacturing method of a shallow trench isolation structure is as follows: a hard mask layer is formed on a substrate, the substrate is etched according to the hard mask layer to form a trench in the substrate, and then an isolation material is filled into the trench to form a shallow trench isolation structure. Then, the hard mask layer is etched and removed. After removing the hard mask layer, the top surface of the shallow trench isolation structure is higher than the top surface of the substrate. In order to eliminate or reduce the step height of the shallow trench isolation structure, a re-etching step needs to be performed on the shallow trench isolation structure. However, the pattern density of the shallow trench isolation structures in different regions is different, and after re-etching the shallow trench isolation structures, the height differences between the shallow trench isolation structures and the substrate in different regions may be different, affecting the performance of the semiconductor structure. The process of re-etching the shallow trench isolation structure may etch the substrate, forming notches on the sidewalls of the active region of the substrate.

[0050] Moreover, when filling an isolation material into the trench to form a shallow trench isolation structure, it is necessary to grind and remove the isolation material on the hard mask layer, and the grinding process may cause the top surface of the shallow trench isolation structure to be sunken, affecting the execution of subsequent device manufacturing processes.

[0051] In view of this, the present disclosure provides a semiconductor structure and a manufacturing method thereof. By using the sunken area formed on the top surface of the isolation structure during the grinding process of forming the isolation structure, a protective layer is formed in the sunken area to protect the isolation structure, and the hard mask layer is etched and removed by using the protective layer to protect the isolation structure, avoiding etching the isolation structure during the process of removing the hard mask layer and resulting in height differences in different regions of the isolation structure; after removing the hard mask layer, an epitaxial layer is epitaxially formed on the top surface of the substrate in the present disclosure, and the substrate between the epitaxial layer and the isolation structure serves as the active region together, so that the top surface of the active region is flush with the top surface of the isolation structure, realizing the adjustment of the height of the active region, eliminating the step height between the isolation structure and the active region, and being beneficial to improving the performance of the semiconductor structure.

[0052] According to an exemplary embodiment, the present disclosure provides a manufacturing method of a semiconductor structure. Please refer to Figure 1 as shown, the manufacturing method of the semiconductor structure includes the following steps:

[0053] Step S10: Provide an initial structure, the initial structure includes a substrate and an isolation structure formed in the substrate, the top surface of the substrate is covered by a hard mask layer, the top surface of the isolation structure is higher than the top surface of the substrate, and the top surface of the isolation structure is sunken relative to the hard mask layer.

[0054] Step S20: Form a protective layer to cover the top surface of the isolation structure and fill the sunken area of the isolation structure.

[0055] Step S30: Etch and remove the hard mask layer to expose the top surface of the substrate.

[0056] Step S40: Epitaxially form an epitaxial layer on the top surface of the substrate, the epitaxial layer is used as the active region, and the top surface of the active region is flush with the top surface of the protective layer.

[0057] Figures 2 - 11 FIG. shows schematic diagrams of various stages of a method for fabricating a semiconductor structure according to some embodiments in this example. The following is a description of the method for fabricating a semiconductor structure according to some embodiments in this example with reference to Figures 2 - 11 introduce the method for fabricating a semiconductor structure according to some embodiments in this example.

[0058] In step S10, with reference to Figure 5 shown, in combination with Figures 2 - 4 , the initial structure 100 includes a substrate 10 and an isolation structure 20. The isolation structure 20 extends from the top surface of the substrate 10 towards the bottom surface of the substrate 10. A hard mask layer 30 for fabricating the isolation structure 20 is formed on the top surface of the substrate 10. The top surface of the isolation structure 20 is higher than the top surface of the substrate 10, and the top surface of the isolation structure 20 is recessed relative to the hard mask layer 30. Among them, the recess on the top surface of the isolation structure 20 is formed during the grinding process of fabricating the isolation structure 20.

[0059] It can be understood that the depths of the recesses of the isolation structures 20 in different regions of the substrate 10 relative to the hard mask layer 30 are not exactly the same. Different graphic densities or sizes of the isolation structures 20 in different regions may all affect the fabrication process of the isolation structures 20, resulting in different depths of the recesses on the top surfaces of the isolation structures 20 in different regions. Even the heights of the top surfaces of the isolation structures 20 in different regions may also be different.

[0060] Among them, the substrate 10 is made of a semiconductor material. The semiconductor material can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials with semiconductor properties, such as group III-V compounds such as gallium arsenide.

[0061] The material of the hard mask layer 30 can include a carbon material. Alternatively, the hard mask layer 30 can also be other suitable materials that can be removed in wet etching. The hard mask layer 30 can include a single-layer or multi-layer structure.

[0062] The isolation structure 20 can include a single-layer or multi-layer isolation layer 21. By way of example, the isolation structure 20 can include silicon oxide.

[0063] In some embodiments, step S20 of forming a protective layer 40 to cover the top surface of the isolation structure 20 and fill the recessed area of the isolation structure 20 includes the following steps:

[0064] Step S21: Form a protective material layer 41. The protective material layer 41 covers the top surface of the isolation structure 20, the top surface of the hard mask layer 30, and fills the recess at the top of the isolation structure 20.

[0065] With reference to Figure 6, a protective material layer 41 can be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The protective material layer 41 covers the top surface of the isolation structure 20, the top surface of the hard mask layer 30, and fills the recess at the top of the isolation structure 20.

[0066] Step S22: Polish the protective material layer 41 to expose the top surface of the hard mask layer 30. The protective material layer 41 in the recess at the top of the isolation structure 20 remains after polishing to form a protective layer 40.

[0067] Refer to Figure 7 , using the top surface of the hard mask layer 30 as the polishing end point, polish the protective material layer 41 by chemical mechanical polishing (CMP). The polishing rate of the protective material layer 41 is close to that of the hard mask layer 30. After polishing and removing the protective material layer 41 on the top surface of the hard mask layer 30, the protective material layer 41 in the recess at the top of the isolation structure 20 forms a protective layer 40, and the top surface of the protective layer 40 is substantially flush with the top surface of the hard mask 30.

[0068] In some embodiments, the material of the protective layer 40 includes at least one of silicon oxycarbide, silicon carbonitride, or silicon oxynitride.

[0069] In this embodiment, the material of the protective layer 40 includes silicon oxycarbide.

[0070] The top surface of the protective layer 40 is a plane, and the top surface of the protective layer 40 is flush with the top surface of the hard mask layer 30. In this way, the protective layer 40 fills the recessed area at the top of the isolation structure 20. The protective layer 40 can not only protect the isolation structure 20, but also eliminate the height difference of the isolation structure 20 in different regions.

[0071] In step S30, refer to Figure 8 、 Figure 9 , the hard mask layer 30 can be etched by a wet process to expose the top surface of the substrate 10 after removing the hard mask layer 30. The etching solution used in the wet process has a high etching selectivity between the hard mask layer 30 and the substrate 10 and the isolation structure 20, so that after removing the hard mask layer 30, the top surfaces of the substrate 10 in different regions and the isolation structure 20 have the same step height.

[0072] In step S40, refer to Figure 10, Molecular Beam Epitaxy (MBE), Vapor Phase Epitaxy (VPE), or Metal-organic Chemical Vapor Deposition (MOCVD) can be used to epitaxially form an epitaxial layer 60 on the top surface of the substrate 10. The material of the epitaxial layer 60 includes semiconductor materials, and the lattice direction of the epitaxial layer 60 is the same as the crystal direction of the substrate 10. The substrate 10 between the epitaxial layer 60 and the isolation structure 20 together serves as the active region 11, and the active region 11 is used to form semiconductor devices.

[0073] The material of the epitaxial layer 60 can be selected to be the same semiconductor material as the substrate 10, or, alternatively, a semiconductor material different from the substrate 10 can be selected according to the manufacturing requirements of the device. For example, the material composition, conduction type, and resistivity characteristics of the epitaxial layer 60 are different from those of the substrate 10.

[0074] In one example, the material of the epitaxial layer 60 is the same as that of the substrate 10. The substrate 10 is a silicon substrate, and the material of the epitaxial layer 60 is single-crystalline silicon. In this way, it helps to reduce the lattice mismatch at the contact interface between the epitaxial layer 60 and the substrate 10 and improve the quality of the epitaxial layer 60 and the performance of the device.

[0075] In another example, the material of the epitaxial layer 60 is different from that of the substrate 10. The substrate 10 is a silicon substrate, and the material of the epitaxial layer 60 is germanium silicon. In this example, it can be applied to fabricate PMOS devices. Epitaxial germanium silicon forms the epitaxial layer 60, and the epitaxial layer 60 serves as the source and / or drain of the PMOS, improving the stress of the PMOS and enhancing the device performance.

[0076] In the manufacturing method of the semiconductor structure of this embodiment, a protective layer 40 is formed in the recessed area on the top surface of the isolation structure 20 to protect the isolation structure 20 with the protective layer 40. At the same time, the height difference of the isolation structure 20 is eliminated through the protective layer 40, so that the top surfaces of the protective layer 40 on the isolation structures 20 in each region are located on the same plane. After removing the hard mask layer 30, an epitaxial layer 60 is epitaxially formed on the top surface of the substrate 10 as the active region 11, so that the top surface of the active region 11 is located on the same plane as the top surface of the protective layer 40, eliminating the step height between the active region 11 and the isolation structure 20, which is beneficial to improving the performance of the semiconductor structure.

[0077] In some embodiments, step S10 provides an initial structure 100, including:

[0078] Refer to Figure 2, Step S11: Provide an initial substrate 101, and form a hard mask layer 30 on the top surface of the initial substrate 101. The hard mask layer 30 defines the pattern of the isolation structure 20. Form a hard mask layer 30 on the top surface of the initial substrate 101, pattern the hard mask layer 30 to expose a part of the top surface of the initial substrate 101, and define the pattern of the isolation structure 20 in the hard mask layer 30.

[0079] Refer to Figure 3 , Step S12: Etch the initial substrate 101 according to the hard mask layer 30 to form isolation trenches 102 in the initial substrate 101, and the remaining initial substrate 101 after etching forms the substrate 10.

[0080] Refer to Figure 4 , Step S13: Form an isolation layer 21. The isolation layer 21 fills the isolation trenches 102 and covers the top surface of the hard mask layer 30. In this embodiment, one or more isolation layers 21 can be deposited by ALD or CVD.

[0081] Refer to Figure 5 , Step S14: Grind and remove the isolation layer 21 on the hard mask layer 30, and the remaining isolation layer 21 in the isolation trenches 102 forms the isolation structure 20. In this embodiment, taking the top surface of the hard mask layer 30 as the grinding end point, polish the isolation layer 21 by CMP to remove the isolation layer 21 on the top surface of the hard mask layer 30. Since the anti-grinding property of the isolation layer 21 is lower than that of the hard mask layer 30, after the grinding stops, the top surface of the isolation layer 21 is recessed relative to the hard mask layer 30.

[0082] In some embodiments, the critical dimensions and pattern densities of the isolation trenches 102 in different regions of the substrate 10 are different. When grinding the isolation layer 21, affected by the loading effect, in the regions where the critical dimensions of the isolation trenches 102 are small and the pattern density is large, the depth of the depression on the top surface of the isolation structure 20 is greater.

[0083] In some embodiments, refer to Figure 2 , an oxide layer 103 can be formed on the top surface of the initial substrate 101. The oxide layer 103 can be formed by a deposition process or a thermal oxidation process, or the oxide layer 103 can also be formed by natural oxidation of the initial substrate 101.

[0084] In some of these examples, refer to Figure 5 , form a hard mask layer 30 on the top surface of the oxide layer 103. An oxide layer 103 is formed on the top surface of the substrate 10 of the initial structure 100, and the oxide layer 103 is disposed between the substrate 10 and the hard mask layer 30; refer to Figure 8 , Figure 9 , after etching and removing the hard mask layer 30, etch and remove the oxide layer 103 to expose the top surface of the substrate 10.

[0085] In some other examples, after etching away the oxide layer 103 on the top surface of the initial substrate 101, a hard mask layer 30 is formed on the top surface of the initial substrate 101 and is in direct contact with the initial substrate 101. In this example, a first isolation layer, a second isolation layer, and a third isolation layer can be sequentially deposited in the isolation trench 102 to form the isolation structure 20. Among them, the materials of the first isolation layer and the third isolation layer can include silicon oxide, and the material of the second isolation layer can include silicon nitride. The isolation structure 20 is an oxide-nitride-oxide (ONO) stack, which is beneficial to improving the isolation effect of the isolation structure 20 and optimizing the device performance. In this example, after etching away the hard mask layer 30, there is no need to perform the step of etching away the oxide layer 103, which can avoid damaging the first isolation layer when etching away the oxide layer 103 and avoid forming a notch on the sidewall of the isolation structure 20, ensuring the structural integrity of the isolation structure 20 and ensuring that the isolation structure 20 has a good isolation effect.

[0086] In some embodiments, the manufacturing method further includes: referring to Figure 11 As shown, step S50: form a pad oxide layer 70, and the pad oxide layer 70 covers at least the top surface of the active region 11. The pad oxide layer 70 can be formed on the top surface of the epitaxial layer 60 by a thermal oxidation process; alternatively, the pad oxide layer 70 can be formed by ALD deposition, and the pad oxide layer 70 covers the top surface of the active region 11 and the top surface of the protection layer 40.

[0087] For example, the material of the pad oxide layer 70 includes silicon oxide.

[0088] In some embodiments, referring to Figures 2 - 11 As shown, the substrate 10 includes a first region A1 and a second region A2, and the sizes of the isolation structures 20 in the first region A1 and the second region A2 are different; after epitaxially forming the epitaxial layer 60, the top surfaces of the first region A1 and the second region A2 are flush.

[0089] In this embodiment, when forming the initial structure 100, a first isolation structure 120 is formed in the first region A1 of the substrate 10, and a second isolation structure 220 is formed in the second region A2 of the substrate 10. The critical dimension of the second isolation structure 220 is greater than that of the first isolation structure 120, and the pattern density of the first isolation structure 120 in the first region A1 is greater than that of the second isolation structure 220 in the second region A2.

[0090] Referring to Figure 4 、 Figure 5, during the process of fabricating the first isolation structure 120 and the second isolation structure 220, the isolation layer 21 on the hard mask layer 30 is removed by grinding. Affected by the critical dimensions and pattern density of the first isolation structure 120 and the second isolation structure 220, the grinding rate of the first isolation structure 120 in the first region A1 is greater than that of the second isolation structure 220 in the second region A2. After the grinding stops, the height of the top surface of the first isolation structure 120 is lower than that of the top surface of the second isolation structure 220 in the second region A2, and the depth of the depression on the top surface of the first isolation structure 120 is greater than that of the depression on the top surface of the second isolation structure 220.

[0091] Referring to Figure 7 , after forming the protective layer 40, the protective layer 40 covers the top surface of the first isolation structure 120 and fills the depressed area on the top surface of the first isolation structure 120. The protective layer 40 also covers the top surface of the second isolation structure 220 and fills the depressed area on the top surface of the second isolation structure 220. The height of the top surface of the protective layer 40 on the first isolation structure 120 is flush with the height of the top surface of the protective layer 40 on the second isolation structure 220, eliminating the height difference between the first isolation structure 120 and the second isolation structure 220. This avoids the problem of different step heights between the isolation structure 20 in the first region A1 and the second region A2 and the active region 11, and also avoids the situation where the step height difference of the isolation structure 20 in different pattern density regions affects the performance of the semiconductor structure.

[0092] In some embodiments, an oxide layer 103 is formed on the top surface of the substrate 10 of the initial structure 100; after etching away the hard mask layer 30, the oxide layer 103 is etched away. In the step of etching the oxide layer 103, it is possible that the etching rate in the first region A1 is greater than that in the second region A2, resulting in the top surface of the substrate 10 in the first region A1 being lower than the top surface of the substrate 10 in the second region A2 after etching away the oxide layer 103. In this embodiment, when epitaxially growing the epitaxial layer 60, the duration of the epitaxial production is controlled so that the top surface of the epitaxial layer 60 is higher than the top surface of the protective layer 40. Then, the epitaxial layer 60 is ground to grind the top surface of the epitaxial layer 60 to be flush with the top surface of the protective layer 40, avoiding the problem of different step heights between the isolation structure 20 in the first region A1 and the second region A2 and the active region 11, and ensuring that the step height between the top surfaces of the isolation structure 20 in the first region A1, the isolation structure 20 in the second region A2 and the active region 11 is zero.

[0093] According to an exemplary embodiment, the present disclosure provides a semiconductor structure, referring to Figure 11As shown, the semiconductor structure includes a substrate 10, an isolation structure 20, a protective layer 40, and an epitaxial layer 60; the isolation structure 20 is disposed in the substrate 10, dividing the substrate 10 into spaced-apart active regions 11, and the top surface of the isolation structure 20 has a recessed area; the protective layer 40 covers the top surface of the isolation structure 20 and fills the recessed area of the isolation structure 20; the epitaxial layer 60 is disposed on the top surface of the substrate 10, and the substrate 10 between the epitaxial layer 60 and the isolation structure 20 together serves as the active region 11, and the top surface of the active region 11 is flush with the top surface of the protective layer 40. In the semiconductor structure of this embodiment, the step height between the isolation structure 20 and the active region 11 is adjusted by using the protective layer 40 on the isolation structure 20 and the epitaxial layer 60 of the active region 11, so that the top surface of the active region 11 is flush with the top surface of the isolation structure 20, realizing the adjustment of the height of the active region 11, eliminating the step height between the isolation structure 20 and the active region 11, and being beneficial to improving the performance of the semiconductor structure.

[0094] In some embodiments, referring to Figure 11 As shown, the material of the epitaxial layer 60 includes a semiconductor material, and the lattice direction of the epitaxial layer 60 is the same as the crystal direction of the substrate 10. The substrate 10 between the epitaxial layer 60 and the isolation structure 20 together serves as the active region 11, and the active region 11 is used to form semiconductor devices.

[0095] The material of the epitaxial layer 60 can be selected to be the same semiconductor material as the substrate 10, or, alternatively, a semiconductor material different from the substrate 10 can be selected according to the manufacturing requirements of the device. For example, the material composition, conductivity type, and resistivity characteristics of the epitaxial layer 60 are different from those of the substrate 10.

[0096] In one example, referring to Figure 11 As shown, the material of the epitaxial layer 60 is the same as that of the substrate 10. The substrate 10 is a silicon substrate, and the material of the epitaxial layer 60 is single-crystalline silicon. In this way, it helps to reduce the lattice mismatch at the contact interface between the epitaxial layer 60 and the substrate 10 and improve the quality of the epitaxial layer 60 and the performance of the device.

[0097] In another example, the material of the epitaxial layer 60 is different from that of the substrate 10. The substrate 10 is a silicon substrate, and the material of the epitaxial layer 60 is germanium silicon. In this example, it can be applied to fabricate PMOS devices. The epitaxial germanium silicon forms the epitaxial layer 60, and the epitaxial layer 60 serves as the source and / or drain of the PMOS, improving the stress of the PMOS and enhancing the device performance.

[0098] In some embodiments, referring to Figure 11 As shown, the material of the protective layer 40 includes at least one of silicon carbon oxide, silicon carbonitride, or silicon oxynitride.

[0099] In some embodiments, referring to Figure 11As shown, the semiconductor structure further includes a pad oxide layer 70 that covers at least the top surface of the active region 11.

[0100] In some embodiments, referring to Figure 11 As shown, the substrate 10 includes a first region A1 and a second region A2. The isolation structures 20 in the first region A1 have different sizes from those of the isolation structures 20 in the second region A2; the top surfaces of the first region A1 and the second region A2 are flush.

[0101] In some embodiments, referring to Figure 11 As shown, the critical dimension of the second isolation structure 220 is greater than that of the first isolation structure 120, and the pattern density of the first isolation structure 120 in the first region A1 is greater than that of the second isolation structure 220 in the second region A2. The height of the top surface of the first isolation structure 120 is lower than that of the top surface of the second isolation structure 220 in the second region A2, and the depth of the depression on the top surface of the first isolation structure 120 is greater than that of the depression on the top surface of the second isolation structure 220. The top surface height of the protective layer 40 on the first isolation structure 120 is flush with the top surface height of the protective layer 40 on the second isolation structure 220, eliminating the height difference between the first isolation structure 120 and the second isolation structure 220. This avoids the problem of different step heights between the isolation structures 20 in the first region A1 and the second region A2 and the active region 11, and also avoids the situation where the step height difference of the isolation structures 20 in different pattern density regions affects the performance of the semiconductor structure.

[0102] The semiconductor structure of this embodiment can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), or other types of memories.

[0103] In some embodiments, an electronic device is provided, including the semiconductor structure of the above embodiment or a semiconductor structure fabricated by the manufacturing method of the semiconductor structure of the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0104] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0105] The above-described embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing an initial structure, the initial structure comprising a substrate and an isolation structure formed in the substrate, wherein a top surface of the substrate is covered by a hard mask layer, a top surface of the isolation structure is higher than a top surface of the substrate, and the top surface of the isolation structure is recessed relative to the hard mask layer; the substrate comprises a first region and a second region, and the recess depths of the top surfaces of the isolation structure in the first region and the isolation structure in the second region are different; forming a protective layer to cover the top surface of the isolation structure and fill the recessed area of ​​the isolation structure, wherein the top surface height of the protective layer on the isolation structure in the first area is flush with the top surface height of the protective layer on the top surface of the isolation structure in the second area; Etching and removing the hard mask layer to expose the top surface of the substrate; epitaxially forming an epitaxial layer on the top surface of the substrate, wherein the epitaxial layer is used as an active region, and the top surface of the active region is flush with the top surface of the protective layer; After the epitaxial layer is formed by epitaxial growth, the top surfaces of the first region and the second region are flush.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a protection layer to cover the top surface of the isolation structure and fill the recessed area of ​​the isolation structure, comprising: forming a protective material layer, wherein the protective material layer covers a top surface of the isolation structure, a top surface of the hard mask layer, and fills a recess at the top of the isolation structure; The protective material layer is ground to expose the top surface of the hard mask layer, and the protective material layer at the recessed portion of the top of the isolation structure is ground to remain to form the protective layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The material of the protective layer includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

4. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: An oxide layer is formed on the top surface of the substrate, and the oxide layer is arranged between the substrate and the hard mask layer; After the hard mask layer is removed by etching, the oxide layer is removed by etching to expose the top surface of the substrate.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Provide an initial structure, including: Providing an initial substrate, forming the hard mask layer on a top surface of the initial substrate, wherein the hard mask layer defines a pattern of the isolation structure; Etching the initial substrate according to the hard mask layer to form an isolation trench in the initial substrate, and etching the remaining initial substrate to form the substrate; forming an isolation layer, wherein the isolation layer fills the isolation trench and covers a top surface of the hard mask layer; The isolation layer on the hard mask layer is removed by grinding, and the isolation layer remaining in the isolation trench forms the isolation structure.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The production method further comprises: A pad oxide layer is formed, wherein the pad oxide layer at least covers a top surface of the active region.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The isolation structure in the first region has a different size from the isolation structure in the second region.

8. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein the semiconductor structure comprises: substrate; An isolation structure is arranged in the substrate to divide the substrate into active areas arranged at intervals, and a top surface of the isolation structure has a concave area; A protective layer, covering the top surface of the isolation structure and filling a recessed area of ​​the isolation structure; An epitaxial layer is arranged on the top surface of the substrate, the epitaxial layer and the substrate between the isolation structure serve together as the active area, and the top surface of the active area is flush with the top surface of the protective layer.

9. The semiconductor structure according to claim 8, characterized in that: The material of the protective layer includes at least one of silicon oxycarbide, silicon carbonitride or silicon oxynitride.

10. The semiconductor structure according to claim 8, characterized in that The substrate includes a first region and a second region. The isolation structure in the first region has a different size from the isolation structure in the second region. The top surfaces of the first region and the second region are flush.

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