Chip-substrate composite semiconductor device

Abstract

The invention relates to a chip-substrate composite semiconductor device. A semiconductor device includes a semiconductor chip including a front side and a back side. The first electrode is disposed on the front side of the semiconductor chip. The inorganic substrate includes a first side, a second side opposite the first side, and a first lateral side extending between the first side and the second side. A metal layer is disposed over the first side and the first lateral side of the inorganic substrate. The first electrode is bonded to the metal layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices, and in particular to the field of high voltage semiconductor chips. Background Art

[0002] When producing thin semiconductor chips, the mechanical stability of the wafer, wafer handling, chip separation, chip handling and further packaging processes become more difficult. Some processes in the known processes use a reversible carrier system to support the semiconductor wafer or the semiconductor chip cut from the wafer during wafer handling or packaging. However, after removing this reversible carrier system, the semiconductor wafer or semiconductor chip no longer has sufficient mechanical support. In addition, thick metal layers can bring high stress to thin semiconductor wafers or semiconductor chips, causing warping or bending of semiconductor materials as a result of CTE (coefficient of thermal expansion) mismatch. Summary of the invention

[0003] According to one aspect of the present disclosure, a semiconductor device includes: a semiconductor chip having a front side and a back side, wherein a first electrode is disposed on the front side of the semiconductor chip. The semiconductor device includes an inorganic substrate having a first side, a second side opposite to the first side, and a first lateral side extending between the first side and the second side. A metal layer is disposed on the first side and the first lateral side of the inorganic substrate. The first electrode is bonded to the metal layer.

[0004] According to one aspect of the present disclosure, a method for manufacturing multiple semiconductor devices includes: providing an inorganic substrate, the inorganic substrate including a first side and a second side opposite to the first side; forming a grid of grooves in the first side of the inorganic substrate, thereby defining a pattern of a base on the first side; forming a metal layer over the first side of the inorganic substrate, wherein the metal layer extends over the base and the sidewalls of the grooves; attaching the semiconductor substrate to the inorganic substrate by bonding the multiple first electrodes to the structured metal layer; thinning the semiconductor substrate to obtain a thinned semiconductor substrate; separating the thinned semiconductor substrate into a plurality of semiconductor chips; and separating the inorganic substrate into the plurality of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other, and / or can be selectively omitted if not described as necessarily required. Embodiments are depicted in the drawings and are exemplarily detailed in the following description.

[0006] Figure 1 is a schematic cross-sectional view of an exemplary semiconductor device including a semiconductor chip and an inorganic substrate.

[0007] Figure 2 is a schematic cross-sectional view of an exemplary semiconductor device including a semiconductor chip and an inorganic substrate, wherein the inorganic substrate includes a semiconductor substrate and an insulating layer covering the semiconductor substrate.

[0008] Figure 3A is a schematic cross-sectional view of an example of a semiconductor device having a first electrode and a second electrode disposed on the front side of a semiconductor chip, wherein a metal layer is structured to connect to both electrodes.

[0009] Figure 3B is a schematic cross-sectional view of an example of a semiconductor device having a first electrode and a second electrode disposed on the front side of a semiconductor chip, wherein a metal layer is structured to be connected to the first electrode and the second electrode is connected to a first type of vertical metal structure extending through an inorganic substrate.

[0010] Figure 3C is a schematic cross-sectional view of an example of a semiconductor device having a first electrode and a second electrode disposed on the front side of a semiconductor chip, wherein a metal layer is structured to be connected to the first electrode and the second electrode is connected to a second type of vertical metal structure extending through an inorganic substrate.

[0011] Figure 4 is a schematic cross-sectional view of an exemplary semiconductor device further including a device carrier.

[0012] Figure 5 is a perspective top view of an exemplary inorganic substrate having a grid of grooves in a first side of the inorganic substrate, thereby defining a pattern of pedestals.

[0013] Fig. 6A is a cross-sectional view of an example of a trench in a first side of an inorganic substrate.

[0014] Figure 6B is a cross-sectional view of another example of a trench in a first side of an inorganic substrate.

[0015] Figure 7 After forming a metal layer on the first side of the inorganic substrate Figure 5 A perspective top view of an exemplary inorganic substrate.

[0016] Fig. 8A yes Figure 7 An enlarged portion of the diagram showing how the metal layer is structured after Figure 7 The base viewed from one side.

[0017] Figure 8B yes Figure 7 An enlarged portion of the diagram showing how the metal layer is structured after Figure 7 The base viewed from the opposite side.

[0018] Fig. 9A is a cross-sectional view of an example of a metal layer in a trench of an inorganic substrate.

[0019] Fig. 9B is a cross-sectional view of another example of a metal layer in a trench of an inorganic substrate.

[0020] Fig.10 The diagram illustrates a stage in a process of manufacturing a semiconductor device before the semiconductor substrate is attached to an inorganic substrate.

[0021] Fig.11 Illustrated is a stage in a process of manufacturing a semiconductor device after a semiconductor substrate is attached to an inorganic substrate.

[0022] Fig.12 Diagram Fig.11 0014] A stage of a process is shown in which a semiconductor substrate exemplarily comprises a grid of pre-machined grooves filled with a polymer material.

[0023] Fig.13 After thinning the semiconductor substrate Fig.11 or 12 are the stages of the process shown.

[0024] Fig.14 The diagram shows a stage of a process for manufacturing a semiconductor device after a thinned semiconductor substrate is separated into a plurality of semiconductor chips by an etching process.

[0025] Fig.15 The diagram illustrates a stage of a process for manufacturing a semiconductor device after a thinned semiconductor substrate is separated into a plurality of semiconductor chips by a laser cutting process.

[0026] Fig.16 The diagram shows a stage in a process of manufacturing a semiconductor device after separating an inorganic substrate into a plurality of chip-substrate composite semiconductor devices.

[0027] Fig.17 is a schematic side view of an exemplary semiconductor device including a lead frame as a device carrier. DETAILED DESCRIPTION

[0028] As used in this specification, the term "electrically connected" or "connected" or similar terms are not intended to mean that elements are directly in contact together; intervening elements may be provided between the elements that are "electrically connected" or "connected", respectively. However, according to the present disclosure, the above and similar terms may optionally also have the specific meaning that elements are directly in contact together, that is, no intervening elements are provided between the elements that are "electrically connected" or "connected", respectively.

[0029] In addition, the words “on…” or “below…” in connection with a part, element, or material layer formed or located or arranged “on a surface” or “below a surface” may be used herein to mean that the part, element, or material layer is “directly” located (e.g., placed, formed, arranged, deposited, etc.) “on the implied surface” or “directly” located (e.g., placed, formed, arranged, deposited, etc.) “below the implied surface”, such as directly contacting the implied surface. However, the words “on…” or “below…” used in connection with a part, element, or material layer formed or located or arranged “on a surface” or “below a surface” may be used herein to mean that the part, element, or material layer is “indirectly” located (e.g., placed, formed, arranged, deposited, etc.) “on the implied surface” or “indirectly” located (e.g., placed, formed, arranged, deposited, etc.) “below the implied surface”, with one or more additional parts, elements, or layers arranged between the implied surface and the part, element, or material layer.

[0030] Figure 1 A schematic cross-sectional view of an exemplary semiconductor device 100 is shown. The semiconductor device 100 includes a semiconductor chip 110. The semiconductor chip 110 has a front side 110A and a back side 110B. A first electrode 130_1 is disposed on the front side 110A of the semiconductor chip 110.

[0031] In addition, the semiconductor device 100 includes an inorganic substrate 150. The inorganic substrate 150 includes a first side 150A, a second side 150B opposite to the first side 150A, and at least a first lateral side 150C_1. A metal layer 170 is disposed on the first side 150A and the first lateral side 150C_1 of the inorganic substrate 150.

[0032] The first electrode 130_1 of the semiconductor chip 110 is bonded to the metal layer 170. The inorganic substrate 150 may, for example, have a thickness T of at least 50 μm measured between the first side 150A and the second side 150B.

[0033] Therefore, the semiconductor device 100 is a semiconductor chip-inorganic substrate composite device. The inorganic substrate 150 provides mechanical stability to the semiconductor device 100, allowing the semiconductor device 100 to be handled during, for example, packaging and further processed.

[0034] In one example, the inorganic substrate 150 can be a glass substrate. In other examples, it may be possible to utilize an insulating layer (such as Figure 2 A semiconductor substrate (eg, a Si substrate) coated with MgO (as shown in FIG. 4 ) is used for the inorganic substrate 150 .

[0035] If the metal layer 170 is structured, the surface of the inorganic substrate 150 at the first side 150A and at the first lateral side 150C_1 may be electrically insulating in order to avoid any short circuits of the metal layer 170 (as will be explained further below). For example, the inorganic substrate 150 may include or be made of an electrically insulating material, or be coated with an electrically insulating material.

[0036] For example, the semiconductor chip 110 may have a (small) thickness equal to or less than 30 μm or 20 μm or 15 μm or 10 μm. In the art, semiconductor chips of such thickness are also referred to as ultra-thin chips or "one-digit chips" (if the thickness is below 10 μm). As will be further described in more detail below, it is also possible that, for example, the semiconductor chip 110 is formed by an epitaxial layer, which can be produced according to such a small thickness.

[0037] The semiconductor chip 110 may be, for example, a power chip. For example, the semiconductor chip 110 may be a power transistor chip or a power diode chip. In particular, a load voltage equal to or greater than, for example, 50V, 100V, 200V, 300V, 400V, 500V, 600V, 700V, 800V, 900V, or 1000V may be applied to the semiconductor chip 110.

[0038] The metal layer 170 may, for example, provide a high current flow.For example, the metal layer 170 may have a minimum thickness in a range between 5 and 100 μm, in particular, 20 and 50 μm.

[0039] If the semiconductor device 100 is a power semiconductor device, the first electrode 130_1 may, for example, be a load electrode of the power semiconductor device 100. However, as will be described further below, it is also possible to connect the metal layer 170 or a structured portion of the metal layer 170 to one or more electrodes of the semiconductor chip 110 which are not load electrodes but are, for example, control electrodes and / or sensing electrodes (Kelvin electrodes) or the like.

[0040] For example, if the semiconductor chip 110 includes an integrated power transistor, the semiconductor chip 110 may be configured to include one or more MISFETs (metal insulator semiconductor field effect transistors), MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), JFETs (junction gate field effect transistors), HEMTs (high electron mobility transistors), or bipolar transistors.

[0041] The semiconductor chip 110 may, for example, be made of any semiconductor material, such as Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc. In particular, Si or SiC power chips 110 are considered herein.

[0042] The semiconductor chip 110 is irreversibly attached to the inorganic substrate 150 by a bonding connection between the first electrode 130_1 of the semiconductor chip 110 and the metal layer 170 disposed over the first side 150A of the inorganic substrate 150. For example, the bonding connection may be a metal-to-metal direct bonding connection or a eutectic bonding connection.

[0043] For example, the first electrode 130_1 may include or have copper or a copper alloy, and the metal layer 170 may include or have copper or a copper alloy. In particular, a metal-to-metal direct bonding connection may be formed as a thermocompression bonding connection between these or other materials.

[0044] In other examples, the first electrode 130_1 and / or the metal layer 170 may have other metal materials. They may, for example, include or have Au or an Au-based alloy. In these and other cases, the bonding connection may, for example, be a eutectic bonding connection.

[0045] Figure 3A An example of a semiconductor device 100 is shown. The semiconductor device 100 is similar to Figure 1 The semiconductor device 100 is described below, and for the sake of brevity, reference is made to the above description. Figure 3A The semiconductor device 100 and Figure 1 The semiconductor device 100 of FIG. 1 is different in that the second electrode 130_2 is disposed on the front side 110A of the semiconductor chip 110 .

[0046] In addition, the metal layer 170 is structured to include a first continuous conductive path 170_1, which extends over the first side 150A, the first lateral side 150C_1, and the edge E1 between the first side 150A and the first lateral side 150C_1. The structured metal layer 170 may also include a second continuous conductive path 170_2, which extends over the first side 150A, the second lateral side 150C_2, and the edge E2 between the first side 150A and the second lateral side 150C_2. The second electrode 130_2 is bonded to the second continuous conductive path 170_2. In the same manner as described above for the bonding connection between the first electrode 130_1 and the metal layer 170, a bonding connection between the second electrode 130_2 and the second continuous conductive path 170_2 can be established.

[0047] As an example, Figure 3AAs further illustrated, the third electrode 130_3 of the semiconductor chip 110 may be disposed on the back side 110B of the semiconductor chip 110 .

[0048] For example, if the semiconductor chip 110 is a transistor chip, the first electrode 130_1 may be a control electrode (e.g., a gate electrode) or a sensing electrode, the second electrode 130_2 may be, for example, a source electrode or an emitter electrode, and the third electrode 130_3 may be, for example, a drain electrode or a collector electrode of the semiconductor chip 110. In other examples, when the semiconductor chip 110 is a horizontal device, all transistor electrodes as described above may be disposed on the front side 110A of the semiconductor chip 110.

[0049] In addition, the semiconductor chip 110 may, for example, be a device having a single electrode (e.g., a first electrode 130_1) on the front side 110A of the semiconductor chip 110 and a single electrode (e.g., a third electrode 130_3) on the back side 110B of the semiconductor chip 110. In this case, the semiconductor chip 110 may, for example, be a (power) diode. A semiconductor device including such a semiconductor chip 110 may be, for example, Figure 1 2, wherein in these figures, the electrode on the back side 110B of the semiconductor chip 110 (corresponding to Figure 3A The third electrode 130_3) is not depicted.

[0050] Furthermore, it is possible that the semiconductor chip 110 has a single electrode (corresponding to the first electrode 130_1) disposed on the front side 110A (eg Figure 1 and 2 ) and a plurality of electrodes ( Figure 1 and 2 not shown).

[0051] Figure 2 is a schematic cross-sectional view of an exemplary semiconductor device 100, which is similar to Figure 1 The semiconductor device 100 includes a semiconductor substrate 150_1 and an insulating layer 150_2 covering the semiconductor substrate 150_1, except that the inorganic substrate 150 includes a semiconductor substrate 150_1. The semiconductor substrate 150_1 may include silicon, for example, and the insulating layer 150_2 may be a hard passivation layer such as silicon oxide and / or silicon nitride.

[0052] Figure 3B and 3C Another example of the semiconductor device 100 is shown. Figure 3B , the inorganic substrate 150 may include a vertical metal structure extending through the inorganic substrate 150 from the first side 150A to the second side 150B. The second electrode 130_2 is bonded to the vertical metal structure.

[0053] exist Figure 3B In the embodiment, the vertical metal structure may include a plated metal pillar 370_1, or be formed by a plated metal pillar 370_1. To this end, a recess or a through hole may be formed in the inorganic substrate 150. The recess or the through hole may then be filled by plating with a suitable material (e.g., Cu). The lateral dimension (e.g., diameter) of each plated metal pillar 370_1 may be, for example, equal to or greater than or less than 10 μm, 15 μm, 20 μm, or 25 μm.

[0054] Reference Figure 3C , the vertical metal structure may be formed, for example, by a bulk metal inlay 370_2. The bulk metal inlay 370_2 may be formed by wet chemically etching a through hole in the inorganic substrate 150 and then filling the through hole with a suitable metal (e.g., Cu). The bulk metal inlay 370_2 may be: a single metal structure having a lateral dimension that may be similar to the lateral dimension of the second electrode 130_2. For example, the lateral dimension of the second electrode 130_2 may be, for example, equal to or greater than or less than 100 μm or 500 μm or 1 mm or 2 mm.

[0055] In all examples, the inorganic substrate 150 may have a thickness T, as described above with reference to Figure 1 described. Figure 3B The thickness T of the inorganic substrate 150 of the semiconductor device 100 shown in FIG. 1 may preferably be between 150 and 200 μm. On the other hand, for example, Figure 3C The thickness of the inorganic substrate 150 of the semiconductor device 100 may preferably be between 50 and 100 μm.

[0056] exist Figure 3B and 3C In the example shown in , the second electrode 130_2 (e.g., source electrode or emitter electrode) of the semiconductor chip 110 can be contacted via a contact extending through the inorganic substrate, while the first electrode 130_1 (e.g., gate contact) can be contacted via a continuous (first) conductive path 170_1 extending over a lateral side end surface (e.g., first lateral side 150C_1) of the inorganic substrate 150.

[0057] In all examples, the inorganic substrate 150 represents an irreversible (ie, permanent) base for supporting the fragile semiconductor chip 110 in order to provide the semiconductor device 100 with the required mechanical stability and robustness.

[0058] Figure 4 An example of a semiconductor device 400 is shown, and the semiconductor device 400 includes one of the semiconductor devices 100 described above and a device carrier 410 on which the semiconductor device 100 is mounted. Figure 4 The semiconductor device 100 mounted on the device carrier 410 is shown as being Figure 3A The semiconductor device 100 illustrated in FIG. 1 is a semiconductor device 100 , but all other examples of the semiconductor device 100 described above may be used.

[0059] The device carrier 410 may be any suitable carrier, for example, may include a lead frame or an application board or a ceramic-based carrier or a printed circuit board (PCB), etc. The bonding material 420 connects a portion of the metal layer 170 extending over the first lateral side 150C_1 and / or over the second lateral side 150C_2 (e.g., a portion of the first continuous conductive path 170_1 and / or a portion of the second continuous conductive path 170_2) with the device carrier 410 or an electrical conductor (not shown) provided by the device carrier 410. For example, the first continuous conductive path 170_1 may be connected to a first portion 410_1 of the device carrier 410 (e.g., a lead frame) by the bonding material 420, and the second continuous conductive path 170_2 may be connected to a second portion 410_2 of the device carrier 410 by the bonding material 420.

[0060] The bonding material 420 may be, for example, solder or a conductive adhesive (glue). In some examples, solder may be preferred because it automatically wets the contact surfaces of the device carrier 410 and the metal layer 170 during the process of mounting the semiconductor device 100 on the device carrier 410 .

[0061] In some of the examples, the lateral side (e.g., the first lateral side 150C_1 and / or the second lateral side 150C_2) may be inclined with respect to the second side 150B at an angle α of less than 90°, 80°, or 70°. The skewed geometry of the lateral sides of the inorganic substrate 150 may facilitate the mounting process. In addition, the structuring of the metal layer 170 at the lateral end faces (the first side 150A and / or the second side 150B) of the inorganic substrate 150 may be much easier.

[0062] Figures 5 to 16 Stages of an exemplary method of fabricating a plurality of semiconductor devices 100 are illustrated.

[0063] Reference Figure 5 , an inorganic substrate 550 is provided. The inorganic substrate 550 may be, for example, a wafer. The inorganic substrate 550 is a precursor of the inorganic substrate 150 described above, and may therefore have one of the materials mentioned above for the inorganic substrate 150 .

[0064] The inorganic substrate 550 has a first side 550A and a second side 550B opposite the first side 550A. A grid of grooves 520 is formed in the first side 550A of the inorganic substrate 550. By forming the grid of grooves 520, a pattern of pedestals is defined on the first side 550A of the inorganic substrate 550.

[0065] The grid of grooves 520 may, for example, be lattice-shaped. The grooves 520 may, for example, be cut (e.g., sawed) into an inorganic substrate 550 (e.g., a glass wafer or a silicon wafer coated by an insulating layer) in a mechanical manner. The size of the tile-shaped area on the first side 550A of the inorganic substrate 550 defined by the grid of grooves 520 may correspond to the size of the semiconductor chip 110, which is intended to be attached to the inorganic substrate 550.

[0066] The grooves 520 may vary in shape and / or depth. Fig. 6A and 6B , the groove 520 may have a depth d kerf and width W kerf . Depth d kerf can be selected so that the desired thickness TM of the inorganic substrate 150 (see Figure 1 ) can be implemented as will be described further below. Width W kerf It may be selected to allow metal deposition in a desired thickness TM of metal layer 170 and structuring of metal layer 170 within the trenches.

[0067] For example, the depth d kerf For example, the width W of the trench 520 may be in the range between 50 and 250 μm (particularly 100 and 200 μm). kerf The expected thickness TM of the metal layer 170 is larger, and the width W of the trench 520 is larger. kerf But the bigger it is.

[0068] The groove 520 may have a tapered shape in the downward direction. For example, the tapered shape may be circular ( Fig. 6A ) or sharp, such as V-shaped (e.g. Figure 6B ). Round shape ( Fig. 6A ) may, for example, be parabolic.

[0069] Reference Figure 7 The metal layer 570 is formed on the first side 550A of the inorganic substrate 550. The metal layer 570 extends over the top of the pedestal and the sidewalls 150C_1, 150C_2 of the trench 520.

[0070] Metallization of the inorganic substrate 550 may include depositing a single metal layer or a stack of metal layers on the first side 550A of the inorganic substrate 550. For example, the inorganic substrate 550 may be metallized by a first thin adhesive layer that adheres well to the material of the inorganic substrate 550 (e.g., glass or an insulating layer coating a silicon substrate). For example, the adhesive layer (not shown) may include or have Ti / Cu or Ag.

[0071] Subsequently, the formation of the metal layer 570 may include: metal plating (eg, galvanic plating) to a desired thickness TM. The thickness TM may depend on whether a load current (eg, source current) or a control or sensing signal will be conducted by the metal layer 570 ( Fig. 9A , 9B For example, the thickness TM may be in the range between 5 μm and 30 μm (particularly, between 8 μm and 20 μm).

[0072] For example, the metal layer 570 may be structured. The structuring may be performed by photolithography in the region above the pedestal and / or at the sidewalls of the trench 520. The sidewalls of the trench 520 correspond to the first and second lateral sides 150C_1 and 150C_2 of the inorganic substrate 150.

[0073] Reference Fig. 8A and 8B , the metal layer 570 may be structured to include a first continuous conductive path 170_1 extending over the first side 550A of the inorganic substrate 550 and over the sidewalls of the trench 520 (corresponding to the first lateral side 150C_1 of the inorganic substrate 150), and / or the metal layer 570 may be structured to include a second continuous conductive path 170_2 extending over the first side 550A of the inorganic substrate 550 and over the sidewalls of the trench 520 (corresponding to the second lateral side 150C_2 of the inorganic substrate 150). For example, the first continuous conductive path 170_1 may be connected to the gate G electrode (or more generally, the first electrode 130_1) of the semiconductor chip 110, and / or the second continuous conductive path 170_2 may be connected to the source (S) electrode (or more generally, the second electrode 130_2) of the semiconductor chip 110. First and second continuous conductive paths 170_1 and 170_2 are thus formed on opposite sidewalls of the trench 520 , as indicated by the arrows.

[0074] It has been found that by classical optical lithography, the in-groove structuring of the metal layer 570 can be implemented. A spray coater can be used to apply a photoresist on the first side 550A of the inorganic substrate 550. The structuring of the metal layer 570 on the top surface of the base and in the groove 520 can be implemented simultaneously. More specifically, the photoresist can be exposed on the top surface of the base and in the groove 520 at the same time. The focus of the optical lithography tool can be placed on the top surface of the base. Additional lithography steps, such as developing the photoresist (photoresist etching) can also be implemented simultaneously on the top surface of the base and in the groove 520.

[0075] Reference Fig.10 , a semiconductor substrate 1010 is provided. The semiconductor substrate 1010 includes a front side 1010A and a back side 1010B. A plurality of first electrodes 130_1 and (optionally) a plurality of second electrodes 130_2 are disposed on the front side 1010A of the semiconductor substrate 1010. The size of the semiconductor chip 110 to be cut from the semiconductor substrate 1010 is indicated by the line L. The inorganic substrate 550 and the semiconductor substrate 1010 are arranged relative to each other so that the line L is aligned with the bottom of the trench 520.

[0076] Reference Fig.11 The semiconductor substrate 1010 is then attached to the inorganic substrate 550 by bonding the plurality of first electrodes 130_1 and (optionally) the plurality of second electrodes 130_2 to the structured metal layer 570. The bonding may include metal-to-metal direct bonding, in particular, thermocompression bonding. In other examples, eutectic bonding may be used.

[0077] Thermocompression bonding involves heating and applying relatively high pressure to the semiconductor substrate 1010 and the inorganic substrate 550. As an electrode material and a metal layer material, copper is particularly suitable for direct metal-to-metal bonding. In addition, through direct metal-to-metal bonding, high planarity within the range of ±5 μm TTV (total thickness variation) can be obtained. Considering the following semiconductor substrate thinning process, high semiconductor substrate planarity may be important.

[0078] Fig.11 The thinning line TL is indicated. The semiconductor substrate 1010 is thinned from its back side down to the thinning line TL to obtain a thinned semiconductor substrate 1010T. The thinned semiconductor substrate 1010T may have a thickness TC of the semiconductor chip 110 .

[0079] In some examples, the semiconductor substrate 1010 may include an etch stop layer. The etch stop layer may be indicated by a thinning line TL. In other words, the etch stop layer may be arranged so that through the etching process, the semiconductor substrate (e.g., wafer) 1010 is thinned down to the thinning line TL, where the etching process stops at the etch stop layer.

[0080] The etch stop layer (at TL) allows to precisely set the desired thickness TC of the semiconductor chip 110, which is largely independent of the TTV of the inorganic substrate 550. Without the etch stop layer, the thickness TC of the semiconductor chip 110 would directly depend on the TTV of the inorganic substrate 550. For example, if the inorganic substrate 550 has a TTV of ±5 μm and the desired thickness TC of the semiconductor chip 110 is 10 μm, the thickness TC of the semiconductor chip 110 would vary at least between 5 μm and 15 μm during the thinning of the semiconductor substrate 110 by backside grinding. On the other hand, the etch stop layer allows to compensate for the TTV of the inorganic substrate 550, thus making the thinning process (more) independent of the TTV of the inorganic substrate 550.

[0081] For example, the semiconductor substrate 1010 may be a silicon-on-insulator (SOI) substrate. In this case, the etch stop layer may be provided by a buried oxide (BOX) layer in the SOI substrate 1010. The base silicon of the SOI substrate 1010 is thinned, and a thin top silicon layer above the BOX layer of a precisely defined thickness TC is used as the thinned semiconductor substrate 1010T.

[0082] In other examples, the thinned semiconductor substrate 1010T can be formed by an epitaxial layer deposited on a substrate suitable for epitaxial growth. For example, such a substrate can be a low-cost substrate that does not need to be made of silicon. This solution has the advantage that no expensive wafer material needs to be cut away. In addition, using the epitaxial layer, the thickness TC of the thinned semiconductor substrate 1010T can be controlled with high precision. In this way, for example, a semiconductor chip can be formed by a separate epitaxial layer.

[0083] Fig.12 Graphics Fig.11 A variation of the example. Fig.12 In the example of , the semiconductor substrate 1010 includes a pre-processed groove 1220 (groove) aligned with the line L. The pre-processed groove 1220 may be filled with a polymer material (e.g., an epoxy-based material). The pre-processed groove 1220 is formed in the front side 1010A of the semiconductor substrate 1010 and may have a depth equal to or greater than TC.

[0084] After thinning, the polymer material in the pre-machined groove 1220 is exposed on the back side of the thinned semiconductor substrate 1010T. The integrity of the thinned semiconductor substrate 1010T is maintained by the polymer material. If the pre-machined groove 1220 is not provided in the thinned semiconductor substrate 1010T, the integrity of the thinned semiconductor substrate 1010T is thus maintained by the substrate.

[0085] Subsequently, the thinned semiconductor substrate 1010T may be subjected to semiconductor processing. For example, one or more ion implantation processes may be performed on the backside surface of the thinned semiconductor substrate 1010T obtained by the thinning process. In particular, ion implantation may be used to produce a highly doped region adjacent to the backside surface obtained by thinning. In addition, a metal layer may be formed on the backside surface of the thinned semiconductor substrate 1010T. For example, the metal layer may then be structured to provide a third electrode 130_3.

[0086] Reference Fig.14 , the thinned semiconductor substrate 1010T is then separated into a plurality of semiconductor chips 110. For example, chip separation may be performed by laser cutting. In other examples, when the thinned semiconductor substrate 1010T is provided with a polymer-filled groove pattern, the thinned semiconductor substrate 1010T may be separated by etching the polymer material from the pre-machined groove 1220. For example, a plasma etching process (indicated by arrows) may be used.

[0087] Fig.15 The thinned semiconductor substrate 1010T is shown being separated by laser cutting. To this end, a laser beam 1510 is directed onto the thinned semiconductor substrate 1010T, aligned with the grid of trenches 520 in the inorganic substrate 550.

[0088] For example, after singulating the thinned semiconductor substrate 1010T into semiconductor chips 110, the inorganic substrate 550 may be separated to obtain a plurality of semiconductor devices 100 (ie, chip-substrate composite devices) (see Fig.16 ).to this end, Fig.14 The device shown in FIG. 15 may be turned over and placed on a temporary carrier (not shown). The inorganic substrate 550 may then be separated into a plurality of individual inorganic substrates 150 as described above. For example, the inorganic substrate 550 may be thinned until the metal layer 170 is separated at the bottom of the groove 520. Fig.16 This results in a separate semiconductor device 100 , as shown in , with continuous conductive paths 170_1 , 170_2 being connected to the chip electrodes 130_1 , 130_2 on opposite sides of the semiconductor chip 110 .

[0089] Fig.17An exemplary semiconductor device 1700 is shown, which includes a lead frame 1710 as a device carrier. In the example shown, the third electrode 130_3 can be a drain (D) electrode of the semiconductor chip 110. Similar to the device carrier 410, the lead frame 1710 can include: a first portion 1710_1, which is bonded to the first continuous conductive path 170_2; and a second portion 1710_2, which is bonded to the second continuous conductive path 170_2. In addition, the lead frame 1710 can include: a third portion 1710_3, which is connected to the third electrode 130_3 by, for example, a wire bonding connection 1720, a clip connection, or a ribbon connection.

[0090] Example

[0091] The following examples relate to further aspects of the present disclosure:

[0092] Example 1 is a semiconductor device, comprising: a semiconductor chip having a front side and a back side, wherein a first electrode is disposed on the front side of the semiconductor chip. The semiconductor device comprises an inorganic substrate having a first side, a second side opposite to the first side, and a first lateral side extending between the first side and the second side. A metal layer is disposed on the first side and the first lateral side of the inorganic substrate. The first electrode is bonded to the metal layer.

[0093] In Example 2, the subject matter of Example 1 can optionally further include: a device carrier, the inorganic substrate being mounted on the device carrier, with the second side facing the device carrier; and a bonding material configured to electrically connect a portion of the metal layer extending over the first lateral side to the device carrier or an electrical conductor provided by the device carrier.

[0094] In Example 3, the subject matter of Example 1 or 2 can optionally include, wherein the metal layer is structured to include a first continuous conductive path extending over the first side, the first lateral side, and an edge between the first side and the first lateral side.

[0095] In Example 4, the subject matter of Example 3 can optionally include, wherein a second electrode is disposed on the front side of the semiconductor chip; the inorganic substrate also includes a second lateral side extending between the first side and the second side; and the metal layer is structured to include a second continuous conductive path extending over the first side, the second lateral side, and an edge between the first side and the second lateral side, wherein the second electrode is bonded to the second continuous conductive path.

[0096] In Example 5, the subject matter of Example 3 can optionally include: a second electrode is disposed on the front side of the semiconductor chip; and the inorganic substrate includes a vertical metal structure extending through the inorganic substrate from the first side to the second side, and the second electrode is bonded to the vertical metal structure.

[0097] In Example 6, the subject matter of any of the preceding examples can optionally include, wherein the metal layer has a minimum thickness in the range between 5 and 100 μm, in particular has a minimum thickness in the range between 20 and 50 μm.

[0098] In Example 7, the subject matter of any of the preceding examples can optionally include, wherein the bonding connection between the first electrode and the metal layer is a metal-to-metal direct bonding connection, in particular, a thermocompression bonding connection or a eutectic bonding connection.

[0099] In Example 8, the subject matter of any of the preceding examples can optionally include, wherein the inorganic substrate is a glass substrate.

[0100] In Example 9, the subject matter of any of the preceding examples can optionally include, wherein the inorganic substrate is a semiconductor substrate coated with an insulating layer.

[0101] In Example 10, the subject matter of any of the preceding examples can optionally include, wherein the first lateral side is inclined with respect to the second side at an angle less than 90°.

[0102] In Example 11, the subject matter of any of the preceding examples can optionally include, wherein the inorganic substrate has a thickness of at least 50 μm measured between the first side and the second side.

[0103] In Example 12, the subject matter of any of the preceding examples can optionally include, wherein the semiconductor chip has a thickness equal to or less than 20 μm, or 15 μm, or 10 μm.

[0104] In Example 13, the subject matter of any of the preceding examples can optionally include, wherein the semiconductor chip is formed of an epitaxial layer.

[0105] In Example 14, the subject matter of any of the preceding examples can optionally include, wherein the semiconductor chip is a power chip.

[0106] Example 15 is a method for manufacturing multiple semiconductor devices, the method comprising: providing an inorganic substrate, the inorganic substrate comprising a first side and a second side opposite to the first side; forming a grid of grooves in the first side of the inorganic substrate, thereby defining a pattern of a base on the first side; forming a metal layer over the first side of the inorganic substrate, wherein the metal layer extends over the base and the sidewalls of the grooves; attaching the semiconductor substrate to the inorganic substrate by bonding the multiple first electrodes to the structured metal layer; thinning the semiconductor substrate to obtain a thinned semiconductor substrate; separating the thinned semiconductor substrate into a plurality of semiconductor chips; and separating the inorganic substrate into the plurality of semiconductor devices.

[0107] In Example 16, the subject matter of Example 15 can optionally include, wherein forming the metal layer includes performing metal plating to form the metal layer, the metal layer having a thickness in a range between 5 μm and 30 μm, in particular, having a thickness in a range between 8 μm and 20 μm.

[0108] In Example 17, the subject matter of Example 15 or 16 can optionally include structuring the metal layer by photolithography in a region above the pedestal and / or at sidewalls of the trench.

[0109] In Example 18, the subject matter of any one of Examples 15 to 17 can optionally include, wherein bonding the plurality of electrodes to the structured metal layer comprises metal-to-metal direct bonding, in particular, comprises thermocompression bonding or eutectic bonding.

[0110] In Example 19, the subject matter of any one of Examples 15 to 18 can optionally include, wherein thinning the semiconductor substrate includes obtaining a thinned semiconductor substrate having a thickness equal to or less than 20 μm, or 15 μm, or 10 μm.

[0111] In Example 20, the subject matter of Example 19 can optionally include, wherein thinning comprises etching the semiconductor substrate to the etch stop layer.

[0112] In Example 21, the subject matter of Example 19 or 20 can optionally include performing one or more ion implantation processes on the surface of the thinned semiconductor substrate obtained by thinning; and / or forming a structured metal layer over the surface of the thinned semiconductor substrate obtained by thinning.

[0113] In Example 22, the subject matter of any one of Examples 15 to 21 can optionally include, wherein separating the thinned semiconductor substrate into a plurality of semiconductor chips comprises: etching a polymer material from pre-machined grooves in the thinned semiconductor substrate; or laser cutting of the thinned semiconductor substrate.

[0114] In Example 23, the subject matter of any one of Examples 15 to 22 can optionally include, wherein separating the thinned semiconductor substrate into the plurality of semiconductor chips and separating the inorganic substrate into the plurality of semiconductor devices are performed sequentially and by different separation processes.

[0115] In Example 24, the subject matter of any one of Examples 15 to 23 can optionally include, wherein separating the inorganic substrate into the plurality of semiconductor devices comprises: thinning the inorganic substrate until the trench is reached.

[0116] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device comprising: a semiconductor chip comprising a front side and a back side, wherein a first electrode is disposed on the front side of the semiconductor chip; an inorganic substrate comprising a first side, a second side opposite the first side, and a first lateral side extending between the first side and the second side; a metal layer disposed on the first side and the first lateral side of the inorganic substrate; in The first electrode is bonded to the metal layer.

2. The semiconductor device according to claim 1, further comprising: a device carrier on which the inorganic substrate is mounted, with the second side facing the device carrier; and A bonding material is configured to electrically connect a portion of the metal layer extending over the first lateral side with the device carrier or an electrical conductor provided by the device carrier. 3 . The semiconductor device of claim 1 , wherein the metal layer is structured to include a continuous conductive path extending over the first side, the first lateral side, and an edge between the first side and the first lateral side.

4. The semiconductor device according to claim 3, wherein A second electrode is disposed on the front side of the semiconductor chip; The inorganic substrate further includes a second lateral side extending between the first side and the second side; and The metal layer is structured to include a second continuous conductive path extending over the first side, the second lateral side, and an edge between the first side and the second lateral side, wherein the second electrode is bonded to the second continuous conductive path.

5. The semiconductor device according to claim 3, wherein A second electrode is disposed on the front side of the semiconductor chip; and The inorganic substrate includes a vertical metal structure extending through the inorganic substrate from the first side to the second side, the second electrode being bonded to the vertical metal structure. 6 . The semiconductor arrangement as claimed in claim 1 , wherein the metal layer has a minimum thickness in the range between 5 and 100 μm, in particular in the range between 20 and 50 μm. 7 . The semiconductor device as claimed in claim 1 , wherein the bonding connection between the first electrode and the metal layer is a metal-to-metal direct bonding connection, in particular a thermocompression bonding connection or a eutectic bonding connection.

8. A semiconductor device as claimed in any preceding claim, wherein the inorganic substrate is a glass substrate.

9. The semiconductor device according to any one of claims 1 to 7, wherein the inorganic substrate is a semiconductor substrate coated with an insulating layer.

10. The semiconductor device of any of the preceding claims, wherein the first lateral side is inclined with respect to the second side at an angle of less than 90°.

11. The semiconductor device of any of the preceding claims, wherein the inorganic substrate has a thickness of at least 50 μm measured between the first side and the second side. 12 . The semiconductor device according to claim 1 , wherein the semiconductor chip has a thickness equal to or less than 20 μm or 15 μm or 10 μm.

13. A semiconductor device as claimed in any preceding claim, wherein the semiconductor chip is formed from epitaxial layers.

14. The semiconductor device as claimed in any one of the preceding claims, wherein the semiconductor chip is a power chip.

15. A method of manufacturing a plurality of semiconductor devices, the method comprising: providing a semiconductor substrate comprising a front side and a back side, wherein a plurality of first electrodes are disposed on the front side of the semiconductor substrate; providing an inorganic substrate comprising a first side and a second side opposite the first side; forming a grid of trenches in the first side of the inorganic substrate, thereby defining a pattern of pedestals on the first side; forming a metal layer over the first side of the inorganic substrate, wherein the metal layer extends over the pedestal and the sidewalls of the trench; attaching the semiconductor substrate to the inorganic substrate by bonding the plurality of first electrodes to the structured metal layer; thinning the semiconductor substrate to obtain a thinned semiconductor substrate; separating the thinned semiconductor substrate into a plurality of semiconductor chips; and The inorganic substrate is separated into the plurality of semiconductor devices. 16 . The method of claim 15 , wherein forming the metal layer comprises performing metal plating to form the metal layer, the metal layer having a thickness in a range between 5 μm and 30 μm, in particular, having a thickness in a range between 8 μm and 20 μm.

17. The method of claim 15 or 16, further comprising: The metal layer is structured by photolithography in the region above the pedestal and / or at the side walls of the trenches. 18 . The method of claim 15 , wherein bonding the plurality of electrodes to the structured metal layer comprises metal-to-metal direct bonding, in particular, thermocompression bonding or eutectic bonding.

19. The method of any one of claims 15 to 18, wherein thinning the semiconductor substrate comprises obtaining a thinned semiconductor substrate having a thickness equal to or less than 20 μm, or 15 μm, or 10 μm.

20. The method of claim 19, wherein the semiconductor substrate comprises an etch stop layer, wherein thinning comprises etching the semiconductor substrate to the etch stop layer.

21. The method of claim 19 or 20, further comprising: performing one or more ion implantation processes on the surface of the thinned semiconductor substrate obtained by thinning; and / or A structured metal layer is formed on the surface of the thinned semiconductor substrate obtained by thinning.

22. The method of any one of claims 15 to 21, wherein separating the thinned semiconductor substrate into a plurality of semiconductor chips comprises: Etching polymer material from pre-machined grooves in a thinned semiconductor substrate, or Laser cutting of thinned semiconductor substrates.

23. The method according to any one of claims 15 to 22, wherein separating the thinned semiconductor substrate into the plurality of semiconductor chips and separating the inorganic substrate into the plurality of semiconductor devices are performed sequentially and by different separation processes.

24. The method of any one of claims 15 to 23, wherein separating the inorganic substrate into the plurality of semiconductor devices comprises: The inorganic substrate is thinned until the trench is reached.

Images