Overcurrent protection circuit for eliminating input imbalance

Abstract

The invention belongs to the technical field of power management, and particularly relates to an overcurrent protection circuit for eliminating input imbalance. The circuit comprises an SW sampling module, a reference voltage generation module, a level shift module, an operational amplifier module, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate and a capacitor, and through multiplexing an operational amplifier circuit, the operational amplifier circuit alternately works between an operational amplifier mode and a comparator mode under the control of a clock; and the input offset voltage is calibrated in real time, so that the over-current detection precision and reliability are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of power management, and in particular relates to an overcurrent protection circuit for eliminating input offset. Background Art

[0002] Overcurrent protection is an important part of circuit design. It is used to monitor and protect the load in the circuit from excessive current damage and improve the reliability and stability of the circuit. Overcurrent may be caused by a variety of reasons, such as short circuit, excessive load or component failure. Traditional overcurrent protection methods include the use of current limiting resistors, fuses and electronic fuses. However, each of these methods has its limitations. For example, current limiting resistors will introduce additional power consumption and voltage drop under normal operating conditions, and although fuses and electronic fuses can provide protection in overcurrent conditions, they usually need to be manually reset or replaced and cannot achieve automatic recovery function.

[0003] As electronic devices become more complex and require more reliability, it is important to design an efficient, fast-responding, and automatically recoverable overcurrent protection circuit. Modern overcurrent protection circuits typically use intelligent monitoring and control technology to protect circuits by detecting current values ​​in real time and responding quickly to overcurrent conditions. For example, an overcurrent detection circuit composed of an operational amplifier or a comparator can accurately monitor current changes and quickly trigger a protection mechanism, such as cutting off power or limiting current, when the current exceeds a set threshold.

[0004] However, many existing overcurrent protection circuits are inadequate in dealing with input offset voltage. Input offset voltage is a voltage shift caused by manufacturing process differences and environmental changes, which will affect the accuracy of the detection circuit and cause the overcurrent limit to deviate from the ideal value. Therefore, eliminating the impact of input offset voltage on overcurrent protection circuits and improving their detection accuracy and response speed have become an important direction of current technological development. Summary of the invention

[0005] The purpose of the present invention is to solve the above problem and propose an overcurrent protection circuit that eliminates input offset voltage. Figure 1 The self-calibration technology shown in the figure, through multiplexing the operational amplifier circuit, makes it work alternately between the operational amplifier and comparator modes under clock control, and calibrates the input offset voltage in real time, thereby improving the accuracy and reliability of over-current detection.

[0006] The technical solution of the present invention:

[0007] An overcurrent protection circuit for eliminating input offset is used for overcurrent detection of NLDMOS power tubes in a half-bridge structure, comprising a SW sampling module, a reference voltage generation module, a level shift module, an operational amplifier module, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate and a capacitor;

[0008] The SW sampling module is used to sample the switch node voltage in the half-bridge structure, and the obtained sampled voltage is used as the input of the first transmission gate;

[0009] The reference voltage generating module is used to convert the reference current into a reference voltage, and the reference voltage is used as an input of the second transmission gate;

[0010] The output of the first transmission gate and the output of the second transmission gate are used as inputs of the level shift module, and the level shift module shifts the input voltage and then outputs it to the in-phase terminal of the operational amplifier module;

[0011] The output of the operational amplifier module is connected to the inputs of the third transmission gate and the fourth transmission gate, the output of the third transmission gate is connected to the inverting input terminal of the operational amplifier and one end of the capacitor, the other end of the capacitor is grounded, and the output of the fourth transmission gate is the output of the overcurrent protection circuit;

[0012] The switch node voltage is a square wave signal, the highest level is approximately the power supply signal VDD_H of the power tube, which is a high voltage signal, the lowest level is approximately the reference ground signal GND, and the duty cycle is 50%; the SW sampling module includes a first NMOS tube and a first bias current source I b1 , where the first NMOS tube is an NLDMOS tube, the drain is connected to the switch node voltage, and the gate voltage V G is the gate voltage of the lower power tube in the half-bridge structure, and the source is connected to the first bias current source I b1 and the input of the first transmission gate, the first bias current source I b1 Providing a bias current to the first NMOS tube;

[0013] The reference voltage generation module includes a second NMOS tube and a second bias current source I REF , wherein the second NMOS tube is an NLDMOS tube, and the drain is connected to the second bias current source I REF The gate of the second transmission gate is connected to a fixed 5V voltage and the source is grounded; the second bias current source I REF Provide over-current reference current signal;

[0014] The first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate are controlled by a clock signal CLK, the CLK signal has the same frequency as the switch node voltage, the highest level is the power supply signal VDD_5V, the lowest level is the reference ground signal GND, and the duty cycle is 50%; when the CLK signal is at a high level, it is defined as During the period, the first transmission gate and the third transmission gate are turned on, and the second transmission gate and the fourth transmission gate are turned off; when the CLK signal is at a low level, it is defined as During the period, the second transmission gate and the fourth transmission gate are turned on, and the first transmission gate and the third transmission gate are turned off.

[0015] Furthermore, the level shift module includes a third bias current I b3 , a first resistor R1, and a seventh PMOS tube; the gate of the seventh PMOS tube is connected to the input signal of the level shift module, the third bias current is connected to the source of the seventh PMOS tube and serves as the output end of the level shift module, and the first resistor is connected to the drain of the seventh PMOS tube.

[0016] Further, the operational amplifier module includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube; wherein the first PMOS tube and the second PMOS tube are input pairs of tubes, the gates of which are connected to the input signal of the operational amplifier module, the gates of the third PMOS tube and the fourth PMOS tube are both connected to the drain of the fifth PMOS tube, and the source is connected to VDD to form a current mirror; the gates of the fifth PMOS tube and the sixth PMOS tube are both connected to the third bias voltage and work as common-source common-gate tubes; the gates of the third NMOS tube and the fourth NMOS tube are both connected to the first bias voltage, and the source is connected to GND to form a bias current; the gates of the fifth NMOS tube and the sixth NMOS tube are both connected to the second bias voltage and work as common-source common-gate tubes; the drain of the sixth NMOS tube is connected to the drain of the sixth PMOS as the module output end.

[0017] The output signal of the operational amplifier passes through the fourth transmission gate and is connected to the first Schmitt trigger and the first inverter in succession. The output of the inverter is connected to V OUT The signal is the output signal of the overcurrent protection circuit. The power supply signals of the first Schmitt trigger and the first inverter are both VDD_5V, and the ground signals are both GND.

[0018] The beneficial effects of the present invention are as follows: the overcurrent protection circuit for eliminating input offset described in the present invention realizes more accurate overcurrent protection detection and improves the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a block diagram of the overall architecture of the present invention.

[0020] Figure 2 The present invention provides a circuit diagram of an overcurrent protection circuit for eliminating input offset voltage.

[0021] Figure 3 For the present invention Schematic diagram of the circuit for period operation.

[0022] Figure 4 For the present invention Schematic diagram of the circuit for period operation.

[0023] Figure 5 The present invention provides a simulation waveform diagram of the overcurrent protection circuit. DETAILED DESCRIPTION

[0024] The present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 The overall framework structure of the overcurrent protection circuit proposed by the present invention that can eliminate input offset voltage is demonstrated, including a SW sampling module, a reference voltage generation module, a level shift module, an operational amplifier module, a transmission gate, and a capacitor. Figure 2 The specific circuit diagram of the overcurrent protection circuit that can eliminate the input offset voltage proposed by the present invention, wherein VDD_5V is the power supply voltage, GND is the reference low voltage, SW is the square wave signal of the switch node, CLK is the clock signal with the same frequency as SW, CLK~ is the inverted signal of CLK, V G I is the gate voltage control signal of the power tube under the half bridge; REF is the reference current, I b1 ,I b2 ,I b3 A fixed bias current signal provided to the outside world; V b1 、V b2 、V b3 The voltage signal provided by the outside world, V OUT It is an output signal to indicate whether an overcurrent occurs. OUT A high level indicates an overcurrent has occurred.

[0026] The main circuit of overcurrent protection is as follows, V G When it is high level, the first NLDMOS tube is turned on and enters the linear region, and the drain voltage is approximately equal to the source voltage, so V sense The voltage is approximately the SW voltage. The gate voltage of the second NLDMOS tube is always 5V, which is always in the on state and in the linear region, and can be equivalent to a resistor R dson_N2 , the current acts on the equivalent resistance to obtain the reference voltage:

[0027] V REF =I REF ×R dson_N2

[0028] V REF Voltage and V sense The voltage is connected to the gate of the seventh PMOS transistor MP7 through the first transmission gate TG1 and the second transmission gate TG2. MP7 works in the saturation region to realize the level shift function. Its bias current is I b3 For a fixed current, according to the relationship between the PMOS tube current and the gate-source voltage

[0029]

[0030] It can be obtained that the gate-source voltage V of MP7 SG7 is a fixed value, that is, for the level shift circuit, the output signal is a fixed level higher than the input signal, which is named V rise .

[0031] The output signal of the level shift module is connected to the in-phase terminal of the operational amplifier. The inverting terminal signal of the comparator is V-signal, which is determined by the conduction of the third transmission gate TG3 and the fourth transmission gate TG4 controlled by CLK. The first PMOS tube MP1 and the second PMOS tube MP2 are the input signals of the tubes. The source of the two PMOS tubes is connected together to ensure that the source voltage is the same. Therefore, the difference in source-drain current of MP1 and MP2 is completely determined by the in-phase and inverting input signals. The gates of MN3 and MN4 are connected to V b1 , providing a fixed current bias, MP3 and MP4 form a current mirror to convert the dual-ended input signal into a single-ended output signal, and the drains of MP1 and MP2 are connected to the source of MN5 and MN6 respectively, forming a folded CASCODE structure.

[0032] Ideally, the operational amplifier satisfies the virtual-off property, and the voltages at the positive and negative input terminals are exactly the same. However, in actual operation, due to problems such as device mismatch, there is an offset voltage between the input voltages, which affects the comparison accuracy. The present invention eliminates this offset voltage by multiplexing the operational amplifier, and the connection relationship of the operational amplifier can be changed by changing the conduction of the transmission gate. The first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are all controlled by the CLK signal. When the CLK signal is at a high level, the first transmission gate TG1 and the third transmission gate TG3 are turned on, and the second transmission gate TG2 and the fourth transmission gate TG4 are turned off. The circuit structure diagram at this time is as shown in FIG. Figure 3 As shown, the operational amplifier with input offset is equivalent to an ideal amplifier without input offset and offset voltage V OS , V OS The effect of connecting to the non-inverting input terminal and the inverting input terminal is the same. Here, it is assumed that it is connected to the non-inverting input terminal. Figure 3 In, V REF The voltage is sent to the input of the level shifter, so the voltage at point A is V A =V REF +V rise , the voltage at the inverting terminal of the ideal op amp is V + =V REF +V rise +V OS , because TG3 is turned on, the operational amplifier is connected into a unity gain negative feedback structure, and the input voltage of the ideal operational amplifier is the same, that is, V - =V+ =V REF +V rise +V OS , so the capacitor voltage at this time is V B =V-=V REF +V rise +V OS .

[0033] For the folded CASCODE structure of the PMOS tube input, the tube input voltage value can be lower than the minimum power supply voltage, that is, the GND voltage. The sampled SW voltage and reference voltage are slightly higher than the GND voltage, about tens of millivolts, which can theoretically achieve normal operation of the operational amplifier input. During this period, the output of the op amp is connected to the inverting input. When the input is clamped, the voltage at the output is only a few tens of millivolts, which is not enough to make MN4 and MN6 at the output work in the saturation region. The two NMOS tubes will enter the linear region, the gain will be significantly reduced, and the offset will increase further. REF or V sense When the voltage changes, the degree to which MN4 and MN6 enter the linear region will also be different, causing the offset voltage to change, and the input offset voltage cannot be reasonably eliminated. However, if there is a level shift structure, V rise When set at 1.5V, the voltage at the in-phase input terminal is maintained at around 1.5V. When connected as a unit gain negative feedback, MN4 and MN6 at the output terminal can operate in the saturation region, and the input offset voltage is a constant value and can be eliminated.

[0034] When the CLK signal is at a low level, the second transmission gate TG2 and the fourth transmission gate TG4 are turned on, and the first transmission gate TG1 and the third transmission gate TG3 are turned off. Figure 4 As shown, the operational amplifier with input offset is equivalent to an ideal amplifier without input offset and offset voltage V OS , the capacitor voltage is V B =V REF +V rise +V OS At this time, the input voltage is the SW signal, and the voltage at point A is V A =V sense +V rise , the voltage at the inverting terminal of the ideal op amp is V + =V sense +V rise +V OS , because TG4 is turned on, the operational amplifier is an open-loop circuit at this time, and the signal difference at the input end is large, the operational amplifier is used as a comparator, and the difference between the two signals at the comparator input end is V + -V - =(Vsense +V rise +V OS )-(V REF +V rise +V OS )=V sense -V REF , which is equivalent to comparing the SW voltage with V REF Voltage, the input offset voltage V inside the op amp OS be offset.

[0035] The SW voltage is generated by the load current flowing through the lower power tube of the half-bridge. Assume that the resistance of the lower power tube is R ds , the load current is I LOAD , then the voltage of SW when the lower power tube is turned on is:

[0036] V SW_L =I LOAD ×R ds

[0037] Therefore, comparing the SW voltage with V REF The voltage is actually comparing I LOAD ×R ds with I REF ×R dson_N2 After the circuit design is completed, R ds With R dson_N2 are all constant values, so it is equivalent to comparing I LOAD with I REF The relationship between the overcurrent protection and the imbalance is eliminated.

[0038] Figure 5 The simulation waveform diagram of the overcurrent protection circuit proposed in the present invention is shown. It can be seen that under the same current parameters, the accuracy of the overcurrent protection is significantly improved compared with the case where the offset is not eliminated.

Claims

1. An overcurrent protection circuit for eliminating input offset, used for overcurrent detection of NLDMOS power tube in a half-bridge structure, characterized in that: It includes a SW sampling module, a reference voltage generating module, a level shifting module, an operational amplifier module, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate and a capacitor; The SW sampling module is used to sample the switch node voltage in the half-bridge structure, and the obtained sampled voltage is used as the input of the first transmission gate; The reference voltage generating module is used to convert the reference current into a reference voltage, and the reference voltage is used as an input of the second transmission gate; The output of the first transmission gate and the output of the second transmission gate are used as inputs of the level shift module, and the level shift module shifts the input voltage and then outputs it to the in-phase terminal of the operational amplifier module; The output of the operational amplifier module is connected to the inputs of the third transmission gate and the fourth transmission gate, the output of the third transmission gate is connected to the inverting input terminal of the operational amplifier and one end of the capacitor, the other end of the capacitor is grounded, and the output of the fourth transmission gate is the output of the overcurrent protection circuit; The switch node voltage is a square wave signal, the highest level is approximately the power supply signal VDD_H of the power tube, which is a high voltage signal, the lowest level is approximately the reference ground signal GND, and the duty cycle is 50%; the SW sampling module includes a first NMOS tube and a first bias current source I b1 , where the first NMOS tube is an NLDMOS tube, the drain is connected to the switch node voltage, and the gate voltage V G is the gate voltage of the lower power tube in the half-bridge structure, and the source is connected to the first bias current source I b1 and the input of the first transmission gate, the first bias current source I b1 Providing a bias current to the first NMOS tube; The reference voltage generation module includes a second NMOS tube and a second bias current source I REF , wherein the second NMOS tube is an NLDMOS tube, and the drain is connected to the second bias current source I REF The gate of the second transmission gate is connected to a fixed 5V voltage and the source is grounded; the second bias current source I REF Provide over-current reference current signal; The first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate are controlled by a clock signal CLK, the CLK signal has the same frequency as the switch node voltage, the highest level is the power supply signal VDD_5V, the lowest level is the reference ground signal GND, and the duty cycle is 50%; when the CLK signal is at a high level, which is defined as a φ1 period, the first transmission gate and the third transmission gate are turned on, and the second transmission gate and the fourth transmission gate are turned off; When the CLK signal is at a low level, which is defined as a φ2 period, the second transmission gate and the fourth transmission gate are turned on, and the first transmission gate and the third transmission gate are turned off.

2. The overcurrent protection circuit for eliminating input offset according to claim 1, characterized in that: The level shift module includes a third bias current I b3 , a first resistor R1, and a seventh PMOS tube; The gate of the seventh PMOS tube is connected to the input signal of the level shift module, the third bias current is connected to the source of the seventh PMOS tube and serves as the output end of the level shift module, and the first resistor is connected to the drain of the seventh PMOS tube.

3. The overcurrent protection circuit for eliminating input offset according to claim 1, characterized in that: The operational amplifier module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube; wherein the first PMOS tube and the second PMOS tube are input pair tubes, the gates of which are connected to the input signal of the operational amplifier module, the gates of the third PMOS tube and the fourth PMOS tube are both connected to the drain of the fifth PMOS tube, and the source is connected to VDD to form a current mirror; the gates of the fifth PMOS tube and the sixth PMOS tube are both connected to the third bias voltage, and work as common source and common gate tubes; The gates of the third NMOS tube and the fourth NMOS tube are both connected to the first bias voltage, and the source is connected to GND to form a bias current; the gates of the fifth NMOS tube and the sixth NMOS tube are both connected to the second bias voltage, and work as common-source and common-gate tubes; the drain of the sixth NMOS tube is connected to the drain of the sixth PMOS as the module output end.

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