Pulse elimination modulation method and system for SiC device five-level split inverter

Abstract

The present invention belongs to the field of power electronics technology, and the present invention relates to a pulse rejection modulation method and system for a SiC device five-level split inverter, two groups of reverse stacked carriers are generated according to a set reference signal, two different carrier signals are generated according to the two groups of reverse stacked carriers and the size of the set modulation wave, two auxiliary modulation waves are generated according to the actual voltage of the suspended capacitor and the expected lower limit threshold and the expected upper limit threshold, a low-frequency drive signal is generated according to the size of the set modulation wave, and a high-frequency drive signal for each phase is generated according to the size of the output current of each phase, the auxiliary modulation wave and the carrier signal. Only half of the fundamental wave cycle is a high-frequency drive signal, and the other half of the cycle is a low-frequency drive signal, which effectively reduces the loss of the drive circuit, and there is no need to add dead time between the high-frequency drive signals, so as to avoid the dead zone effect from the source, reduce the current output harmonics, reduce the current distortion, and improve the output current quality; the voltage balance of the suspended capacitor is maintained by the regulation of the auxiliary modulation wave.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and relates to inverter modulation technology, and in particular to a pulse elimination modulation method and system for a SiC device five-level split inverter. Background Art

[0002] In the field of renewable energy generation, multi-level inverters have been widely used due to their advantages of multiple output voltage levels, low voltage stress, and high efficiency, especially in photovoltaic and wind power generation systems. Compared with traditional two-level and three-level inverters, five-level inverters can provide higher quality output voltage, and therefore have significant application prospects in medium-high voltage and high-power applications.

[0003] In recent years, the development of silicon carbide metal oxide semiconductor field effect transistors (hereinafter referred to as: SiC MOSFET) has brought more possibilities to inverter technology. Compared with traditional silicon (Si) material power switching devices, SiC MOSFET has higher voltage resistance, lower on-resistance and faster switching speed, which can significantly improve the switching frequency and overall performance of the inverter. However, this high switching speed also causes a series of new problems. The high switching speed will cause the complementary on-off SiCMOSFETs in the same bridge arm to affect each other, which can easily lead to a direct short circuit, thereby increasing the risk of inverter operation and affecting the reliability of the inverter.

[0004] The high switching frequency characteristics of SiC MOSFET significantly increase the drive loss of the inverter, and at the same time, the dead time to avoid the inverter's direct short circuit will produce a dead time effect. Although high-speed SiC MOSFET can shorten the dead time, the dead time effect intensifies with the increase of switching frequency, especially at high switching frequency, the dead time effect is particularly serious, greatly increasing the distortion rate of the output current and reducing the quality of the output current.

[0005] For the five-level inverter, the complexity of its topology may also introduce the problem of floating capacitors. During the long-term operation of the inverter, the voltage of the floating capacitor may gradually increase or decrease due to imbalance, thus threatening the operating stability of the inverter. Therefore, how to achieve effective balance of the floating capacitor voltage is also one of the technical problems that need to be solved urgently for the stable operation of the five-level inverter.

[0006] In summary, the five-level inverter still has many technical difficulties in terms of high reliability, low output current harmonics and suspended capacitor voltage balance. It is necessary to propose practical solutions to these problems in order to further improve its application performance and reliability in new energy power generation systems. Summary of the invention

[0007] In view of the above-mentioned problems in the prior art such as large driving loss, high output current harmonics, and voltage imbalance, the present invention provides a pulse elimination modulation method and system for a five-level split inverter of a SiC device, in which a high-frequency driving signal is used only in half of the fundamental wave cycle and a low-frequency driving signal is used in the other half of the cycle, thereby effectively reducing the loss of the driving circuit, eliminating the dead zone effect, reducing the output current harmonics, reducing current distortion, improving the output current quality, and maintaining the voltage balance of the suspended capacitor.

[0008] In a first aspect, the present invention provides a pulse elimination modulation method for a five-level split inverter of a SiC device, the specific steps of which are as follows:

[0009] The step of generating two groups of reverse stacked carrier waves is as follows: generating two groups of reverse stacked carrier waves according to a set reference signal, wherein the first group of reverse stacked carrier waves includes a first forward stacked carrier wave and a first reverse stacked carrier wave, and the second group of reverse stacked carrier waves includes a second forward stacked carrier wave and a second reverse stacked carrier wave;

[0010] Carrier generation step: generating a first carrier signal according to the size of the set modulation wave, a first forward stacked carrier, and a first reverse stacked carrier, and generating a second carrier signal according to the size of the set modulation wave, a second forward stacked carrier, and a second reverse stacked carrier;

[0011] Auxiliary modulation wave generation step: according to the size of the actual voltage of the suspension capacitor and the expected lower limit threshold, the modulation wave is set to generate a first auxiliary modulation wave, and according to the size of the actual voltage of the suspension capacitor and the expected upper limit threshold, the modulation wave is set to generate a second auxiliary modulation wave;

[0012] The driving signal generating step is as follows: a low-frequency driving signal is generated according to the size of the set modulation wave; a first signal is generated according to the size of the first auxiliary modulation wave and the first carrier signal, a second signal is generated according to the size of the second auxiliary modulation wave and the second carrier signal, and a k-phase high-frequency driving signal is generated according to the size of the k-phase output current, the first signal, and the second signal, where k=A, B, C.

[0013] In some embodiments, in the dual-group reverse stacked carrier generation step, the first forward stacked carrier is a set reference signal, the second forward stacked carrier is obtained by subtracting the set reference signal from 1, the first reverse stacked carrier is obtained by inverting the set reference signal, and the second reverse stacked carrier is obtained by subtracting 1 from the set reference signal.

[0014] In some embodiments, in the carrier generation step, the method of generating the first carrier signal according to the size of the set modulation wave, the first forward stacked carrier, and the first reverse stacked carrier is: when the modulation wave is set ≥0, the first carrier signal is the first forward stacked carrier; when the modulation wave is set <0, the first carrier signal is the first reverse stacked carrier.

[0015] In some embodiments, in the carrier generation step, the method of generating the second carrier signal according to the size of the set modulation wave, the second forward stacked carrier, and the second reverse stacked carrier is: when the modulation wave is set ≥0, the second carrier signal is the second forward stacked carrier; when the modulation wave is set <0, the second carrier signal is the second reverse stacked carrier.

[0016] In some embodiments, in the auxiliary modulation wave generation step, the method of generating the first auxiliary modulation wave according to the size of the actual voltage of the suspended capacitor and the expected lower limit threshold and the set modulation wave is: when the actual voltage of the suspended capacitor ≥ the expected lower limit threshold, the first auxiliary modulation wave is the set modulation wave; when the actual voltage of the suspended capacitor < the expected lower limit threshold, the first auxiliary modulation wave is 1.2 times the set modulation wave.

[0017] In some embodiments, in the auxiliary modulation wave generation step, the method of generating the second auxiliary modulation wave according to the size of the actual voltage of the suspension capacitor and the expected upper limit threshold and the set modulation wave is: when the actual voltage of the suspension capacitor ≥ the expected upper limit threshold, the second auxiliary modulation wave is 1.2 times the set modulation wave; when the actual voltage of the suspension capacitor < the expected upper limit threshold, the second auxiliary modulation wave is the set modulation wave.

[0018] In some embodiments, in the drive signal generating step, the method of generating a low-frequency drive signal according to the size of the set modulation wave is: when the modulation wave is set ≥0, the drive signal PWM1 is equal to 1, which is a high level, the drive signal PWM2 is equal to 0, which is a low level, the drive signal PWM3 is equal to 1, which is a high level, and the drive signal PWM4 is equal to 0, which is a low level; when the modulation wave is set <0, the drive signal PWM1 is equal to 0, which is a low level, the drive signal PWM2 is equal to 1, which is a high level, the drive signal PWM3 is equal to 0, which is a low level, and the drive signal PWM4 is equal to 1, which is a high level.

[0019] In some embodiments, in the step of generating the driving signal, the method of generating the first signal according to the magnitude of the first auxiliary modulation wave and the first carrier signal is: when the first auxiliary modulation wave ≥ the first carrier signal, the first signal is 1; when the first auxiliary modulation wave < the first carrier signal, the first signal is 0;

[0020] The method of generating the second signal according to the magnitude of the second auxiliary modulation wave and the second carrier signal is: when the second auxiliary modulation wave ≥ the second carrier signal, the second signal is 1; when the second auxiliary modulation wave < the second carrier signal, the second signal is 0;

[0021] The method for generating a high-frequency drive signal according to the magnitude of the k-phase output current, the first signal, and the second signal is as follows: when the k-phase output current ≥0, the drive signal PWMk5 is the first signal, the drive signal PWMk6 is 0, the drive signal PWMk7 is the second signal, and the drive signal PWMk8 is 0; when the k-phase output current <0, the drive signal PWMk5 is 0, the drive signal PWMk6 is the inverted signal of the first signal, the drive signal PWMk7 is 0, and the drive signal PWMk8 is the inverted signal of the second signal.

[0022] In a second aspect, the present invention provides a SiC device five-level split inverter pulse elimination modulation system, which is used to implement the SiC device five-level split inverter pulse elimination modulation method described in the first aspect of the present invention, including:

[0023] A setting module, used to set the reference signal and modulation wave;

[0024] A detection device, used to detect the three-phase output current of the SiC device five-level split inverter and the actual voltage of the suspended capacitor;

[0025] A dual-group reverse stacked carrier generation module generates two groups of reverse stacked carriers according to a set reference signal;

[0026] A carrier generation module generates a first carrier signal according to the size of the set modulation wave, a first forward stacked carrier, and a first reverse stacked carrier, and generates a second carrier signal according to the size of the set modulation wave, a second forward stacked carrier, and a second reverse stacked carrier;

[0027] The auxiliary modulation wave generating module generates a first auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected lower threshold value and sets the modulation wave, and generates a second auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected upper threshold value and sets the modulation wave;

[0028] A low-frequency driving signal generating module generates a low-frequency driving signal according to the size of the set modulation wave;

[0029] The high-frequency drive signal generating module generates a first signal according to the magnitude of the first auxiliary modulation wave and the first carrier signal, generates a second signal according to the magnitude of the second auxiliary modulation wave and the second carrier signal, and generates a k-phase high-frequency drive signal according to the magnitude of the k-phase output current, the first signal, and the second signal.

[0030] In some embodiments, the high-frequency driving signal generating module includes:

[0031] Comparison module I: when the first auxiliary modulation wave is ≥ the first carrier signal, the first signal output is 1; when the first auxiliary modulation wave is < the first carrier signal, the first signal output is 0;

[0032] Comparison module II, when the second auxiliary modulation wave ≥ the second carrier signal, outputs the second signal as 1; when the second auxiliary modulation wave < the second carrier signal, outputs the second signal as 0;

[0033] Select module I, when the k-phase output current is ≥0, the output drive signal PWMk5 is the first signal; when the k-phase output current is <0, the output drive signal PWMk5 is 0;

[0034] Select module II, when the k-phase output current is ≥0, the output drive signal PWMk6 is 0; when the k-phase output current is <0, the output drive signal PWMk6 is the inverted signal of the first signal;

[0035] Select module III, when the k-phase output current is ≥0, the output drive signal PWMk7 is the second signal; when the k-phase output current is <0, the output drive signal PWMk7 is 0;

[0036] Select module IV, when the k-phase output current is ≥0, the output drive signal PWMk8 is 0; when the k-phase output current is <0, the output drive signal PWMk8 is the inverted signal of the second signal.

[0037] Compared with the prior art, the advantages and positive effects of the present invention are:

[0038] (1) The pulse elimination modulation method and system for the SiC device five-level split inverter provided by the present invention uses a high-frequency driving signal only in half of the fundamental wave cycle and a low-frequency driving signal in the other half of the cycle, which effectively reduces the loss of the driving circuit. There is no need to add dead time between the high-frequency driving signals, which can avoid the dead time effect from the source, reduce the current output harmonics, reduce current distortion, and improve the output current quality.

[0039] (2) The pulse elimination modulation method and system for the SiC device five-level split inverter provided by the present invention maintain the voltage of the floating capacitor balanced by the regulation of the auxiliary modulation wave. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A circuit diagram of a five-level split inverter of a ripple bus SiC device according to an embodiment of the present invention;

[0041] Figure 2 This is a flow chart of a pulse elimination modulation method for a five-level split inverter of a SiC device according to an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of the generation of dual sets of reverse stacked carriers according to an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of carrier generation according to an embodiment of the present invention;

[0044] Figure 5 A schematic diagram of the auxiliary modulation wave generation according to an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of the generation of a low-frequency driving signal according to an embodiment of the present invention;

[0046] Figure 7 A schematic diagram of the high-frequency driving signal generation according to an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the generation of the A-phase high-frequency driving signal according to an embodiment of the present invention;

[0048] Fig. 9 A schematic diagram of the A-phase driving signal waveform with a dead time of 4μs in the traditional modulation method;

[0049] Fig.10 A schematic diagram of a phase A driving signal waveform of a pulse elimination modulation method for a five-level split inverter of a SiC device according to an embodiment of the present invention;

[0050] Fig.11 This is a structural block diagram of a pulse elimination modulation system for a SiC device five-level split inverter according to an embodiment of the present invention;

[0051] Fig.12 The first auxiliary modulation wave m is a pulse elimination modulation method and system for a SiC device five-level split inverter according to an embodiment of the present invention. a1 Waveform diagram;

[0052] Fig.13 The second auxiliary modulation wave m is a pulse elimination modulation method and system for a SiC device five-level split inverter according to an embodiment of the present invention. a2 Waveform diagram

[0053] Fig.14 This is a schematic diagram of the three-phase output current waveform with a dead time of 4μs using the traditional modulation method;

[0054] Fig.15 The figure is a schematic diagram of three-phase output current waveforms of a pulse elimination modulation method and system for a five-level split inverter of a SiC device according to an embodiment of the present invention.

[0055] In the figure, 1. setting module, 2. detection device, 3. double-group reverse stacked carrier generation module, 4. carrier generation module, 5. auxiliary modulation wave generation module, 6. low-frequency drive signal generation module, 7. high-frequency drive signal generation module, 8. superimposed pulse. DETAILED DESCRIPTION

[0056] The present invention will be described in detail below by way of exemplary embodiments in conjunction with the accompanying drawings. However, it should be understood that, without further description, elements, structures and features in one embodiment may also be beneficially combined in other embodiments.

[0057] Figure 1 The main topology circuit of the SiC device five-level split inverter is shown in FIG. dc is a DC voltage source, C1 and C2 are DC bus capacitors, C3 is a floating capacitor, Q a1 To Q a8 A is the SiC MOSFET power switch device, D a1 , D a2 For the A-phase SiC Schottky diode, L a1 , L a2 I is the isolation inductance of phase A; A 、i B 、i C is the three-phase output current; L a , L b , L c is the three-phase load inductance, R a , R b , R c is the three-phase load resistance. It should be noted that the topological circuit structure of the three-phase ABC is exactly the same. Figure 1 Only the topological circuit structure of phase A is given, and the topological circuit structures of phases B and C are the same as the topological circuit structure of phase A.

[0058] Continue to see Figure 1 Since the ABC three-phase bridge arms are completely symmetrical, we will take phase A as an example to explain the connection method of the main circuit. dc Provide the overall voltage for the DC bus, the DC bus is connected in series with the DC bus capacitor C1 and the DC bus capacitor C2 from top to bottom; the DC bus capacitor C1 and the DC bus capacitor C2 are connected to the O1 point; the power switch device Q a1 One end is connected to the DC bus positive electrode P, and the other end is connected to the power switch device Q a2 One end and the power switch device Q a5 One end is connected to X a1 point, power switch device Q a2 The other end is connected to the power switch device Q a3 , DC bus capacitor C1, DC bus capacitor C2 are connected to point O1, power switch device Q a5 The other end is connected to the suspension capacitor C3 and the power switch device Q a7 One end, diode D a1 Connect to X a2 Point; Power switch device Q a7 The other end is connected to the diode Da2 , Isolation inductor L a2 Connect to X a3 Point; diode D a1 The other end is connected to the isolation inductor L a1 , power switch device Q a8 Connect to X a4 Point; C3 and diode D a2 , power switch device Q a8 , power switch device Q a6 Connect to X a5 Point; Isolation inductor L a1 One end and diode D a1 , power switch device Q a8 Connect to X a4 point, and the other end is connected to the isolation inductor L a2 Connect to X a7 Point; Power switch device Q a3 and power switch device Q a6 The other end is connected to X a6 Click, and click X a6 By connecting the power switch device Q a4 Connected to the negative pole N of the DC bus; point X a7 Through the load inductance L a , load resistance R a Connect to the load neutral point O2. The connection method of the B-phase and C-phase main circuits is the same as that of the A-phase, and will not be repeated here.

[0059] For the above-mentioned fluctuating bus SiC device five-level split inverter, the present invention provides a SiC device five-level split inverter pulse rejection modulation method and system, which generates two groups of reverse stacked carriers according to the set reference signal, generates two different carrier signals according to the two groups of reverse stacked carriers and the size of the set modulation wave, generates two auxiliary modulation waves according to the actual voltage of the suspended capacitor and the expected lower limit threshold and the expected upper limit threshold, generates a low-frequency drive signal according to the size of the set modulation wave, and generates a high-frequency drive signal for each phase according to the size of the output current of each phase, the auxiliary modulation wave and the carrier signal. The high-frequency drive signal is only in half of the fundamental wave cycle, and the low-frequency drive signal is in the other half of the cycle, which effectively reduces the loss of the drive circuit. There is no need to add dead time between the signals in the high-frequency drive signal, which can avoid the dead zone effect from the source, reduce the current output harmonics, reduce current distortion, and improve the output current quality. The voltage of the suspended capacitor is kept balanced by the regulation of the auxiliary modulation wave.

[0060] The pulse elimination modulation method and system of the SiC device five-level split inverter of the present invention are described in detail below in conjunction with the accompanying drawings and embodiments.

[0061] See also Figure 2The first aspect of the present invention provides a pulse elimination modulation method for a five-level split inverter of a SiC device, and the specific steps are as follows:

[0062] S1, double set of reverse stacked carrier generation steps: see Figure 3 According to the set reference signal U0, two groups of reverse stacked carriers are generated. The first group of reverse stacked carriers includes a first forward stacked carrier U1 and a first reverse stacked carrier U3, and the second group of reverse stacked carriers includes a second forward stacked carrier U2 and a second reverse stacked carrier U4.

[0063] Specifically, see Figure 3 The first forward stacked carrier U1 is the set reference signal U0, the second forward stacked carrier U2 is obtained by subtracting the set reference signal U0 from 1, the first reverse stacked carrier U3 is obtained by inverting the set reference signal U0, and the second reverse stacked carrier U4 is obtained by subtracting 1 from the set reference signal U0.

[0064] Specifically, in some embodiments, the reference signal U0 is set to an isosceles triangle wave with an amplitude of 1. The frequency of the reference signal U0 is set to but limited to 10 kHz, which can be set specifically according to actual conditions.

[0065] S2, carrier generation step: see Figure 4 , according to the size of the set modulation wave SINA, the first positive stacked carrier U1, and the first reverse stacked carrier U3, the first carrier signal U is generated. cc1 The second carrier signal U is generated according to the size of the set modulation wave SINA, the second forward stacked carrier U2, and the second reverse stacked carrier U4. cc2 .

[0066] Specifically, in some embodiments, continue to see Figure 4 , according to the size of the set modulation wave SINA, the first positive stacked carrier U1, and the first reverse stacked carrier U3, the first carrier signal U is generated. cc1 The method is: when the modulation wave SINA≥0, the first carrier signal U cc1 is the first positive stacked carrier U1; when the modulation wave SINA is set to <0, the first carrier signal U cc1 It is the first reverse stacked carrier U3.

[0067] Specifically, in some embodiments, continue to see Figure 4 The second carrier signal U is generated according to the size of the set modulation wave SINA, the second forward stacked carrier U2, and the second reverse stacked carrier U4. cc2 The method is: when the modulation wave SINA ≥ 0, the second carrier signal U cc2 is the second positive stacked carrier U2; when the modulation wave SINA is set to <0, the second carrier signal Ucc2 It is the second reverse stacked carrier U4.

[0068] It should be noted that in the above carrier signal generation method, the first carrier signal U cc1 and the second carrier signal U cc2 The amplitude changes with the modulation wave SINA. When the modulation wave SINA≥0, the magnitude of the two carrier signals is between 0 and 1. When the modulation wave SINA<0, the magnitude of the two carrier signals is between -1 and 0.

[0069] S3, auxiliary modulation wave generation steps: see Figure 5 , according to the actual voltage U of the suspension capacitor c3 The size of the desired lower limit threshold and the modulation wave SINA are set to generate the first auxiliary modulation wave m a1 , according to the actual voltage U of the suspension capacitor c3 The size of the desired upper threshold value and the setting modulation wave SINA generate the second auxiliary modulation wave m a2 .

[0070] Specifically, in some embodiments, continue to see Figure 5 , according to the actual voltage U of the suspension capacitor c3 The size of the desired lower limit threshold and the modulation wave SINA are set to generate the first auxiliary modulation wave m a1 The method is: the actual voltage of the suspended capacitor U c3 ≥ expected lower limit threshold, the first auxiliary modulation wave m a1 To set the modulation wave SINA; the actual voltage of the floating capacitor U c3 < expected lower limit threshold, the first auxiliary modulation wave m a1 Set the modulation wave SINA to 1.2 times.

[0071] Specifically, in some embodiments, continue to see Figure 5 , according to the actual voltage U of the suspension capacitor c3 The size of the desired upper threshold value and the setting modulation wave SINA generate the second auxiliary modulation wave m a2 The method is: the actual voltage of the suspended capacitor U c3 ≥ expected upper threshold, the second auxiliary modulation wave m a2 The actual voltage of the floating capacitor is 1.2 times of the set modulation wave SINA. c3 < expected upper limit threshold, the second auxiliary modulation wave m a2 To set the modulation wave SINA.

[0072] It should be noted that the expected lower threshold and the expected upper threshold can be set according to actual needs. For example, the expected lower threshold is 199.3, and the expected upper threshold is 200.7.

[0073] Two auxiliary modulation waves are generated by comparing the actual value of the suspension capacitor voltage with the expected lower threshold and the expected upper threshold respectively. The waveforms of the two auxiliary modulation waves fluctuate in amplitude at a specific moment, generating a superimposed pulse 8, which can balance the voltage of the suspension capacitor.

[0074] S4, drive signal generating step: generate a low-frequency drive signal according to the size of the set modulation wave; generate a first signal according to the size of the first auxiliary modulation wave and the first carrier signal, generate a second signal according to the size of the second auxiliary modulation wave and the second carrier signal, and generate a k-phase high-frequency drive signal according to the size of the k-phase output current, the first signal, and the second signal, k=A, B, C.

[0075] Specifically, in some embodiments, see Figure 6 , the method for generating a low-frequency driving signal according to the size of the modulation wave SINA is: when the modulation wave SINA is set to be greater than or equal to 0, the driving signal PWM1 is equal to 1, which is a high level, the driving signal PWM2 is equal to 0, which is a low level, the driving signal PWM3 is equal to 1, which is a high level, and the driving signal PWM4 is equal to 0, which is a low level; when the modulation wave SINA is set to be less than 0, the driving signal PWM1 is equal to 0, which is a low level, the driving signal PWM2 is equal to 1, which is a high level, the driving signal PWM3 is equal to 0, which is a low level, and the driving signal PWM4 is equal to 1, which is a high level.

[0076] Specifically, in some embodiments, see Figure 7 , according to the first auxiliary modulation wave m a1 With the first carrier signal U cc1 The method of generating the first signal SQ1 is as follows: the first auxiliary modulation wave m a1 ≥First carrier signal U cc1 When the first signal SQ1 is 1, the first auxiliary modulation wave m a1 The first carrier signal U cc1 , the first signal SQ1 is 0.

[0077] Specifically, in some embodiments, continue to see Figure 7 , according to the second auxiliary modulation wave m a2 With the second carrier signal U cc2 The method of generating the second signal SQ2 is as follows: the second auxiliary modulation wave m a2 ≥The second carrier signal U cc2 When the second signal SQ2 is 1, the second auxiliary modulation wave m a2 The second carrier signal U cc2 When , the second signal SQ2 is 0;

[0078] Specifically, in some embodiments, continue to see Figure 7The method of generating a high-frequency driving signal according to the magnitude of the k-phase output current, the first signal SQ1, and the second signal SQ2 is as follows: the k-phase output current i k ≥0, the drive signal PWMk5 is the first signal SQ1, the drive signal PWMk6 is 0, the drive signal PWMk7 is the second signal SQ2, and the drive signal PWMk8 is 0; the k-phase output current i k <0, the driving signal PWMk5 is 0, the driving signal PWMk6 is the inverted signal of the first signal SQ1, the driving signal PWMk7 is 0, and the driving signal PWMk8 is the inverted signal of the second signal SQ2.

[0079] exist Figure 4 The carrier generation link shown, Figure 5 The auxiliary modulation wave generation link and Figure 7 In the high-frequency pulse generation link shown in the figure, the signal is judged and selected by selecting the switch Switch (abbreviated as SW switch). The SW switch is divided into an input side and an output side. The input side has three signal input terminals, the upper terminal and the lower terminal are signal input terminals, the middle terminal is a comparison signal input terminal, and the output side has only one signal output terminal. When the signal received by the middle terminal is greater than 0, the output terminal outputs the signal received by the upper terminal; when the comparison signal received by the middle terminal is less than 0, the output terminal outputs the signal received by the lower terminal.

[0080] It should be noted that, since the A-phase modulation, the B-phase modulation, and the C-phase modulation are the same, the modulation principle of the above method is described below using the A-phase modulation as an example.

[0081] It should be noted that in the A-phase regulation, B-phase modulation, and C-phase regulation, the double-group reverse stacked carrier generation link, carrier generation link, auxiliary modulation wave generation link, and low-frequency drive signal generation link are the same as the steps in the above method and will not be repeated here.

[0082] See also Figure 8 In the A-phase high-frequency drive signal generation link, the process of generating the A-phase high-frequency drive signals PWMA5, PWMA6, PWMA7, and PWMA8 is as follows:

[0083] The first signal SQ1 is the first auxiliary modulation wave m a1 With the first carrier signal U cc1 The value obtained by performing a logical operation of “≥” is the first auxiliary modulation wave m a1 ≥First carrier signal U cc1 When the first signal SQ1 is 1, the first auxiliary modulation wave m a1 The first carrier signal U cc1 , the first signal SQ1 is 0.

[0084] The second signal SQ2 is the second auxiliary modulation wave m a2 With the second carrier signal U cc2 The value obtained by performing a logical operation of "≥" is the second auxiliary modulation wave m a2 ≥The second carrier signal U cc2 When the second signal SQ2 is 1, the second auxiliary modulation wave m a2 The second carrier signal U cc2 , the second signal SQ2 is 0.

[0085] A phase output current i A ≥0, the drive signal PWMA5 is the first signal SQ1, the drive signal PWMA6 is 0, the drive signal PWMA7 is the second signal SQ2, and the drive signal PWMA8 is 0; the A phase output current i A <0, the driving signal PWMA5 is 0, the driving signal PWMA6 is the inverted signal of the first signal SQ1, the driving signal PWMA7 is 0, and the driving signal PWMA8 is the inverted signal of the second signal SQ2.

[0086] The above specifically introduces the generation process of the A-phase high-frequency drive signals PWMA5, PWMA6, PWMA7, and PWMA8. The generation method of the high-frequency drive signals of the B-phase and the C-phase is the same, which will not be repeated here.

[0087] In order to more intuitively demonstrate the basic principle of the pulse elimination modulation method of the SiC device five-level split inverter, Fig. 9 The A-phase drive signal waveform with a dead time of 4μs in the traditional modulation method is shown. Fig.10 The A-phase drive signal waveform of the pulse elimination modulation method of the SiC device five-level split inverter proposed in the present invention is demonstrated. Fig. 9 and Fig.10 Middle,U A is the output voltage of phase A, compared with Fig. 9 and Fig.10 It can be seen that the low-frequency drive signals PWM1 to PWM4 of the modulation method proposed in the present invention are exactly the same as those of the traditional modulation method, but the high-frequency drive signals PWMA5 to PWMA8 are quite different. In the traditional modulation method, the drive signals PWMA5 to PWMA8 are high-frequency drive signals in the entire fundamental wave cycle; while in the modulation method proposed in the present invention, the drive signals PWMA5 to PWMA8 are high-frequency drive signals only in half of the fundamental wave cycle, and the other half of the cycle is a low-frequency drive signal. When the output current i of phase A is A ≥0, the drive signals PWMA5 and PWMA7 are high-frequency drive signals, and the drive signals PWMA6 and PWMA8 are low-frequency drive signals; when the A-phase output current i A<0, the drive signals PWMA5 and PWMA7 are low-frequency drive signals, and the drive signals PWMA6 and PWMA8 are high-frequency drive signals. Therefore, compared with the traditional modulation method, the modulation method of the present invention reduces the loss of the drive circuit. In addition, there is no need to add dead time between the drive signals PWMA5 and PWMA6, and between the drive signals PWMA7 and PWMA8, which can avoid the dead time effect from the source and improve the output current quality.

[0088] See also Fig.11 The second aspect of the present invention provides a SiC device five-level split inverter pulse elimination modulation system, which is used to implement the SiC device five-level split inverter pulse elimination modulation method described in the first aspect of the present invention, including:

[0089] Setting module 1, used for setting reference signal and modulation wave;

[0090] Detection device 2, used to detect the three-phase output current of the SiC device five-level split inverter and the actual voltage of the floating capacitor;

[0091] A dual-group reverse stacked carrier generation module 3 generates two groups of reverse stacked carriers according to a set reference signal;

[0092] The carrier generation module 4 generates a first carrier signal according to the size of the set modulation wave, the first forward stacked carrier, and the first reverse stacked carrier, and generates a second carrier signal according to the size of the set modulation wave, the second forward stacked carrier, and the second reverse stacked carrier;

[0093] Auxiliary modulation wave generating module 5, generates a first auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected lower threshold value, and generates a second auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected upper threshold value;

[0094] A low-frequency driving signal generating module 6 generates a low-frequency driving signal according to the size of the set modulation wave;

[0095] The high-frequency driving signal generating module 7 generates a first signal according to the size of the first auxiliary modulation wave and the first carrier signal, generates a second signal according to the size of the second auxiliary modulation wave and the second carrier signal, and generates a k-phase high-frequency driving signal according to the size of the k-phase output current, the first signal, and the second signal.

[0096] In some embodiments, the high-frequency driving signal generating module includes:

[0097] Comparison module I: when the first auxiliary modulation wave is ≥ the first carrier signal, the first signal output is 1; when the first auxiliary modulation wave is < the first carrier signal, the first signal output is 0;

[0098] Comparison module II, when the second auxiliary modulation wave ≥ the second carrier signal, outputs the second signal as 1; when the second auxiliary modulation wave < the second carrier signal, outputs the second signal as 0;

[0099] Select module I, when the k-phase output current is ≥0, the output drive signal PWMk5 is the first signal; when the k-phase output current is <0, the output drive signal PWMk5 is 0;

[0100] Select module II, when the k-phase output current is ≥0, the output drive signal PWMk6 is 0; when the k-phase output current is <0, the output drive signal PWMk6 is the inverted signal of the first signal;

[0101] Select module III, when the k-phase output current is ≥0, the output drive signal PWMk7 is the second signal; when the k-phase output current is <0, the output drive signal PWMk7 is 0;

[0102] Select module IV, when the k-phase output current is ≥0, the output drive signal PWMk8 is 0; when the k-phase output current is <0, the output drive signal PWMk8 is the inverted signal of the second signal.

[0103] Specifically, in some embodiments, the selection module I, the selection module II, the selection module III, and the selection module IV select the selection switch Switch (abbreviated as: SW switch) for comparison and judgment. The SW switch is divided into an input side and an output side. The input side has three signal input terminals, the upper terminal and the lower terminal are signal input terminals, the middle terminal is a comparison signal input terminal, and the output side has only one signal output terminal. When the signal received by the middle terminal is greater than 0, the output terminal outputs the signal received by the upper terminal; when the comparison signal received by the middle terminal is less than 0, the output terminal outputs the signal received by the lower terminal.

[0104] Specifically, in some embodiments, the setting module includes a first signal generator for generating a setting reference signal according to a preset value and a second signal generator for generating a setting modulation wave according to the preset value.

[0105] Specifically, in some embodiments, the reference signal is set to be an isosceles triangle wave, and the first signal generator is a triangle wave generator. The modulation wave is set to be a sine wave, and the second signal generator is a sine wave generator.

[0106] Specifically, in some embodiments, the detection device includes a current sensor and a voltage sensor, the current sensor is used to detect the three-phase output current of the SiC device five-level split inverter, and the voltage sensor is used to detect the actual voltage of the floating capacitor in the SiC device five-level split inverter.

[0107] In order to verify the effectiveness of the pulse removal modulation method and system of the SiC device five-level split inverter of the present invention, a simulation model was built using SIMULINK for verification. dc The reference signal U0 has an isosceles triangle wave frequency of 10kHz, a modulation wave SINA frequency of 50Hz, busbar DC capacitors C1 and C2 of 4.7mF, and a suspension capacitor C3 of 1mF. In the simulation model, the conventional modulation method and the SiC device five-level split inverter pulse elimination modulation method and system proposed in the present invention are respectively used for the SiC device isolated output inverter. Fig.12 and Fig.13 The auxiliary modulation wave m output by the auxiliary modulation wave generation module in the method proposed by the present invention is shown respectively. a1 and m a2 Waveform. It can be seen that compared with the ideal sine wave, the auxiliary modulation wave m a1 and auxiliary modulation wave m a2 The waveform of has an amplitude fluctuation at a specific moment, generating a superimposed pulse 8, which can balance the voltage of the suspension capacitor C3 to about 200V. Fig.14 The three-phase output current waveform with a dead time of 4μs using the traditional modulation method is given. Through Fourier analysis, it can be seen that the total harmonic distortion rates THD of the three-phase currents A, B, and C are 3.77%, 3.78%, and 3.77% respectively. Fig.15 The three-phase current waveform of the pulse removal modulation method and system of the SiC device five-level split inverter proposed by the present invention is given. Through Fourier analysis, it can be seen that the total harmonic distortion rate THD of the three-phase currents A, B, and C is 3.45%. Fig.14 and Fig.15 , which can effectively illustrate that the present invention can improve the output current quality, effectively eliminate the dead zone effect, and reduce the output current harmonic distortion.

[0108] The above embodiments are used to explain the present invention rather than to limit the present invention. Any modification and change made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A pulse elimination modulation method for a five-level split inverter of a SiC device, characterized in that: The specific steps are: The step of generating two groups of reverse stacked carriers is as follows: two groups of reverse stacked carriers are generated according to a set reference signal, wherein the first group of reverse stacked carriers includes a first forward stacked carrier and a first reverse stacked carrier, and the second group of reverse stacked carriers includes a second forward stacked carrier and a second reverse stacked carrier; the first forward stacked carrier is the set reference signal, the second forward stacked carrier is obtained by subtracting the set reference signal from 1, the first reverse stacked carrier is obtained by inverting the set reference signal, and the second reverse stacked carrier is obtained by subtracting 1 from the set reference signal; Carrier generation step: generating a first carrier signal according to the size of the set modulation wave, a first forward stacked carrier, and a first reverse stacked carrier, and generating a second carrier signal according to the size of the set modulation wave, a second forward stacked carrier, and a second reverse stacked carrier; The method for generating the first carrier signal according to the size of the set modulation wave, the first forward stacked carrier, and the first reverse stacked carrier is: when the set modulation wave is ≥0, the first carrier signal is the first forward stacked carrier; when the set modulation wave is <0, the first carrier signal is the first reverse stacked carrier; The method of generating the second carrier signal according to the size of the set modulation wave, the second forward stacked carrier, and the second reverse stacked carrier is: when the set modulation wave is ≥0, the second carrier signal is the second forward stacked carrier; when the set modulation wave is <0, the second carrier signal is the second reverse stacked carrier; Auxiliary modulation wave generation step: according to the size of the actual voltage of the suspension capacitor and the expected lower limit threshold, the modulation wave is set to generate a first auxiliary modulation wave, and according to the size of the actual voltage of the suspension capacitor and the expected upper limit threshold, the modulation wave is set to generate a second auxiliary modulation wave; The method of generating the first auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected lower limit threshold and the set modulation wave is as follows: when the actual voltage of the suspension capacitor is ≥ the expected lower limit threshold, the first auxiliary modulation wave is the set modulation wave; when the actual voltage of the suspension capacitor is < the expected lower limit threshold, the first auxiliary modulation wave is 1.2 times the set modulation wave; The method of generating the second auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected upper limit threshold and the set modulation wave is as follows: when the actual voltage of the suspension capacitor is ≥ the expected upper limit threshold, the second auxiliary modulation wave is 1.2 times the set modulation wave; when the actual voltage of the suspension capacitor is < the expected upper limit threshold, the second auxiliary modulation wave is the set modulation wave; The driving signal generating step is as follows: generating a low-frequency driving signal according to the size of the set modulation wave; generating a first signal according to the size of the first auxiliary modulation wave and the first carrier signal, generating a second signal according to the size of the second auxiliary modulation wave and the second carrier signal, and generating a k-phase high-frequency driving signal according to the size of the k-phase output current, the first signal, and the second signal, where k=A, B, C; The method of generating a low-frequency drive signal according to the size of the set modulation wave is: when the modulation wave is set ≥ 0, the drive signal PWM1 is equal to 1, which is a high level, the drive signal PWM2 is equal to 0, which is a low level, the drive signal PWM3 is equal to 1, which is a high level, and the drive signal PWM4 is equal to 0, which is a low level; when the modulation wave is set < 0, the drive signal PWM1 is equal to 0, which is a low level, the drive signal PWM2 is equal to 1, which is a high level, the drive signal PWM3 is equal to 0, which is a low level, and the drive signal PWM4 is equal to 1, which is a high level. The method of generating the first signal according to the magnitude of the first auxiliary modulation wave and the first carrier signal is: when the first auxiliary modulation wave ≥ the first carrier signal, the first signal is 1; when the first auxiliary modulation wave < the first carrier signal, the first signal is 0; The method of generating the second signal according to the magnitude of the second auxiliary modulation wave and the second carrier signal is: when the second auxiliary modulation wave ≥ the second carrier signal, the second signal is 1; when the second auxiliary modulation wave < the second carrier signal, the second signal is 0; The method for generating a high-frequency drive signal according to the magnitude of the k-phase output current, the first signal, and the second signal is as follows: when the k-phase output current ≥0, the drive signal PWMk5 is the first signal, the drive signal PWMk6 is 0, the drive signal PWMk7 is the second signal, and the drive signal PWMk8 is 0; when the k-phase output current <0, the drive signal PWMk5 is 0, the drive signal PWMk6 is the inverted signal of the first signal, the drive signal PWMk7 is 0, and the drive signal PWMk8 is the inverted signal of the second signal.

2. A SiC device five-level split inverter pulse elimination modulation system, used to implement the SiC device five-level split inverter pulse elimination modulation method as claimed in claim 1, characterized in that: include: A setting module, used to set a reference signal; A detection device, used to detect the three-phase output current of the SiC device five-level split inverter and the actual voltage of the suspended capacitor; A dual-group reverse stacked carrier generation module generates two groups of reverse stacked carriers according to a set reference signal; A carrier generation module generates a first carrier signal according to the size of the set modulation wave, a first forward stacked carrier, and a first reverse stacked carrier, and generates a second carrier signal according to the size of the set modulation wave, a second forward stacked carrier, and a second reverse stacked carrier; The auxiliary modulation wave generating module generates a first auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected lower threshold value and sets the modulation wave, and generates a second auxiliary modulation wave according to the magnitude of the actual voltage of the suspension capacitor and the expected upper threshold value and sets the modulation wave; A low-frequency driving signal generating module generates a low-frequency driving signal according to the size of the set modulation wave; The high-frequency drive signal generating module generates a first signal according to the magnitude of the first auxiliary modulation wave and the first carrier signal, generates a second signal according to the magnitude of the second auxiliary modulation wave and the second carrier signal, and generates a k-phase high-frequency drive signal according to the magnitude of the k-phase output current, the first signal, and the second signal.

3. The SiC device five-level split inverter pulse elimination modulation system according to claim 2, characterized in that: The high-frequency driving signal generating module comprises: Comparison module I: when the first auxiliary modulation wave is ≥ the first carrier signal, the first signal output is 1; when the first auxiliary modulation wave is < the first carrier signal, the first signal output is 0; Comparison module II, when the second auxiliary modulation wave ≥ the second carrier signal, outputs the second signal as 1; when the second auxiliary modulation wave < the second carrier signal, outputs the second signal as 0; Select module I, when the k-phase output current is ≥0, the output drive signal PWMk5 is the first signal; when the k-phase output current is <0, the output drive signal PWMk5 is 0; Select module II, when the k-phase output current is ≥0, the output drive signal PWMk6 is 0; when the k-phase output current is <0, the output drive signal PWMk6 is the inverted signal of the first signal; Select module III, when the k-phase output current is ≥0, the output drive signal PWMk7 is the second signal; when the k-phase output current is <0, the output drive signal PWMk7 is 0; Select module IV, when the k-phase output current is ≥0, the output drive signal PWMk8 is 0; when the k-phase output current is <0, the output drive signal PWMk8 is the inverted signal of the second signal.

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