Negative single event transient hardening circuit and method based on comparator and compensation tube

Abstract

The application provides a negative single event transient reinforcement circuit and method based on a comparator and a compensation tube, the negative single event transient reinforcement circuit comprising a comparator, a connecting tube, a compensation tube, a capacitor, a seventh resistor and an eighth resistor; the seventh resistor and the eighth resistor form a resistor network, a reference voltage is arranged between the seventh resistor and the eighth resistor; a positive input end of the comparator is connected with the reference voltage, a negative input end of the comparator is connected with an output voltage Vout, a control end is connected with a control voltage Ven, and an output end of the comparator is connected with a gate of the connecting tube and the compensation tube; a source of the connecting tube is connected with a source of the compensation tube, one end of the capacitor, and a gate of a power tube respectively, and the other end of the capacitor is grounded, the reinforcement circuit of the application forms an effect of isolating the power tube and an error amplifier when a negative single event transient pulse arrives, and compensating the charge flowing out of the negative single event transient pulse through the connecting tube, thereby reducing the influence of the negative single event transient pulse, and playing a reinforcement role.

Description

Technical Field

[0001] This application relates to the field of transient hardening circuit technology, and in particular to a negative single-event transient hardening circuit and method based on a comparator and a compensation transistor. Background Technology

[0002] Particle transients are caused by the energy transfer of particles to electrons in a medium. When a particle (such as an electron or photon) passes through a medium, it interacts with atoms or molecules in the medium, causing electrons to be excited or stripped from their atomic orbitals. These excited or ionized states exist only momentarily and decay rapidly. During this process, holes are formed, which move through the surrounding medium until they recombine with other electrons. The timescale of this recombination process is shorter than the timescale of the interaction between the electron and the medium, so it can be assumed that all electrons recombine simultaneously within a short period of time. Single-event transients can be used to develop highly sensitive single-event sensors. By combining a sensitive medium with an electron detector, the signal can be captured when a particle passes through the medium and causes a transient effect. Such single-event sensors can be used in fields such as environmental monitoring and life science research. Single-event transients can also be used to evaluate the reliability of electronic devices. In electronic devices, single-event transients can lead to malfunctions or device damage, making reliability assessment crucial. Through simulation or experiments, the response of electronic devices to single-event transients and their resistance to particle radiation can be studied, thus guiding the design and manufacture of electronic devices.

[0003] LDO stands for Low Dropout Linear Regulator, primarily used to convert unstable DC voltages into stable DC output voltages. LDOs are a new generation of integrated circuit regulators. Their biggest difference from three-terminal regulators is that LDOs are miniature system-on-a-chip (SoCs) with very low self-dissipation. They can be used for main current channel control, integrating hardware circuitry such as MOSFETs with extremely low on-resistance, Schottky diodes, sampling resistors, and voltage divider resistors on the chip. They also feature overcurrent protection, overtemperature protection, a precision reference source, a differential amplifier, and a delay circuit. LDOs typically have extremely low intrinsic noise and high power supply rejection ratio (PSRR). However, current LDOs lack hardening circuitry, making them susceptible to damage from negative single-event transients (SOETs). Therefore, it is necessary to design a SOET hardening circuit. Summary of the Invention

[0004] This application provides a negative single-event transient hardening circuit and method based on comparators and compensation transistors to solve the problem that current LDOs are easily affected by negative single-event transient pulses. It realizes the isolation of power transistors and error amplifiers when negative single-event transient pulses arrive, thereby reducing the impact of negative single-event transient pulses.

[0005] This application provides a negative single-event transient hardening circuit based on a comparator and a compensation transistor. The negative single-event transient hardening circuit includes a comparator, a connecting transistor, a compensation transistor, a capacitor, a seventh resistor, and an eighth resistor.

[0006] The seventh resistor and the eighth resistor form a resistor network, and a reference voltage Vout_min is set between the seventh resistor and the eighth resistor;

[0007] The positive input terminal of the comparator is connected to the reference voltage Vout_min, the negative input terminal of the comparator is connected to the output voltage Vout, the control terminal is connected to the control voltage Ven, and the output terminal of the comparator is connected to the gate of the connecting transistor and the compensation transistor.

[0008] The source of the connecting transistor is connected to the source of the compensation transistor, one end of the capacitor, and the gate of the power transistor, respectively, and the other end of the capacitor is grounded.

[0009] The drain of the connecting tube is connected to the output terminal of the error amplifier, the source of the power tube is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the negative input terminal of the error amplifier and one end of the sixth resistor, and the other end of the sixth resistor is grounded.

[0010] The positive input terminal of the error amplifier is connected to the Vref reference voltage terminal.

[0011] Preferably, the comparator consists of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit, and an output buffer circuit, wherein the bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit, and the output buffer circuit.

[0012] Preferably, the first-stage differential amplifier circuit includes a second transistor, a first differential input transistor, a second differential input transistor, a first load transistor, a second load transistor, a first reset transistor, and a second reset transistor. The source of the second transistor is grounded, and its gate is connected to the gate of the eighth transistor in the bias circuit. The drain of the second transistor is connected to the source of the first differential input transistor and the source of the second differential input transistor, respectively. The drain of the first differential input transistor is connected to the drain of the first load transistor and the drain of the first reset transistor, respectively. The drain of the second differential input transistor is connected to the drain of the second reset transistor and the drain of the second load transistor, respectively.

[0013] Preferably, the second-stage differential-to-single-ended output circuit includes a third transistor, a third differential input transistor, a fourth differential input transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a third load transistor, a fourth load transistor, a fifth load transistor, a sixth load transistor, a third reset transistor, and a fourth reset transistor. The gate of the third transistor is connected to the gate of the eighth transistor, the source of the third transistor is grounded, and the drain of the third transistor is connected to the source of the third differential input transistor and the source of the fourth differential input transistor, respectively.

[0014] The drain of the third differential input transistor is connected to the drain of the fifth load transistor, the drain of the fourth differential input transistor is connected to the drain of the fourth load transistor, the gate of the third differential input transistor is connected to the drain of the third load transistor and the drain of the sixth transistor, the source of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the drain of the fourth transistor.

[0015] The drain of the fourth differential input transistor is connected to the drain of the fourth load transistor and the drain of the fourth reset transistor, respectively. The gate of the fourth differential input transistor is connected to the drain of the fourth load transistor and the drain of the seventh transistor, respectively. The source of the seventh transistor is grounded, and the drain of the seventh transistor is also connected to the drain of the fifth transistor.

[0016] The gate of the fifth load transistor is connected to the gate of the sixth load transistor and to the drain of the third reset transistor.

[0017] Preferably, the output buffer circuit consists of three inverters connected in series, with the input terminal of each inverter connected to the drain of a fourth differential input transistor.

[0018] Preferably, the bias circuit includes a fifth reset transistor, a first transistor, and an eighth transistor. A fourth resistor, a first resistor, a second resistor, and a third resistor are connected in series between the drain of the fifth reset transistor and the drain of the eighth transistor. The source of the eighth transistor is grounded, the drain of the first transistor is connected to the drain of the eighth transistor, and the source of the first transistor is grounded.

[0019] A preferred hardening method for a negative single-event transient hardening circuit based on a comparator and a compensation transistor includes the following steps:

[0020] A. Before the LDO enters normal operation, the control signal Ven is low, the comparator is not working, the comparator output is low, the connecting tube is turned on, the compensation tube is turned off, the error amplifier discharges the gate of the power tube, Vg becomes high, and the LDO output voltage Vout becomes high.

[0021] B. When the LDO enters the normal operating state, the control voltage Ven is high, the comparator starts to work, and at this time the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network. The comparator output is low, the connecting transistor remains on, the compensation transistor remains off, and the LDO works stably.

[0022] C. When a negative single-event transient pulse occurs, the LDO output Vout is less than the reference voltage Vout_min, the comparator output is high, the connecting tube is disconnected, the compensation tube is turned on, the capacitor starts to maintain the gate voltage of the power tube, and at the same time the compensation tube starts to slowly discharge to the gate of the power tube to compensate for the charge flowing out by the negative single-event transient pulse.

[0023] D. As the charge is compensated, the gate voltage Vg of the power transistor gradually increases, and the output voltage Vout of the LDO gradually increases. When the output voltage Vout of the LDO rises to a level greater than the reference voltage Vout_min formed by the resistor network, the negative single-event transient pulse of the error amplifier EA has ended.

[0024] E. When the comparator's output voltage returns to a low level, the connecting transistor P11 turns on, the compensation transistor N13 turns off, and the gate of the power transistor N12 is connected to the output of the error amplifier, the LDO returns to normal operation.

[0025] Beneficial effects: The hardening circuit of the present invention isolates the power transistor and error amplifier when a negative single-event transient pulse arrives, and compensates for the charge flowing out of the negative single-event transient pulse through the connecting transistor, thereby reducing the influence of the negative single-event transient pulse and playing a hardening role.

[0026] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is the circuit schematic diagram of the present invention;

[0029] Figure 2 This is a schematic diagram of the comparator circuit of the present invention;

[0030] Figure 3 This is a schematic diagram showing the LDO output results before and after reinforcement.

[0031] Figure 4 This is a schematic diagram of an unreinforced LDO. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion.

[0034] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0036] Please see Figures 1-3 The present invention discloses a negative single-event transient hardening circuit based on a comparator and a compensation transistor. The negative single-event transient hardening circuit includes a comparator, a connecting transistor P11, a compensation transistor N13, a capacitor C1, a seventh resistor R7 and an eighth resistor R8.

[0037] The seventh resistor R7 and the eighth resistor R8 form a resistor network, and a reference voltage Vout_min is set between the seventh resistor R7 and the eighth resistor R8;

[0038] The positive input terminal of the comparator is connected to the reference voltage Vout_min, the negative input terminal of the comparator is connected to the output voltage Vout, the control terminal is connected to the control voltage Ven, and the output terminal of the comparator is connected to the gate of the connecting transistor P11 and the compensation transistor N13.

[0039] The source of the connecting transistor P11 is connected to the source of the compensation transistor N13, one end of the capacitor C1, and the gate of the power transistor N12, respectively, and the other end of the capacitor C1 is grounded.

[0040] The drain of the connecting transistor P11 is connected to the output terminal of the error amplifier, the source of the power transistor N12 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the negative input terminal of the error amplifier and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded.

[0041] The positive input terminal of the error amplifier is connected to the Vref reference voltage terminal.

[0042] In this circuit, the connecting transistor P11 acts as an isolation element, controlling the switching between the output of the error amplifier EA and the gate of the power transistor N12 based on the output of the comparator CMP. The compensation transistor N13, similarly controlled by the output of the comparator CMP, is used to slowly compensate for the charge lost from the gate of the power transistor N12 during negative pulses. Capacitor C1 maintains the stability of the gate-2 voltage of the power transistor N1 when the connecting transistor P11 is disconnected, and also provides a filtering effect.

[0043] In this invention, the comparator consists of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit, and an output buffer circuit. The bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit, and the output buffer circuit.

[0044] The first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load transistor P1, a second load transistor P4, a first reset transistor P2, and a second reset transistor P3. The source of the second transistor N2 is grounded, and its gate is connected to the gate of the eighth transistor N0 in the bias circuit. The drain of the second transistor N2 is connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4. The drain of the first differential input transistor N3 is connected to the drain of the first load transistor P1 and the drain of the first reset transistor P2. The drain of the second differential input transistor N4 is connected to the drain of the second reset transistor P3 and the drain of the second load transistor P4.

[0045] The second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7, and a fourth reset transistor P9. The gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7, respectively.

[0046] The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5.

[0047] The drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, respectively. The gate of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, respectively. The source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6.

[0048] The gate of the fifth load transistor P8 is connected to the gate of the sixth load transistor P10 and to the drain of the third reset transistor P7.

[0049] The output buffer circuit consists of three inverters connected in series, with the input terminals of the inverters connected to the drain of the fourth differential input transistor N7.

[0050] The bias circuit includes a fifth reset transistor P0, a first transistor N1, and an eighth transistor N0. The drain of the fifth reset transistor P0 and the drain of the eighth transistor N0 are connected in series with a fourth resistor R0, a first resistor R1, a second resistor R2, and a third resistor R3. The source of the eighth transistor N0 is grounded, and the drain of the first transistor N1 is connected to the drain of the eighth transistor N0. The source of the first transistor N1 is grounded.

[0051] When the control voltage Vcmp_en is high, the comparator enters normal operation. The second transistor N2 replicates the current from the bias circuit. At this time, the differential amplifier receives two input voltages, Vin_m and Vin_p. The end with the higher voltage receives more current, therefore its drain voltage Vom1 or Vop1 is lower. These two voltages control the conduction states of the fourth transistor P5 and the fifth transistor P6. The end with the lower voltage between Vom1 and Vop1 generates a larger current, pulling Vop2 or Vom2 high. Simultaneously, due to the positive feedback formed by the sixth transistor N8 and the seventh transistor N11, the voltage difference between Vop2 and Vom2 is amplified, serving as the differential input for the differential-to-single-ended converter. The fifth load transistor P8 and the sixth load transistor P10 convert the differential signal into a single-ended signal, which serves as the output.

[0052] Working principle: The hardening method for a negative single-event transient hardening circuit based on a comparator and a compensation transistor includes the following steps:

[0053] A. Before the LDO enters normal working state, the control signal Ven is low, the comparator does not work, the comparator output is low, the connecting tube P11 is turned on, the compensation tube N13 is turned off, the error amplifier discharges the gate of the power tube N12, Vg becomes high, and the LDO output voltage Vout becomes high.

[0054] B. When the LDO enters the normal working state, the control voltage Ven is high and the comparator starts to work. At this time, the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network. The comparator output is low, the connecting transistor P11 remains on, the compensation transistor N13 remains off, and the LDO works stably.

[0055] C. When a negative single-event transient pulse occurs, the LDO output Vout is less than the reference voltage Vout_min, the comparator output is high, the connecting transistor P11 is disconnected, the compensation transistor N13 is turned on, the capacitor C1 starts to maintain the gate voltage of the power transistor N12, and at the same time, the compensation transistor N13 starts to slowly discharge to the gate of the power transistor N12 to compensate for the charge flowing out by the negative single-event transient pulse.

[0056] D. As the charge is compensated, the gate voltage Vg of the power transistor N12 gradually increases, and the output voltage Vout of the LDO gradually increases. When the output voltage Vout of the LDO rises to a level greater than the reference voltage Vout_min formed by the resistor network, the negative single-event transient pulse of the error amplifier EA has ended.

[0057] E. When the comparator's output voltage returns to a low level, the connecting transistor P11 turns on, the compensation transistor N13 turns off, and the gate of the power transistor N12 is connected to the output of the error amplifier, the LDO returns to normal operation.

[0058] In summary, the hardening circuit of the present invention isolates the power transistor and error amplifier when a negative single-event transient pulse arrives, and compensates for the charge flowing out of the negative single-event transient pulse through the connecting transistor, thereby reducing the impact of the negative single-event transient pulse and playing a hardening role.

[0059] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A negative single-event transient hardening circuit based on a comparator and a compensation transistor, characterized in that, The negative single-event transient hardening circuit includes a comparator, a connecting transistor P11, a compensation transistor N13, a capacitor C1, a seventh resistor R7, and an eighth resistor R8. The seventh resistor R7 and the eighth resistor R8 form a resistor network, and a reference voltage Vout_min is set between the seventh resistor R7 and the eighth resistor R8; The positive input terminal of the comparator is connected to the reference voltage Vout_min, the negative input terminal of the comparator is connected to the output voltage Vout, the control terminal is connected to the control voltage Ven, and the output terminal of the comparator is connected to the gate of the connecting transistor P11 and the compensation transistor N13. The source of the connecting transistor P11 is connected to the source of the compensation transistor N13, one end of the capacitor C1, and the gate of the power transistor N12, respectively, and the other end of the capacitor C1 is grounded. The drain of the connecting transistor P11 is connected to the output terminal of the error amplifier, the source of the power transistor N12 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the negative input terminal of the error amplifier and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded. The positive input terminal of the error amplifier is connected to the Vref reference voltage terminal.

2. The negative single-event transient hardening circuit based on a comparator and a compensation transistor according to claim 1, characterized in that, The comparator consists of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit, and an output buffer circuit. The bias circuit is connected in sequence to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit, and the output buffer circuit.

3. The negative single-event transient hardening circuit based on a comparator and a compensation transistor according to claim 2, characterized in that, The first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load transistor P1, a second load transistor P4, a first reset transistor P2, and a second reset transistor P3. The source of the second transistor N2 is grounded, and its gate is connected to the gate of the eighth transistor N0 in the bias circuit. The drain of the second transistor N2 is connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4, respectively. The drain of the first differential input transistor N3 is connected to the drain of the first load transistor P1 and the drain of the first reset transistor P2, respectively. The drain of the second differential input transistor N4 is connected to the drain of the second reset transistor P3 and the drain of the second load transistor P4, respectively.

4. The negative single-event transient hardening circuit based on a comparator and a compensation transistor according to claim 2, characterized in that, The second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7, and a fourth reset transistor P9. The gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7, respectively. The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5. The drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, respectively. The gate of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, respectively. The source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6. The gate of the fifth load transistor P8 is connected to the gate of the sixth load transistor P10 and to the drain of the third reset transistor P7.

5. The negative single-event transient hardening circuit based on a comparator and a compensation transistor according to claim 2, characterized in that, The output buffer circuit consists of three inverters connected in series, with the input terminal of each inverter connected to the drain of the fourth differential input transistor N7.

6. The negative single-event transient hardening circuit based on a comparator and a compensation transistor according to claim 2, characterized in that, The bias circuit includes a fifth reset transistor P0, a first transistor N1, and an eighth transistor N0. The drain of the fifth reset transistor P0 and the drain of the eighth transistor N0 are connected in series with a fourth resistor R0, a first resistor R1, a second resistor R2, and a third resistor R3. The source of the eighth transistor N0 is grounded, and the drain of the first transistor N1 is connected to the drain of the eighth transistor N0. The source of the first transistor N1 is grounded.

7. The hardening method for implementing the negative single-event transient hardening circuit based on a comparator and a compensation transistor as described in claim 1, characterized in that, The reinforcement method includes the following steps: A. Before the LDO enters normal working state, the control signal Ven is low, the comparator does not work, the comparator output is low, the connecting tube P11 is turned on, the compensation tube N13 is turned off, the error amplifier discharges the gate of the power tube N12, Vg becomes high, and the LDO output voltage Vout becomes high. B. When the LDO enters the normal working state, the control voltage Ven is high and the comparator starts to work. At this time, the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network. The comparator output is low, the connecting transistor P11 remains on, the compensation transistor N13 remains off, and the LDO works stably. C. When a negative single-event transient pulse occurs, the LDO output Vout is less than the reference voltage Vout_min, the comparator output is high, the connecting transistor P11 is disconnected, the compensation transistor N13 is turned on, the capacitor C1 starts to maintain the gate voltage of the power transistor N12, and at the same time, the compensation transistor N13 starts to slowly discharge to the gate of the power transistor N12 to compensate for the charge flowing out by the negative single-event transient pulse. D. As the charge is compensated, the gate voltage Vg of the power transistor N12 gradually increases, and the output voltage Vout of the LDO gradually increases. When the output voltage Vout of the LDO rises to a level greater than the reference voltage Vout_min formed by the resistor network, the negative single-event transient pulse of the error amplifier EA has ended. E. When the comparator's output voltage returns to a low level, the connecting transistor P11 turns on, the compensation transistor N13 turns off, and the gate of the power transistor N12 is connected to the output of the error amplifier, the LDO returns to normal operation.

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