Ddl circuit, control method, and electronic device

Abstract

The application discloses a DLL circuit, a control method and electronic equipment, and belongs to the technical field of electronic equipment. The DLL circuit comprises a phase detector, a charge pump, a voltage-controlled delay line and a processing unit. The ring oscillator in the voltage-controlled delay line oscillates and processes an input clock signal to output an oscillation signal. The processing unit adjusts the load capacitance of a second delay unit of the ring oscillator when the frequency of the oscillation signal does not meet a target frequency, until the target frequency is met, the ring oscillator is controlled to stop working, and the load capacitance of the first delay unit and the second delay unit is equal to that of the first delay unit in the voltage-controlled delay line. The voltage-controlled delay line delays and processes the input clock signal to output a target clock signal. The phase detector outputs a phase difference signal according to the phases of the target clock signal and the input clock signal. The charge pump outputs a control voltage signal according to the phase difference signal. The application improves the adjustment range of the delay duration of the first delay unit.

Description

Technical Field

[0001] This application belongs to the field of electronic equipment technology, specifically relating to a DLL circuit, a control method, and an electronic device. Background Technology

[0002] A delay-locked loop (DLL) circuit is a clock generation circuit used to output a clock signal that is phase-aligned with a delayed input clock signal. DLL circuits are widely used in microprocessors, memory interfaces, chip-to-chip interfaces, and clock distribution networks for large-scale integrated circuits.

[0003] However, current DLL circuits are limited by the way they delay the input clock signal. The frequency of the input clock signal that a DLL circuit can delay is positively correlated with the number of delay units in the DLL circuit. That is, the higher the frequency of the input clock signal that the DLL circuit needs to delay, the larger the number of delay units in the DLL circuit. Therefore, the frequency of the input clock signal is limited by the circuit area of ​​the DLL circuit. Furthermore, since the frequency of the output signal of the DLL circuit is equal to the frequency of the input clock signal, the frequency of the output signal of the DLL circuit is also correspondingly limited, resulting in a narrow frequency range for the output signal of the DLL circuit. Summary of the Invention

[0004] The DLL circuit, control method, and electronic device provided in this application can, to a certain extent, solve the problem of the narrow frequency range of the output signal in current DLL circuits.

[0005] In a first aspect, a DLL circuit is provided, the DLL circuit comprising: a phase detector, a charge pump unit, a voltage-controlled delay line and a processing unit connected in sequence, wherein the voltage-controlled delay line is also connected to the phase detector;

[0006] The voltage-controlled delay line includes a ring oscillator and multiple cascaded first delay units, the ring oscillator includes multiple cascaded second delay units, and the ring oscillator is used to generate an oscillation signal;

[0007] The processing unit is configured to adjust the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, control the ring oscillator to stop working, and control the load capacitance of the first delay unit and the second delay unit to be equal; wherein, the target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units;

[0008] The voltage-controlled delay line is used to delay the input clock signal through the multiple cascaded first delay units when the ring oscillator is not working, and output the target clock signal.

[0009] The phase detector is used to output a phase difference signal based on the phase comparison result between the target clock signal and the input clock signal;

[0010] The charge pump unit is used to output a control voltage signal based on the phase difference signal. The control voltage signal is used to adjust the delay duration of the first delay unit until the target clock signal is delayed by one clock cycle of the input clock signal relative to the input clock signal.

[0011] In a second aspect, a control method for a DLL circuit is provided, applied to any of the DLL circuits described in the first aspect, the method comprising:

[0012] Control the operation of the ring oscillator;

[0013] If the frequency of the oscillation signal output by the ring oscillator does not meet the target frequency, the load capacitance of the second delay unit is adjusted. The target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line. The first ratio is the ratio of the number of the second delay units to the number of the first delay units.

[0014] When the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the ring oscillator is controlled to stop working, and the load capacitances of the first delay unit and the second delay unit are controlled to be equal.

[0015] The input clock signal is delayed by the multiple cascaded first delay units to obtain the target clock signal;

[0016] The phase detector compares the phase of the target clock signal and the input clock signal.

[0017] If, based on the phase comparison result, it is determined that the delay of the target clock signal relative to the input clock signal is less than one clock cycle, the delay duration of the first delay unit is adjusted by the charge pump unit, and the input clock signal is delayed again by the first delay unit until the delay of the target clock signal relative to the input clock signal satisfies one clock cycle.

[0018] Thirdly, an electronic device is provided, the electronic device comprising any of the DLL circuits described in the first aspect.

[0019] Fourthly, an electronic device is provided, comprising: a processor and a memory; the memory for storing a computer program; the processor for executing the program stored in the memory to implement the steps of the method as described in any of the second aspects.

[0020] Fifthly, a readable storage medium is provided, on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method as described in any of the second aspects.

[0021] In a sixth aspect, a computer program product is provided, comprising a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described in the second aspect.

[0022] In this embodiment, the DLL circuit includes a phase detector, a charge pump unit, a voltage-controlled delay line (VCD), and a processing unit connected in sequence, and the VCD is also connected to the phase detector. The VCD includes a ring oscillator and multiple cascaded first delay units. The ring oscillator includes multiple cascaded second delay units.

[0023] The ring oscillator generates an oscillation signal. If the frequency of the oscillation signal does not meet the target frequency, the processing unit can adjust the load capacitance of the second delay unit in the ring oscillator to adjust the delay duration of the second delay unit, thereby adjusting the oscillation frequency of the ring oscillator until the frequency of the oscillation signal generated by the ring oscillator meets the target frequency. This target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line, where the first ratio is the ratio of the number of second delay units to the number of first delay units.

[0024] In this way, when the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the processing unit controls the load capacitance of the first delay unit and the second delay unit in the voltage-controlled delay line to be equal, so that the capacitance value of the load capacitance of each first delay unit meets the capacitance value requirement corresponding to the frequency of the input clock signal. This allows the voltage-controlled delay line to delay the input clock signal through all the first delay units, outputting a target clock signal with a frequency equal to the input clock signal. The phase detector outputs a phase difference signal to the charge pump unit based on the phase comparison result between the target clock signal and the input clock signal. The charge pump unit then outputs a control voltage signal based on the phase difference signal to adjust the delay duration of the first delay units until the target clock signal is delayed by one clock cycle relative to the input clock signal, thus achieving effective locking of the DLL circuit.

[0025] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line (VCD) to match the frequency of the input clock signal that the VCD requires for delay processing. This reduces the frequency of the input clock signal processed by the DLL circuit, thus minimizing its impact on the number of first delay units in the VCD and the circuit area of ​​the DLL circuit. This effectively expands the frequency range of the input clock signals that the DLL circuit can process, thereby effectively improving the frequency range of the DLL circuit's output signal. Furthermore, the delay units in the VCD often have varying supported input clock signal frequency ranges due to process angles, temperature, and other factors. This application's technical solution can also utilize a ring oscillator to correct the delay and frequency deviations supported by individual first delay units in the VCD. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a DLL circuit provided in an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of the structure of a voltage-controlled delay line provided in an embodiment of this application;

[0028] Figure 3 This is a schematic diagram of another DLL circuit provided in an embodiment of this application;

[0029] Figure 4 This is a flowchart of a control method for a DLL circuit provided in an embodiment of this application;

[0030] Figure 5 This is a block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] A DLL circuit is a clock generation circuit that outputs a clock signal that is phase-aligned with an input clock signal. DLL circuits are widely used in microprocessors, memory interfaces, chip-to-chip interfaces, and clock distribution networks for large-scale integrated circuits.

[0033] The current DLL circuit mainly includes a phase comparator, a charge pump unit, and a voltage-controlled delay line (VCD). The delay units in the VCD can delay the input clock signal and output a delayed clock signal. The phase comparator outputs a phase difference signal based on the phase comparison between the delayed clock signal and the input clock signal. The charge pump unit outputs a control voltage to the VCD based on the phase difference signal, changing the delay duration of the delay units in the VCD. This causes the delay units in the VCD to re-delay the input clock signal until the VCD outputs a delayed clock signal that is delayed by one target clock cycle compared to the input clock signal, at which point the DLL circuit locks in. The frequency of the delayed clock signal output by the VCD is equal to the frequency of the input clock signal, and the phase difference is one target clock cycle. The target clock cycle is the clock cycle of the input clock signal. Furthermore, the DLL circuit can also output the delayed clock signal from each delay unit in the VCD.

[0034] However, current DLL circuits are limited by the way they delay the input clock signal. The frequency of the input clock signal that a DLL circuit can delay is positively correlated with the number of delay units in the DLL circuit. That is, the higher the frequency of the input clock signal that the DLL circuit needs to delay, the larger the number of delay units in the DLL circuit. Therefore, the frequency of the input clock signal is limited by the circuit area of ​​the DLL circuit. Furthermore, since the frequency of the output signal of the DLL circuit is equal to the frequency of the input clock signal, the frequency of the output signal of the DLL circuit is also correspondingly limited, resulting in a narrow frequency range for the output signal of the DLL circuit.

[0035] Please refer to Figure 1 This illustrates a structural diagram of a DLL circuit provided in an embodiment of this application. Figure 1 As shown, the DLL circuit 100 includes a phase detector (PD) 101, a charge pumping (CP) unit 102, a voltage-controlled delay line (VCD) 103, and a processing unit 104 connected in sequence, with the VCD 103 also connected to the phase detector 101. The phase detector 101, charge pumping unit 102, and VCD 103 can form a circuit loop.

[0036] The voltage-controlled delay line 103 includes a ring oscillator 1031 and a plurality of cascaded first delay units 1032. The ring oscillator 1031 includes a plurality of cascaded second delay units. The ring oscillator 1031 is used to generate an oscillation signal. Optionally, the ring oscillator 1031 is used to generate an oscillation signal when each second delay unit receives the same voltage control signal transmitted by the charge pump unit 102.

[0037] The processing unit 104 is used to adjust the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, control the ring oscillator 1031 to stop working, and control the load capacitance of the first delay unit 1032 and the second delay unit to be equal.

[0038] The voltage-controlled delay line 103 is used to delay the input clock signal through multiple cascaded first delay units 1032 (i.e., all the first delay units 1032 of the voltage-controlled delay line 103) when the ring oscillator 1031 is stopped, and output the target clock signal.

[0039] Phase detector 101 outputs a phase difference signal based on the phase comparison result between the target clock signal and the input clock signal. Optionally, phase detector 101 is also called a phase frequency detector (PFD), and its output phase difference signal may include a first phase signal DN and a second phase signal UP. When the phase of the input clock signal leads the target clock signal, the first phase signal DN output by phase detector 101 is low, and the second phase signal UP is high. The phase difference signal indicates that the delay time of the first delay unit needs to be reduced. When the phase of the target clock signal leads the target clock signal, the first phase signal DN output by phase detector 101 is high, and the second phase signal UP is low. The phase difference signal indicates that the delay time of the first delay unit needs to be increased. When the phase of the target clock signal is equal to the phase of the input clock signal, the first phase signal DN output by phase detector 101 is low, and the second phase signal UP is low. The phase difference signal indicates that the phase of the target clock signal is aligned with the phase of the input clock signal, and DLL circuit 100 is locked.

[0040] The charge pump unit 102 is used to output a control voltage signal based on the phase difference signal. The control voltage signal is used to adjust the delay duration of the first delay unit 1032 until the target clock signal is delayed by one clock cycle of the input clock signal relative to the input clock signal.

[0041] In this embodiment, the voltage-controlled delay line 103 is used to generate an oscillation signal by oscillating through the ring oscillator 1031 when the ring oscillator 1031 is working. The processing unit 104 is used to determine whether the frequency of the oscillation signal meets the target frequency. If the frequency of the oscillation signal does not meet the target frequency, the size of the load capacitance of the second delay unit is adjusted until the frequency of the oscillation signal meets the target frequency. At this time, the adjustment of the load capacitance of the second delay unit is stopped, and the ring oscillator 1031 is controlled to stop working. At this time, the frequency of the oscillation signal meets the target frequency, and the size of the load capacitance of the second delay unit is known. The processing unit 104 can be used to adjust the load capacitance of the first delay unit 1032 to be equal to the known size of the load capacitance of the second delay unit, so that the size of the load capacitance of the first delay unit 1032 and the load capacitance of the second delay unit are equal.

[0042] The voltage-controlled delay line 103 is also used to delay the input clock signal through all the first delay units 1032 and output a target clock signal when the ring oscillator 1031 is not working. The phase detector 101 is used to output a phase difference signal to the charge pump unit 102 based on the phase comparison result between the target clock signal and the input clock signal. The charge pump unit 102 is used to output a control voltage signal to the voltage-controlled delay line 103 based on the phase difference signal, so that the voltage-controlled delay line 103 delays the input clock signal again through all the first delay units 1032 after the delay time adjustment and outputs the target clock signal, until the phase detector 101 determines that the phases of the target clock signal and the input clock signal are equal, and the target clock signal is delayed by one clock cycle of the input clock signal compared to the input clock signal.

[0043] In the DLL output circuit DLL circuit 100, the target clock signal output by all the first delay units 1032 of the voltage-controlled delay line 103 has a signal frequency equal to that of the input clock signal. Furthermore, the oscillation frequency Fosc of the ring oscillator 1031 and the number N of its included second delay units satisfy the following condition: Fosc = 1 / (2 × N × Td). Fosc represents the oscillation frequency of the ring oscillator 1031, i.e., the frequency of the oscillation signal output by the ring oscillator 1031. N represents the number of second delay units within the ring oscillator 1031, and Td represents the delay duration of a single second delay unit.

[0044] Therefore, the target frequency required by the ring oscillator 1031 can be determined based on the ratio of the number of the second delay unit to the number of the first delay unit. Specifically, the target frequency is determined by the product of the first ratio and the frequency of the input clock signal Ref_clk of the voltage-controlled delay line 103. The first ratio is the ratio of the number of the second delay unit to the number of the first delay unit 1032. That is, the target frequency Fo satisfies: Fo = (N2 / N1) × FRef_clk Where Fo represents the target frequency. N2 represents the number of second delay units. N1 represents the number of first delay units 1032. F Ref_clk This indicates the frequency of the input clock signal.

[0045] Furthermore, since the load capacitance of the second delay unit in the ring oscillator can affect the delay duration of the second delay unit, when the number of second delay units in the ring oscillator is fixed, the delay duration of the second delay unit can be adjusted by adjusting the load capacitance of the second delay unit, thereby adjusting the frequency of the oscillation signal output by the ring oscillator.

[0046] Similarly, the size of the load capacitance of the first delay unit 1032 also affects the delay duration of the first delay unit 1032, and thus affects the frequency of the output signal of the voltage-controlled delay line 103. The frequency of the input signal (i.e., the input clock signal) of the voltage-controlled delay line 103 is equal to the frequency of the output signal. Therefore, it can be understood that the size of the load capacitance of the first delay unit 1032 affects the frequency of the input clock signal supported by the voltage-controlled delay line 103. Thus, when the load capacitances of the first delay unit 1032 and the second delay unit are equal, the delay durations of the first delay unit 1032 and the second delay unit are the same, and the ratio of the oscillation frequency of the ring oscillator to the frequency of the input clock signal supported by the voltage-controlled delay line is equal to the ratio of the number of second delay units to the number of first delay units.

[0047] In an optional configuration, the processing unit 104 can be used to adjust the load capacitance of the second delay unit according to a capacitance value variable when the frequency of the oscillation signal does not meet the target frequency. The capacitance value variable can be a fixed value. Alternatively, the capacitance value variable can decrease as the number of adjustments increases. Thus, the closer the frequency of the oscillation signal is to the target frequency, the smaller the capacitance value variable, resulting in higher accuracy in adjusting the delay time of the second delay unit.

[0048] In another alternative embodiment, both the first delay unit 1032 and the second delay unit include capacitor arrays. That is, the load capacitors of the first delay unit 1032 and the second delay unit are capacitor arrays.

[0049] The processing unit 104 can be used to adjust the number of capacitors in the capacitor array of the second delay unit that are in operation when the frequency of the oscillation signal does not meet the target frequency, thereby adjusting the size of the load capacitor of the second delay unit. Further optionally, the processing unit 104 can adjust the number of capacitors in the second delay unit that are in operation using a binary search method based on the number of capacitors in the capacitor array of the second delay unit, thereby adjusting the size of the load capacitor of the second delay unit. In this way, adjusting the size of the load capacitor of the second delay unit using the binary search method can more quickly adjust the frequency of the ring oscillator's oscillation signal to the target frequency, improving the adjustment efficiency of the delay time of the first and second delay units. In addition, the processing unit 104 can also adjust the number of capacitors in the second delay unit that are in operation using a traversal method based on the number of capacitors in the capacitor array of the second delay unit, thereby adjusting the size of the load capacitor of the second delay unit, etc. This application embodiment does not limit the method of adjusting the size of the load capacitor of the second delay unit.

[0050] It should be noted that the method by which the processing unit 104 adjusts the load capacitance of the first delay unit 1032 can refer to the method by which the processing unit 104 adjusts the load capacitance of the second delay unit.

[0051] In this embodiment, the DLL circuit includes a phase detector, a charge pump, a voltage-controlled delay line (VCD), and a processing unit connected in sequence, and the VCD is also connected to the phase detector. The VCD includes a ring oscillator and multiple cascaded first delay units. The ring oscillator includes multiple cascaded second delay units.

[0052] The ring oscillator generates an oscillation signal. If the frequency of the oscillation signal does not meet the target frequency, the processing unit adjusts the load capacitance of the second delay unit to adjust its delay duration until the oscillation signal frequency meets the target frequency. Thus, when the frequency of the oscillation signal output from the ring oscillator meets the target frequency, the processing unit controls the load capacitance of the first and second delay units in the voltage-controlled delay line to be equal, ensuring that the capacitance value of each first delay unit matches the capacitance value required for the input clock signal frequency. This allows the voltage-controlled delay line to delay the input clock signal through all the first delay units, outputting a target clock signal with a frequency equal to the input clock signal frequency. The phase detector outputs a phase difference signal to the charge pump unit based on the phase comparison between the target clock signal and the input clock signal. The charge pump unit then outputs a control voltage signal based on the phase difference signal to adjust the delay duration of the first delay units until the target clock signal is delayed by one clock cycle relative to the input clock signal, achieving effective locking of the DLL circuit.

[0053] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line (VCD) to match the frequency of the input clock signal required for delay processing by the VCD, thereby reducing the frequency of the input clock signal processed by the DLL circuit and minimizing its impact on the number of first delay units in the VCD and the circuit area of ​​the DLL circuit. This effectively expands the frequency range of the input clock signals that the DLL circuit can process, and consequently, effectively improves the frequency range of the output signal of the DLL circuit. Furthermore, the delay units in the VCD often have varying frequency ranges of supported input clock signals due to process angles, temperature, and other factors. This application's technical solution can also utilize a ring oscillator to correct the delay and frequency deviations supported by individual first delay units in the VCD. In addition, the configuration of adjusting the delay duration by adjusting the load capacitance and by using a control voltage signal output from a charge pump in the DLL circuit allows for adjustment of the delay duration of the first delay units using different granularity delay duration adjustment methods, effectively improving the adjustment accuracy of the delay duration of the first delay units in the VCD chain.

[0054] In this embodiment, the voltage-controlled delay line 103 includes a ring oscillator 1031 and multiple cascaded first delay units 1032. The ring oscillator 1031 includes multiple cascaded second delay units. The ring oscillator 1031 is used to oscillate the input clock signal Ref_clk and output an oscillation signal.

[0055] In an optional configuration, the multiple cascaded second delay units are a subset of the multiple cascaded first delay units 1032 that are cascaded consecutively. That is, the first delay units 1032 can be reused to form a ring oscillator 1031, reducing circuit components and simplifying the circuit structure. Figure 2 As shown, the ring oscillator 1031 includes a plurality of first delay units 1032 cascaded in succession. Furthermore, the ring oscillator 1031 also includes a switching unit 10311. The switching unit 10311 is connected to the first and last delay units of the plurality of second delay units, respectively.

[0056] The ring oscillator 1031 is used to oscillate the input clock signal and output an oscillation signal when the switch unit 10311 is closed. Correspondingly, the processing unit 104 is used to control the switch unit 10311 to open when the frequency of the oscillation signal meets the target frequency, so as to control the ring oscillator 103 to stop working.

[0057] The number of second delay units included in the ring oscillator 1031 is not limited. However, it should be noted that the number of inverters in the ring oscillator 1031 should be odd. Therefore, in an optional case, the ring oscillator 1031 includes n cascaded second delay units, where n is an odd number greater than 2.

[0058] In another alternative case, such as Figure 2 As shown, the ring oscillator 1031 includes n-1 cascaded second delay units. That is, the number of second delay units in the ring oscillator 1031 is even.

[0059] The switching unit 10311 of the ring oscillator 1031 includes: a first switch S1, an inverter G, and a second switch S2. The first terminal of the first switch S1 is connected to the first delay unit. The second terminal of the first switch S1 is connected to the first terminal of the second switch S2 via the inverter G. The second terminal of the second switch S2 is connected to the last delay unit.

[0060] The ring oscillator 1031 is used to oscillate the input clock signal and output an oscillation signal when both the first switch S1 and the second switch S2 are closed. The processing unit 104 is also used to control both the first switch S1 and the second switch S2 to be opened when the frequency of the oscillation signal meets the target frequency, so as to control the ring oscillator 1031 to stop working.

[0061] It should be noted that, Figure 2 Taking the voltage-controlled delay line 103 including 8 first delay units and the ring oscillator 1031 multiplexing 4 first delay units as an example, the description does not limit the number of first delay units that the voltage-controlled delay line 103 may include, or the number of first delay units that the ring oscillator 1031 may include.

[0062] For example, such as Figure 2 As shown, the voltage-controlled delay line 103 includes eight cascaded first delay units 1032 (first delay units 0 to 8). The ring oscillator 1031 multiplexes four cascaded first delay units 1032 (first delay units 3 to 6). The first terminal of the first switch S1 in the ring oscillator 1031 is connected to the first delay unit 3 1032. The second terminal of the first switch S1 is connected to the first terminal of the second switch S2 via an inverter G. The second terminal of the second switch S2 is connected to the first delay unit 6 1032. When the first switch S1 and the second switch S2 are closed, the first delay units 3 to 6 form a ring circuit structure through the first switch S1 and the second switch S2, constituting a ring oscillator.

[0063] Each first delay unit in the voltage-controlled delay line 103 receives the same control voltage signal output by the charge pump. With both the first switch S1 and the second switch S2 closed, the ring oscillator 1031 oscillates the input clock signal Ref_clk and outputs an oscillation signal Osc between the first delay unit 3 and the first delay unit 4.

[0064] When the frequency of the oscillation signal Osc does not meet the target frequency, the processing unit 104 outputs a capacitor adjustment signal Coarse swf<6:0> to the first delay units 3 to 6 to adjust the load capacitance of the first delay units 3 to 6 until the frequency of the oscillation signal meets the target frequency. The target frequency is 4 / 8×F. Ref_clk That is, 1 / 2 of F Ref_clk The capacitor adjustment signal is used to control the number of capacitors in the ring oscillator 1031 that are in operation.

[0065] The first delay units 3 to 6 in the ring oscillator 1031 are respectively used to adjust the number of capacitors in the capacitor array that are in the working state according to the capacitor adjustment signal. It should be noted that the oscillation signal Osc output by the ring oscillator 1031 can be the output signal between any two of its second delay units. Figure 2 The example given is an oscillation signal Osc, which is the output signal between the first second delay unit (first delay unit 3) and the second second delay unit (first delay unit 4) in the ring oscillator 1031. Of course, the oscillation signal Osc can also be the output signal between the second and third second delay units in the ring oscillator 1031, etc.

[0066] In another alternative embodiment, the second delay unit in the ring oscillator 1031 can also be an independent delay unit. In this case, the voltage-controlled delay line 103 includes a delay chain and a ring oscillator 1031. The delay chain includes multiple cascaded first delay units 1032. The delay chain is used to delay the input clock signal through all the first delay units 1032, output the target clock signal to the outside of the DLL circuit, and output the input clock signal and the target clock signal to the phase detector 101. The ring oscillator 1031 is used to oscillate the input clock signal through all the second delay units and output an oscillation signal to the processing unit 104.

[0067] In this embodiment, the processing unit 104 is used to adjust the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, control the ring oscillator 1031 to stop working, and the load capacitance of the first delay unit 1032 and the second delay unit are equal.

[0068] That is, the processing unit 104 receives the oscillation signal transmitted by the ring oscillator 1031 and determines whether the frequency of the oscillation signal meets the target frequency. If the frequency of the oscillation signal does not meet the target frequency, the load capacitance of the second delay unit is adjusted. If the frequency of the oscillation signal meets the target frequency, the ring oscillator 1031 is controlled to stop working, and the load capacitances of the first delay unit 1032 and the second delay unit are equal.

[0069] In an optional configuration, the processing unit 104 is further configured to adjust the load capacitance of the second delay unit until the frequency of the oscillation signal meets the target frequency when the frequency of the oscillation signal does not meet the target frequency, determine the current target capacitance value of the second delay unit, and adjust the load capacitance of the first delay unit to the target capacitance value.

[0070] In another optional embodiment, where the multiple cascaded second delay units in the ring oscillator 1031 are multiple consecutively cascaded first delay units, the processing unit 104 is further configured to adjust the load capacitance of all first delay units until the frequency of the oscillation signal meets the target frequency if the frequency of the oscillation signal does not meet the target frequency. The method by which the processing unit 104 adjusts the load capacitance of the second delay units and the method by which it adjusts the load capacitance of the first delay units can refer to the aforementioned method by which the processing unit 104 adjusts the load capacitance of the second delay units; this embodiment will not elaborate further.

[0071] In some embodiments of this application, the voltage-controlled delay line 103 is further used to output a delayed clock signal after delay processing for each first delay unit 1031. The target clock signal is the delayed clock signal output by the last first delay unit among the plurality of first delay units of the voltage-controlled delay line.

[0072] Optionally, the DLL circuit 100 further includes an error prevention lockout control circuit 105. The error prevention lockout control circuit 105 is connected to the voltage-controlled delay line 103 and the phase detector 101, respectively.

[0073] The error-proof lockout control circuit 105 determines the initial delay duration of the voltage-controlled delay line 103 based on multiple delayed clock signals with equal phase differences, and outputs a lockout adjustment signal based on the relationship between the initial delay duration and the effective delay range. The initial delay duration refers to the total delay duration of the voltage-controlled delay line before the first delay unit in the voltage-controlled delay line is adjusted by the processing unit 104 and the charge pump unit 102. When the target clock signal output by the voltage-controlled delay line within the effective delay range is in phase with the input clock signal, the target clock signal is delayed by one clock cycle compared to the input clock signal. Optionally, the effective delay range can be [0.5T].ref_clk 1.5T ref_clk ]. T ref_clk This indicates the clock period of the input clock signal Ref_clk.

[0074] Phase detector 101 is used to output a phase difference signal based on the phase comparison result of the target clock signal and the input clock signal and the lock adjustment signal.

[0075] Optionally, the lock adjustment signal of the error prevention lock control circuit 105 in this embodiment may include a first lock signal upper, a second lock signal under, and a third lock signal lock.

[0076] The error-prevention lockout control circuit 105 outputs a high-level second lockout signal "under" when the initial delay duration is less than the minimum of the effective delay range. This high-level second lockout signal "under" indicates that the delay duration of the first delay unit needs to be increased to prevent the DLL circuit from losing lockout.

[0077] The error-prevention lockout control circuit 105 is also used to output a high-level first lockout signal, upper, when the initial delay duration exceeds the maximum value of the effective delay range. This high-level first lockout signal, upper, indicates that the delay duration of the first delay unit needs to be reduced to prevent harmonic lockout in the DLL circuit.

[0078] The error-proof lockout control circuit 105 is also used to output a high-level third lock signal, lock, when the initial delay duration is within the effective delay range. This high-level third lock signal, lock, indicates that the DLL circuit can be locked.

[0079] Optionally, the phase detector 101 in this embodiment may include the following phase difference signal output by the phase detector 101 based on the phase comparison result of the target clock signal and the input clock signal and the lock adjustment signal: a first phase signal DN, a second phase signal UP, a third phase signal NDN, and a fourth phase signal NUP.

[0080] The phase detector 101 is used to output a low-level first phase signal DN, a high-level second phase signal UP, a low-level third phase signal NDN, and a high-level fourth phase signal NUP when the phase of the input clock signal leads the target clock signal and a high-level first lock signal upper is received. The phase difference signal indicates that the delay time of the first delay unit needs to be reduced.

[0081] Phase detector 101 is used to output a first phase signal DN (low level), a second phase signal UP (high level), a third phase signal NDN (low level), and a fourth phase signal NUP (low level) when the phase of the input clock signal leads the target clock signal and a first lock signal upper (low level) is received. The phase difference signal indicates that the delay time of the first delay unit needs to be reduced.

[0082] Phase detector 101 is used to output a high-level first phase signal DN, a low-level second phase signal UP, a high-level third phase signal NDN, and a low-level fourth phase signal NUP when the phase of the target clock signal leads the target clock signal and a high-level second lock signal under is received. The phase difference signal indicates that the delay time of the first delay unit needs to be increased.

[0083] Phase detector 101 is used to output a high-level first phase signal DN, a low-level second phase signal UP, a low-level third phase signal NDN, and a low-level fourth phase signal NUP when the phase of the target clock signal leads the target clock signal and a low-level second lock signal under is received. The phase difference signal indicates that the delay time of the first delay unit needs to be increased.

[0084] Phase detector 101 outputs a low-level first phase signal DN, a low-level second phase signal UP, a low-level third phase signal NDN, and a low-level fourth phase signal NUP when the phase of the target clock signal is equal to the phase of the input clock signal and a high-level third lock signal lock is received. The phase difference signal indicates that the phase of the target clock signal is aligned with the phase of the input clock signal, and the DLL circuit 100 is locked.

[0085] In this way, by using the phase detector 101 in conjunction with the error prevention lock control circuit 105, the DLL circuit can be effectively prevented from losing lock or being locked by harmonics, thereby improving the locking effectiveness of the DLL circuit 100.

[0086] Alternatively, the DLL circuit 100 may further include a switch selection circuit (multiplexer, MUX) 106. The switch selection circuit 106 is connected to the voltage-controlled delay line 103 and the error-proof lockout control circuit 105.

[0087] The switch selection circuit 106 receives the delayed clock signal of each delayed clock signal and outputs multiple delayed clock signals with equal phase differences to the error prevention lockout control circuit 105. The switch selection circuit 106 also receives a selection signal Sel and outputs a delayed clock signal Vcdl_output_clk corresponding to the selection signal Sel from the received multiple delayed clock signals. The selection signal Sel is used to select the phase difference of the delayed clock signals output by the DLL circuit 100. Optionally, the switch selection circuit 106 also outputs the delayed clock signal of each delayed clock signal.

[0088] Further optional, such as Figure 3 As shown, the charge pump unit 102 includes a charge pump 1021 and a ring filter 1022. The charge pump 1021 is connected to both the phase detector 101 and the ring filter 1022. The ring filter 1022 is also connected to the voltage-controlled delay line 103. The charge pump 1021 outputs a control current signal based on the phase difference signal. The ring filter 1022 converts the control current signal into a control voltage signal and outputs the control voltage signal. The ring filter 1022 is a low-pass filter, which can be used to filter out high-frequency components and noise in the control voltage signal. For example, the ring filter 1022 can be a capacitor CF. One end of the capacitor CF is connected to both the charge pump 1021 and the voltage-controlled delay line 103. The other end of the capacitor CF is grounded.

[0089] For example, such as Figure 3 As shown, the DLL circuit 100 further includes: a phase detector 101, a charge pump unit 102, a voltage-controlled delay line 103, a processing unit 104, an error-proof lockout control circuit 105, and a switch selection circuit 106. The charge pump unit 102 includes: a charge pump 1021 and a ring filter 1022. The voltage-controlled delay line 103 includes eight cascaded first delay units, and the ring oscillator 1031 multiplexes the first delay units.

[0090] The voltage-controlled delay line 103 can output the input clock signal of the first delay unit, namely the input clock signal Clk0 (Ref_clk), and the delayed clock signals Clk1-Clk8 output by each first delay unit to the switch selection circuit 106. The switch selection circuit 106 is also used to transmit equally spaced delayed clock signals Clk0, Clk2, Clk4, and Clk6 to the error-proof lockout control circuit 105. The switch selection circuit 106 is also used by the phase detector 101 to transmit the input clock signal Clk0 and the delayed clock signal output by the last first delay unit, namely the target clock signal Clk8. The switch selection circuit 106 is also used to output the input clock signal Clk0 and the delayed clock signals Clk1-Clk8 to the outside of the DLL circuit. The switch selection circuit 106 is also used to output the delayed clock signal Vcdl_output_clk corresponding to the selection signal Sel to the outside of the DLL circuit.

[0091] Before the DLL circuit locks, the charge pump unit 102 outputs an initial control voltage signal Vctr1 to the voltage-controlled delay line 103. The switching unit in the ring oscillator 1031 closes, generating and outputting an oscillation signal Osc to the processing unit 104. The processing unit 104 determines whether the frequency of the oscillation signal Osc meets the target frequency.

[0092] If the frequency of the oscillation signal Osc does not meet the target frequency, the processing unit 104 outputs a capacitor adjustment signal Coarse swf to the first delay unit in the ring oscillator 1031, so that the ring oscillator 1031 oscillates the parameter clock signal Ref_clk again through the adjusted first delay unit, and outputs the oscillation signal Osc to the processing unit 104. The capacitor adjustment signal is used to control the number of capacitors in the ring oscillator 1031 that are in operation.

[0093] When the frequency of the oscillation signal Osc meets the target frequency, the processing unit 104 outputs a switch-off signal Swi to the switching unit in the ring oscillator 1031, causing the switching unit of the ring oscillator 1031 to turn off and the ring oscillator 1031 to stop working. When the frequency of the oscillation signal Osc meets the target frequency, the processing unit 104 can also determine the current capacitor adjustment signal Coarse swf output to the first delay unit, and output the same capacitor adjustment signal Coarse swf to each first delay unit in the voltage-controlled delay line 103 other than the first delay unit included in the ring oscillator 1031, so that the delay duration of each first delay unit is equal to the delay duration of the first delay unit in the ring oscillator 1031.

[0094] When the ring oscillator 1031 is not working, the voltage-controlled delay line 103 delays the input clock signal Ref_clk through all the first delay units and outputs the target clock signal Clk8.

[0095] The error prevention lockout control circuit 105 determines the initial delay duration of the voltage-controlled delay line 103 based on the delayed clock signals Clk0, Clk2, Clk4, and Clk6 received from the switch selection circuit 106. Based on the relationship between the initial delay duration and the effective delay range, it outputs a lockout adjustment signal. The lockout adjustment signal may include a first lock signal (upper), a second lock signal (under), and a third lock signal (lock).

[0096] Phase detector 101 outputs a phase difference signal based on the phase comparison result between the target clock signal Clk8 and the input clock signal Clk0, as well as the lock adjustment signal. The phase difference signal includes: a first phase signal DN, a second phase signal UP, a third phase signal NDN, and a fourth phase signal NUP.

[0097] The charge pump unit 102 outputs a control current signal based on the phase difference signal. This control current signal is converted by the ring filter 1022 and then outputs a control voltage signal Vctrl to the voltage-controlled delay line 103. The control voltage signal Vctrl is used to adjust the delay duration of the first delay unit 1032. The voltage-controlled delay line 103, after adjusting the delay duration of all the first delay units 1032, further delays the input clock signal and outputs the target clock signal until the phase detector 101 determines that the target clock signal Clk8 and the input clock signal Clk0 are in phase. The target clock signal Clk8 is delayed by one clock cycle of the input clock signal Clk0 compared to the input clock signal Clk0.

[0098] In this embodiment, the delay duration of the first delay unit can meet the delay duration requirements corresponding to oscillation signals at different frequencies. This greatly expands the frequency range of the oscillation signals corresponding to the first delay unit, and also allows for adjustment of the delay duration of each first delay unit at different process angles and temperatures.

[0099] In summary, the DLL circuit provided in this application includes a phase detector, a charge pump, a voltage-controlled delay line (VCD), and a processing unit connected in sequence, and the VCD is also connected to the phase detector. The VCD includes a ring oscillator and multiple cascaded first delay units. The ring oscillator includes multiple cascaded second delay units.

[0100] The ring oscillator generates an oscillation signal. If the frequency of the oscillation signal does not meet the target frequency, the processing unit can adjust the load capacitance of the second delay unit in the ring oscillator to adjust the delay duration of the second delay unit, thereby adjusting the oscillation frequency of the ring oscillator until the frequency of the oscillation signal generated by the ring oscillator meets the target frequency. This target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line, where the first ratio is the ratio of the number of second delay units to the number of first delay units.

[0101] In this way, when the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the processing unit controls the load capacitance of the first delay unit and the second delay unit in the voltage-controlled delay line to be equal, so that the capacitance value of the load capacitance of each first delay unit meets the capacitance value requirement corresponding to the frequency of the input clock signal. This allows the voltage-controlled delay line to delay the input clock signal through all the first delay units, outputting a target clock signal with a frequency equal to the input clock signal. The phase detector outputs a phase difference signal to the charge pump unit based on the phase comparison result between the target clock signal and the input clock signal. The charge pump unit then outputs a control voltage signal based on the phase difference signal to adjust the delay duration of the first delay units until the target clock signal is delayed by one clock cycle relative to the input clock signal, thus achieving effective locking of the DLL circuit.

[0102] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line (VCD) to match the frequency of the input clock signal that the VCD requires for delay processing. This reduces the frequency of the input clock signal processed by the DLL circuit, thus minimizing its impact on the number of first delay units in the VCD and the circuit area of ​​the DLL circuit. This effectively expands the frequency range of the input clock signals that the DLL circuit can process, thereby effectively improving the frequency range of the DLL circuit's output signal. Furthermore, the delay units in the VCD often have varying supported input clock signal frequency ranges due to process angles, temperature, and other factors. This application's technical solution can also utilize a ring oscillator to correct the delay and frequency deviations supported by individual first delay units in the VCD.

[0103] Please refer to Figure 4 The diagram illustrates a flowchart of a control method for a DLL circuit provided in an embodiment of this application. The control method can be applied to the DLL circuit provided in the embodiment of this application. Optionally, the control method can be applied to... Figure 1 , Figure 3 The DLL circuit shown. (As shown in the image.) Figure 4 As shown, the control methods include:

[0104] Step 401: Control the ring oscillator to work.

[0105] In this embodiment, this step can be performed by the processing unit 104. Optionally, the processing unit 104 can control the ring oscillator 103 to operate by closing the control switch unit.

[0106] Step 402: If the frequency of the oscillation signal output by the ring oscillator does not meet the target frequency, adjust the load capacitance of the second delay unit.

[0107] The target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line. The first ratio is the ratio of the number of second delay units to the number of first delay units. This step can be performed by the processing unit 104. The method by which the processing unit 104 adjusts the load capacitance of the second delay unit can be referred to the foregoing description, and will not be repeated in this embodiment.

[0108] Step 403: When the frequency of the oscillation signal output by the ring oscillator meets the target frequency, control the ring oscillator to stop working, and the load capacitance of the first delay unit and the second delay unit are equal.

[0109] In this embodiment, this step can be executed by the processing unit 104. The processing unit 104 controls the ring oscillator to stop working, and the implementation method of the first delay unit and the second delay unit having equal load capacitance can refer to the foregoing description. This embodiment will not repeat the details.

[0110] Step 404: The input clock signal is delayed by multiple cascaded first delay units to obtain the target clock signal.

[0111] In this embodiment of the application, this step can be performed by the voltage-controlled delay line 103. The voltage-controlled delay line 103 delays the input clock signal through all the first delay units to obtain the target clock signal. The implementation method can be referred to the foregoing description, and will not be repeated in this embodiment of the application.

[0112] Step 405: Compare the phase of the target clock signal and the input clock signal using a phase detector.

[0113] In this embodiment, this step can be performed by the phase detector 101. The phase detector can compare the phase of the target clock signal and the input clock signal as described above, and will not be repeated in this embodiment.

[0114] Step 406: If, based on the phase comparison result, it is determined that the delay of the target clock signal relative to the input clock signal is less than one clock cycle, the delay duration of the first delay unit is adjusted by the charge pump, and the input clock signal is delayed again by the first delay unit until the delay of the target clock signal relative to the input clock signal meets one clock cycle.

[0115] In this embodiment, this step can be performed by the charge pump unit 102. The method by which the charge pump unit 102 adjusts the delay duration of the first delay unit can be referred to the foregoing description, and will not be repeated in this embodiment.

[0116] Optionally, the load capacitance of the second delay unit includes a capacitor array. The process of adjusting the size of the load capacitance of the second delay unit may include: adjusting the number of capacitors in the second delay unit that are in operation using a binary search method based on the number of capacitors in the capacitor array.

[0117] In this embodiment of the application, this step can be performed by the processing unit 104. The implementation method of the processing unit 104 adjusting the number of capacitors in the working state in the second delay unit according to the number of capacitors in the capacitor array using the binary method can be referred to the foregoing description, and will not be repeated in this embodiment of the application.

[0118] In summary, the DLL circuit provided in this application includes a phase detector, a charge pump, a voltage-controlled delay line (VCD), and a processing unit connected in sequence, and the VCD is also connected to the phase detector. The VCD includes a ring oscillator and multiple cascaded first delay units. The ring oscillator includes multiple cascaded second delay units.

[0119] The ring oscillator generates an oscillation signal. If the frequency of the oscillation signal does not meet the target frequency, the processing unit can adjust the load capacitance of the second delay unit in the ring oscillator to adjust the delay duration of the second delay unit, thereby adjusting the oscillation frequency of the ring oscillator until the frequency of the oscillation signal generated by the ring oscillator meets the target frequency. This target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line, where the first ratio is the ratio of the number of second delay units to the number of first delay units.

[0120] In this way, when the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the processing unit controls the load capacitance of the first delay unit and the second delay unit in the voltage-controlled delay line to be equal, so that the capacitance value of the load capacitance of each first delay unit meets the capacitance value requirement corresponding to the frequency of the input clock signal. This allows the voltage-controlled delay line to delay the input clock signal through all the first delay units, outputting a target clock signal with a frequency equal to the input clock signal. The phase detector outputs a phase difference signal to the charge pump unit based on the phase comparison result between the target clock signal and the input clock signal. The charge pump unit then outputs a control voltage signal based on the phase difference signal to adjust the delay duration of the first delay units until the target clock signal is delayed by one clock cycle relative to the input clock signal, thus achieving effective locking of the DLL circuit.

[0121] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line (VCD) to match the frequency of the input clock signal that the VCD requires for delay processing. This reduces the frequency of the input clock signal processed by the DLL circuit, thus minimizing its impact on the number of first delay units in the VCD and the circuit area of ​​the DLL circuit. This effectively expands the frequency range of the input clock signals that the DLL circuit can process, thereby effectively improving the frequency range of the DLL circuit's output signal. Furthermore, the delay units in the VCD often have varying supported input clock signal frequency ranges due to process angles, temperature, and other factors. This application's technical solution can also utilize a ring oscillator to correct the delay and frequency deviations supported by individual first delay units in the VCD.

[0122] This application also provides an electronic device, which may include the DLL circuit provided in this application. The electronic device may be a chip or a chip system.

[0123] This application also provides an electronic device. For example... Figure 5 As shown, the electronic device 500 may include a processor 501 and a memory 502. The memory 501 is used to store computer programs. The processor 502, when executing the program stored in the memory, implements the control method of the DLL circuit provided in this application embodiment. The electronic device may be or include the DLL circuit provided in this application embodiment. The electronic device 500 may be a chip or a chip system.

[0124] This application also provides a readable storage medium storing a program or instructions. When executed by a processor, the program or instructions implement the various processes of the control method embodiment for the DLL circuit described above, achieving the same technical effect. To avoid repetition, these will not be repeated here. The function of the processor can be referenced from the function of the processor in the electronic device described above. The readable storage medium includes computer-readable storage media, such as a computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0125] This application also provides a computer program product, including a computer program / instruction. When the computer program / instruction is executed by a processor, it implements the various processes of the control method embodiment of the DLL circuit described above and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0126] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A delay-locked loop (DLL) circuit, characterized in that, The DLL circuit includes: a phase detector, a charge pump unit, a voltage-controlled delay line, and a processing unit connected in sequence, and the voltage-controlled delay line is also connected to the phase detector; The voltage-controlled delay line includes a ring oscillator and multiple cascaded first delay units, the ring oscillator includes multiple cascaded second delay units, and the ring oscillator is used to generate an oscillation signal; The processing unit is configured to adjust the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, control the ring oscillator to stop working, and control the load capacitance of the first delay unit and the second delay unit to be equal; wherein, the target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units; The voltage-controlled delay line is used to delay the input clock signal through the multiple cascaded first delay units when the ring oscillator is not working, and output the target clock signal. The phase detector is used to output a phase difference signal based on the phase comparison result between the target clock signal and the input clock signal; The charge pump unit is used to output a control voltage signal based on the phase difference signal. The control voltage signal is used to adjust the delay duration of the first delay unit until the target clock signal is delayed by one clock cycle of the input clock signal relative to the input clock signal.

2. The DLL circuit according to claim 1, characterized in that, The plurality of cascaded second delay units are a plurality of first delay units that are cascaded in succession among the plurality of cascaded first delay units. The ring oscillator further includes: a switching unit, which is connected to the first delay unit and the last delay unit among the plurality of second delay units respectively. The ring oscillator is used to generate the oscillation signal when the switching unit is closed; The processing unit is used to control the switching unit to disconnect when the frequency of the oscillation signal meets the target frequency, so as to control the ring oscillator to stop working.

3. The DLL circuit according to claim 2, characterized in that, The number of the second delay units is even; the switching unit includes: a first switching element, an inverter, and a second switching element; The first end of the first switch is connected to the first delay unit, the second end of the first switch is connected to the first end of the second switch through the inverter, and the second end of the second switch is connected to the last delay unit. The ring oscillator is used to generate the oscillation signal when both the first switch and the second switch are closed. The processing unit is further configured to, when the frequency of the oscillation signal meets the target frequency, control both the first switch and the second switch to disconnect, so as to control the ring oscillator to stop working.

4. The DLL circuit according to any one of claims 1 to 3, characterized in that, The processing unit is further configured to, when the frequency of the oscillation signal does not meet the target frequency, adjust the load capacitance of the second delay unit until the frequency of the oscillation signal meets the target frequency, determine the current target capacitance value of the second delay unit, and adjust the load capacitance of the first delay unit to the target capacitance value. Alternatively, if the plurality of cascaded second delay units are plurality of consecutively cascaded first delay units, the processing unit is further configured to adjust the load capacitance of all the first delay units until the frequency of the oscillation signal meets the target frequency if the frequency of the oscillation signal does not meet the target frequency.

5. The DLL circuit according to claim 1, characterized in that, The voltage-controlled delay line is also used to output the delayed clock signal after delay processing for each of the first delay units; the DLL circuit further includes: an error prevention lockout control circuit; the error prevention lockout control circuit is connected to the voltage-controlled delay line and the phase detector respectively; The error prevention lockout control circuit is used to determine the initial delay duration of the voltage-controlled delay line based on multiple delayed clock signals with equal phase differences, and output a lockout adjustment signal based on the relationship between the initial delay duration and the effective delay range; The phase detector is used to output the phase difference signal based on the phase comparison result between the target clock signal and the input clock signal, and the locking adjustment signal. Wherein, when the phase of the target clock signal output by the voltage-controlled delay line within the effective delay range is equal to that of the input clock signal, the target clock signal is delayed by one clock cycle compared to the input clock signal.

6. The DLL circuit according to claim 5, characterized in that, The DLL circuit further includes: a switch selection circuit; the switch selection circuit is connected to the voltage-controlled delay line and the error-proof lockout control circuit. The switch selection circuit is used to receive the delayed clock signal of each of the delayed clock signals and output a plurality of the delayed clock signals with equal phase differences to the error prevention lock control circuit; The switch selection circuit is also used to receive a selection signal and output the delayed clock signal corresponding to the selection signal from the received plurality of delayed clock signals.

7. The DLL circuit according to claim 1, characterized in that, The charge pump unit includes a charge pump and a ring filter; the charge pump is connected to the phase detector and the ring filter respectively, and the ring filter is also connected to the voltage-controlled delay line; The charge pump is used to output a control current signal based on the phase difference signal; The ring filter is used to convert the control current signal into the control voltage signal and output the control voltage signal.

8. A control method for a delay-locked loop (DLL) circuit, characterized in that, Applied to the DLL circuit according to any one of claims 1 to 7, the method comprises: Control the operation of the ring oscillator; If the frequency of the oscillation signal output by the ring oscillator does not meet the target frequency, the load capacitance of the second delay unit is adjusted. The target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line. The first ratio is the ratio of the number of the second delay units to the number of the first delay units. When the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the ring oscillator is controlled to stop working, and the load capacitances of the first delay unit and the second delay unit are controlled to be equal. The input clock signal is delayed by the multiple cascaded first delay units to obtain the target clock signal; The phase detector compares the phase of the target clock signal and the input clock signal. If, based on the phase comparison result, it is determined that the delay of the target clock signal relative to the input clock signal is less than one clock cycle, the delay duration of the first delay unit is adjusted by the charge pump unit, and the input clock signal is delayed again by the first delay unit until the delay of the target clock signal relative to the input clock signal satisfies one clock cycle.

9. The method according to claim 8, characterized in that, The load capacitor includes a capacitor array; adjusting the size of the load capacitor of the second delay unit includes: Based on the number of capacitors in the capacitor array, the number of capacitors in the second delay unit that are in operation is adjusted using a binary search method.

10. An electronic device, characterized in that, The electronic device includes the delay phase-locked loop (DLL) circuit as described in any one of claims 1 to 7.

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