A 400G Ethernet traffic test system based on FPGA

Abstract

The present application relates to a 400G Ethernet traffic test system based on FPGA, which relates to the field of data communication technology, including a CPU module, a sending FPGA module, a statistics FPGA module and an optical module; the sending FPGA and the statistics FPGA are both connected to the CPU module through a PCIe interface, and the statistics FPGA module and the optical module are both connected to the sending FPGA module through a 400G communication interface; the CPU module is used to send communication protocol messages and configuration messages; the statistics FPGA receives the configuration message, generates configuration information according to the configuration message, and sends the configuration information to the sending FPGA module; the sending FPGA receives and parses the communication protocol message, generates flow information according to the protocol message and the configuration information, and sends the flow information to the optical module, so that the optical module generates an optical signal according to the flow information and sends it to the device under test. The present application is based on the CPU+FPGA architecture, builds a dual FPGA module, realizes separate processing of sending and statistical traffic, and the sending FPGA module and the statistics FPGA module are connected and communicated through a 400G communication interface to realize efficient transmission of information.

Description

[0001] This application is a divisional application of the application filed on July 10, 2023, with application number 202310838902.1 and invention name “A 400G Ethernet traffic testing device based on FPGA”. Technical Field

[0002] The present application relates to the field of data communication technology, and in particular to a 400G Ethernet traffic testing system based on FPGA. Background Art

[0003] Ethernet traffic testing devices are generally implemented using a CPU + DPDK + network card approach. The CPU system is generally oriented towards general-purpose computing. The current mainstream memory system is the DDR4 memory system, which has the disadvantages of large bandwidth but also large access latency. Due to different read and write access modes, there may be delay jitter during operation. In addition, the reference clock accuracy itself is not high, and it is impossible to implement long-term flow of small byte packets on high-speed ports, and thus cannot achieve accurate traffic scheduling. Summary of the Invention

[0004] In order to solve the above technical problems, the present application provides a 400G Ethernet traffic testing system based on FPGA.

[0005] The FPGA-based 400G Ethernet traffic testing system provided in this application adopts the following technical solutions:

[0006] An FPGA-based 400G Ethernet traffic test system includes a CPU module, a transmission FPGA module, a statistics FPGA module, and an optical module;

[0007] The sending FPGA and the statistics FPGA are both connected to the CPU module through a PCIe interface, and the statistics FPGA module and the optical module are both connected to the sending FPGA module through a 400G communication interface;

[0008] The CPU module is used to send communication protocol messages and configuration messages;

[0009] The statistical FPGA receives the configuration message, generates configuration information according to the configuration message, and sends the configuration information to the sending FPGA module;

[0010] The sending FPGA receives and parses the communication protocol message, generates flow information according to the protocol message and configuration information, and sends the flow information to the optical module, so that the optical module generates an optical signal according to the flow information and sends it to the device under test.

[0011] Optionally, the configuration information includes at least the sending traffic rate, the number of sending traffic frames, the sending traffic frame length, the number of sending traffic bytes and the traffic sending mode.

[0012] Optionally, the sending FPGA and the statistical FPGA are further connected via a 100G communication interface;

[0013] The sending FPGA module is also used to receive the traffic protocol message sent by the optical module, and transmit the traffic protocol message to the statistical FPGA module through the 400G communication interface. The statistical FPGA module parses the traffic protocol message to extract traffic information, and sends the traffic information to the sending FPGA module through the 100G communication interface. The sending FPGA module sends the traffic information to the CPU module.

[0014] Optionally, the sending FPGA is also used to parse the traffic protocol message to generate port statistical information, and send the port statistical information to the statistical FPGA module through the 100G communication interface, and the statistical FPGA module sends the port statistical information to the CPU module.

[0015] Optionally, the port statistical information includes at least one or more of the received traffic rate, received traffic frame number, received traffic frame length, received traffic byte number, sent packet type statistics, received protocol frame statistics, received error frame statistics, and received special frame statistics.

[0016] Optionally, a control FPGA module is also included, and the control FPGA module is connected to the sending FPGA module, the statistical FPGA module and the optical module through an IIC communication interface.

[0017] Optionally, the sending FPGA module is externally connected to multiple groups of first DDR4 particles, and the sending FPGA module is further used to parse the description information in the traffic protocol message and store the description information in the first DDR4 particles.

[0018] Optionally, the statistical FPGA is externally connected to a group of second DDR4 particles, and the statistical FPGA is further used to capture data statistical information in the port statistical information and store the data statistical information in the second DDR4 particles.

[0019] Optionally, an operation and maintenance management module is further included, which is used to control the resetting of the CPU module, control the power on and power off of the test device, and monitor the temperature and voltage of a specified location.

[0020] Optionally, the communication interface of the optical module is an optical transceiver in the form of a QSFP-DD interface.

[0021] The present application discloses an FPGA-based 400G Ethernet traffic testing system, in which the statistical FPGA receives the configuration message, generates configuration information according to the configuration message, and sends the configuration information to the FPGA module; the sending FPGA receives and parses the communication protocol message, generates flow information according to the protocol message and the configuration information, and sends the flow information to the optical module, so that the optical module generates an optical signal according to the flow information and sends it to the device under test, thereby realizing separate processing of sending and statistical traffic. Based on the CPU+FPGA architecture, a dual FPGA module is built, and the sending FPGA module and the statistical FPGA module are connected to communicate through a 400G communication interface to realize efficient transmission of information. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a structural diagram of an FPGA-based 400G Ethernet traffic testing system in an embodiment of the present application.

[0023] Explanation of the accompanying symbols: 1. CPU module; 2. Sending FPGA module; 3. Statistics FPGA module; 4. Optical module; 5. Control FPGA module; 6. First DDR particle; 7. Second DDR particle; 8. QDR particle; 9. Operation and maintenance management module. DETAILED DESCRIPTION

[0024] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure. In addition, techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values should be interpreted as being merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0025] This application discloses a 400G Ethernet traffic testing system based on FPGA. Figure 1 The device includes a CPU module 1, a transmitting FPGA module 2, a statistical FPGA module 3, and an optical module 4. The transmitting FPGA and the statistical FPGA are both connected to the CPU module 1 via a PCIe interface, and the statistical FPGA module 3 and the optical module 4 are both connected to the transmitting FPGA module 2 via a 400G communication interface. The optical module 4 can be connected to an external device under test, converting the electrical signal sent by the transmitting FPGA module 2 into an optical signal and sending it to the device under test. It can also convert the optical signal sent by the device under test into an electrical signal and send it to the transmitting FPGA module 2, so as to realize data interaction between the test device of this application and the external device under test.

[0026] In the embodiment of the present application, a control FPGA module 5 is also included. The control FPGA module 5 communicates with the sending FPGA module 2, the statistics FPGA module 3 and the optical module 4 through the IIC communication interface. The control FPGA module 5 can control the loading of the sending FPGA module 2 and the statistics FPGA module 3. Specifically, it can be loaded in the SelectMAP manner. The control FPGA module 5 is connected to the CPU module 1 through the PCIe interface. The control FPGA module 5 can monitor the chip status of the sending FPGA module 2 and the statistics FPGA module 3, and when the chip status of the sending FPGA module 2 or the statistics FPGA module 3 is abnormal, an alarm message is generated and sent to the CPU module 1, so that the CPU module 1 can take corresponding actions according to the alarm message. The above-mentioned chip status can be reflected from the chip temperature and general processing information.

[0027] The control FPGA module 5 can monitor, control, and read information from the optical module 4. Specifically, the control FPGA module 5 can monitor the optical power, operating temperature, operating voltage, interface status, presence, interruption, and other information of the optical module 4. The control FPGA module 5 can also control the reset, operating mode, and control interface of the optical module 4. All registers of the optical module 4 can be read at any time, and the control FPGA module 5 can read the registers to obtain required information such as the status and internal configuration information of the optical module 4.

[0028] Different from traditional Ethernet traffic testing devices, this application is based on the CPU+FPGA architecture, is equipped with multiple FPGA modules, and performs efficient data transmission through the 400G interface between the sending FPGA module 2 and the statistical FPGA module 3, realizing high-performance business processing and fast and accurate processing of 400G traffic transmission and reception and statistical parameters.

[0029] In the embodiment of the present application, the process of sending 400G traffic is as follows:

[0030] CPU module 1 sends configuration messages to statistics FPGA module 3 and communication protocol messages to transmission FPGA module 2 via the PCIe interface. After receiving the configuration messages, statistics FPGA module 3 parses them and generates configuration information, which it then sends to transmission FPGA module 2. Transmission FPGA module 2 receives the protocol messages and configuration information, generates flow information based on them, and sends this flow information to optical module 4, which then generates an optical signal based on the flow information and sends it to the device under test.

[0031] In a specific example, the communication protocol message is an Ethernet general protocol message, and the communication protocol message may include standard test items such as RFC2544, RFC2889, and RFC3918, 4-7 layer application protocols: data protocols (HTTP, FTP, Unicast / Multicast RTSP, RAWTCP, VXLAN, OpenFlow, OVSDB), voice protocols (SIP, SIP overUDP), video protocols (RTSP / RTP, Multicast streaming, IGMPv2, IGMPv3, MLDv2), link or access protocols: ANCP, PPPoE, DHCP, L2TP, IGMPv1 / v2 / v3, MLDv1 / v2, DHCPv6 and PPPoEv6, 802.1x, LACP, routing or multicast protocols: BGP, IS-IS, OSPF, RIP, MPLS, IGMPv1 / v2 / v3, MLDv1 / v2, IGMP / MLD Querier, PIM-SM, encapsulation protocols: 802.1Q and 802.1Q-in-Q, transport protocols: TCP, UDP, supported IP versions: IPv4 / IPv6, etc.

[0032] Configuration information contains basic information about the flow, including at least the sending rate, number of sending frames, sending frame length, number of sending bytes, and the sending mode. The sending mode can include continuous sending, burst sending, scheduled sending, and step sending.

[0033] The sending FPGA module 2 can form flow information based on the protocol information obtained by parsing the protocol message and the received configuration information, and send it to the optical module 4 through the 400G communication interface.

[0034] In the embodiment of the present application, the 400G traffic receiving process is as follows:

[0035] The sending FPGA module 2 receives the traffic protocol message sent by the optical module 4, and transmits the traffic protocol message to the statistical FPGA module 3 through the 400G communication interface. The statistical FPGA module 3 parses the traffic protocol message to extract the traffic information, and sends the traffic information to the sending FPGA module 2 through the 100G communication interface. The sending FPGA module 2 then sends the traffic information to the CPU module 1.

[0036] The sending module can also parse the received traffic protocol messages, generate port statistical information, and send the port statistical information to the statistical FPGA module 3 through the 100G communication interface. The statistical FPGA module 3 then sends the port statistical information to the CPU module 1.

[0037] The port statistics include at least one or more of the following: received traffic rate, received traffic frame number, received traffic frame length, received traffic byte number, sent packet type statistics, received protocol frame statistics, received error frame statistics, and received special frame statistics. The sent packet type may include the total number of IPv4 frames, the total number of IPv6 frames, the total number of IPv4 flow frames, and the total number of IPv6 flow frames.

[0038] In an embodiment of the present application, the sending FPGA module 2 is externally connected to multiple groups of first DDR4 particles. When parsing the traffic protocol message, the sending FPGA module 2 can obtain the description information in the traffic protocol message and store the description information in the first DDR4 particle.

[0039] Specifically, the sending FPGA module 2 may be externally equipped with three groups of DDR4*5 particles, the capacity of a single DDR4 particle is 8Gbit, and the access rate is 2666MT / S.

[0040] The statistical FPGA module 3 is externally connected to a group of second DDR4 particles. After receiving the port statistical information, the statistical FPGA can capture the data statistical information in the port statistical information and store the data statistical information in the second DDR4 particles.

[0041] The statistics FPGA module 3 also has an external QDR4 particle. The statistics FPGA can perform statistics on flow information. The statistical content includes but is not limited to the flow information's sending flow rate, sending flow frame number, sending flow frame length, sending flow byte number and flow sending mode.

[0042] In the embodiment of the present application, an operation and maintenance management module 9 is also included. The operation and maintenance management module 9 can control the reset, power-on and power-off of the test device of the present application, and is also used to monitor the temperature and voltage of the present application.

[0043] In a specific example, the present application includes a power supply module and a temperature sensor set at a specified position. The operation and maintenance management module 9 is connected to the power supply module, the temperature sensor and the CPU module 1. When a reset signal is received, the operation and maintenance management module 9 can output a control signal to the CPU module 1, so that the control signal acts on the reset pin of the CPU module 1 to reset the CPU module 1. The operation and maintenance management module 9 can also output a power-on drive signal to the power supply module after receiving a power-on signal, so that the power supply module can power the test device. Correspondingly, after receiving a power-off signal, the operation and maintenance management module 9 outputs a power-off drive signal to the power supply module to achieve power-off.

[0044] The power supply module is also connected to a voltage detection module, which can output the voltage signals output by the power supply module to each module to the operation and maintenance management module 9. The operation and maintenance management module 9 can monitor each voltage and issue an alarm signal when the voltage signal exceeds the voltage threshold to realize voltage monitoring.

[0045] The temperature sensor can be set according to needs. In the embodiment of the present application, temperature sensors can be set on the CPU module 1, the sending FPGA module 2, the statistical FPGA module 3, the control FPGA module 5 and the optical module 4. The temperature sensor outputs the detected temperature signal to the operation and maintenance management module 9. The operation and maintenance management module 9 sends an alarm signal when any temperature signal exceeds the temperature threshold to realize temperature monitoring.

[0046] It should be noted that the PCIe interface bandwidth between the CPU module 1 and the control module is greater than or equal to 5Gbps in both directions, and the PCIe interface bandwidth between the CPU module 1 and the statistical FPGA is greater than or equal to 128Gbps in both directions, to meet the requirements of sending communication protocol messages and configuration messages, and sending traffic information and port statistical information.

[0047] The test device provided in this application integrates 400Gbps, 200Gbps, 100Gbps and 50Gbps Ethernet test ports. The test ports can be connected to different test equipment, thereby improving the adaptability of this application.

[0048] The present application discloses an FPGA-based 400G Ethernet traffic testing system, which is based on a CPU+FPGA infrastructure and is provided with a CPU module 1, a sending FPGA module 2, a statistical FPGA module 3, a control FPGA module 5 and an optical module 4. During the sending and receiving process of 400G traffic, separate processing of the receiving and sending traffic and the statistical traffic is achieved, and the sending FPGA module 2 and the statistical FPGA module 3 are used to transmit unused data respectively through the 400G communication interface and the 100G communication interface, thereby achieving efficient data transmission and improving the information processing capability of the present application as a whole.

[0049] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A 400G Ethernet traffic testing system based on FPGA, characterized in that: It includes a CPU module (1), a sending FPGA module (2), a statistics FPGA module (3) and an optical module (4); The transmitting FPGA module (2) and the statistical FPGA module (3) are both connected to the CPU module (1) via a PCIe interface, and the statistical FPGA module (3) and the optical module (4) are both connected to the transmitting FPGA module (2) via a 400G communication interface; The CPU module (1) is used to send communication protocol messages and configuration messages; The statistical FPGA module (3) receives the configuration message, generates configuration information according to the configuration message, and sends the configuration information to the sending FPGA module (2); The sending FPGA module (2) receives and parses the communication protocol message, generates flow information according to the communication protocol message and configuration information, and sends the flow information to the optical module (4), so that the optical module (4) generates an optical signal according to the flow information and sends it to the device under test; The sending FPGA module (2) and the statistical FPGA module (3) are also connected via a 100G communication interface; The sending FPGA module (2) is further used to receive the flow protocol message sent by the optical module (4), and transparently transmit the flow protocol message to the statistics FPGA module (3) through the 400G communication interface. The statistics FPGA module (3) parses the flow protocol message to extract flow information, and sends the flow information to the sending FPGA module (2) through the 100G communication interface. The sending FPGA module (2) sends the flow information to the CPU module (1). The sending FPGA module (2) is further used to parse the traffic protocol message to generate port statistical information, and send the port statistical information to the statistical FPGA module (3) through the 100G communication interface, and the statistical FPGA module (3) sends the port statistical information to the CPU module (1); It also includes an operation and maintenance management module (9), which is used to control the resetting of the CPU module (1), control the power on and off of the system, and monitor the temperature and voltage of a specified location; The communication interface of the optical module (4) is an optical transceiver in the form of a QSFP-DD interface.

2. The FPGA-based 400G Ethernet traffic testing system according to claim 1, characterized in that: The configuration information includes at least the sending traffic rate, the number of sending traffic frames, the sending traffic frame length, the number of sending traffic bytes and the traffic sending mode.

3. The FPGA-based 400G Ethernet traffic testing system according to claim 1, characterized in that: The port statistical information includes at least one or more of the following: received traffic rate, received traffic frame number, received traffic frame length, received traffic byte number, sent packet type statistics, received protocol frame statistics, received error frame statistics, and received special frame statistics.

4. The FPGA-based 400G Ethernet traffic testing system according to claim 1, wherein: It also includes a control FPGA module (5), and the control FPGA module (5) is connected to the sending FPGA module (2), the statistics FPGA module (3), and the optical module (4) via an IIC communication interface.

5. The FPGA-based 400G Ethernet traffic testing system according to claim 1, characterized in that: The sending FPGA module (2) is externally connected to multiple groups of first DDR4 particles. The sending FPGA module (2) is also used to parse the description information in the traffic protocol message and store the description information in the first DDR4 particles.

6. The FPGA-based 400G Ethernet traffic testing system according to claim 1, characterized in that: The statistical FPGA module (3) is externally connected to a group of second DDR4 particles. The statistical FPGA module (3) is also used to capture data statistical information in the port statistical information and store the data statistical information in the second DDR4 particles.

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