FPGA-based adaptive shifting long cable harmonic suppression method and deployment method

Abstract

The present invention relates to the field of oil and gas development technology, and provides an FPGA-based adaptive shifting method and deployment method for harmonic suppression in long cables. The harmonic suppression method includes constructing a power-weighted adaptive shifting filter; obtaining inverter output data and power coefficients of a submersible motor, and calculating the filter output of the power-weighted adaptive shifting filter; calculating an error sequence and constructing a root mean square error criterion, using the root mean square error criterion to find the gradient of the power coefficient and update the power coefficient; calculating an adaptive threshold; and adjusting the power coefficient according to the adaptive threshold and adjusting the filter output of the power-weighted adaptive shifting filter to achieve harmonic suppression in long cables. The present invention reduces the computational complexity of the filter output while improving harmonic suppression performance by adaptively adjusting the power coefficient and combining it with a multi-channel parallel FPGA architecture, thereby solving the problems of high harmonic content, long processing delay, and high cost in long cable systems.

Description

Technical Field

[0001] The present invention relates to the technical field of oil and gas development, and in particular to an FPGA-based adaptive shifting long cable harmonic suppression method and a deployment method. Background Art

[0002] During oilfield production, as the depth of extraction gradually increases, the high-frequency PWM waves output by the inverters that control submersible motors contain a large number of harmonic components. After transmission over long cables, the resonance is gradually amplified, causing power quality to deteriorate and affecting the operating efficiency of the submersible motors. As a result, long-distance cable systems suffer from high harmonic content, long processing delays, and high costs.

[0003] The main existing methods for harmonic removal in downhole submersible pumps include LC filtering, active power filtering, harmonic isolation transformers, and multi-pulse rectifier transformers. LC filtering uses a combination of inductors and capacitors, or series compensation, to suppress harmonics, but is costly, bulky, and has limited effectiveness. Active power filtering uses adaptive harmonic detection based on the Kalman algorithm, and active harmonic control based on deep neural networks or genetic optimization. However, these methods are complex, lack real-time performance, and have significant limitations in engineering implementation. Harmonic isolation transformers reduce harmonic transmission by altering the current path. They typically employ independent windings, closed magnetic circuits, or specialized shielding structures to prevent load-generated harmonics from transmitting through the transformer to the grid. While suitable for applications with high-harmonic pollution, they have limited filtering effectiveness against low-frequency harmonics. Multi-pulse rectifier transformers, such as those used in 12-pulse, 18-pulse, or 24-pulse inverters, increase the number of rectifier phases to increase the minimum harmonic order and reduce the amplitude of harmonic currents, thereby reducing harmonic generation. Summary of the Invention

[0004] The present invention aims to address at least one of the technical problems existing in the related art. To this end, it provides an FPGA (field programmable gate array)-based adaptive shifting method and deployment method for long cable harmonic suppression. This method dynamically optimizes filter coefficients by constructing a power-weighted structure and introducing adaptive threshold criteria for error mean and variance. Combined with a multi-channel parallel FPGA architecture, this method reduces computational complexity while improving harmonic suppression performance, addressing the issues of high harmonic content, long processing delays, and high costs in long cable systems.

[0005] The present invention provides an FPGA-based adaptive shifting long cable harmonic suppression method, comprising:

[0006] S1: Construct a power weight adaptive shift filter;

[0007] S2: obtaining a power coefficient of a power weight adaptive shift filter and inverter output data of a submersible motor, and calculating a filter output of the power weight adaptive shift filter according to the power coefficient and the inverter output data of the submersible motor;

[0008] S3: Calculate the error sequence based on the filter output and the inverter output data of the submersible motor;

[0009] S4: Construct an error root mean square criterion based on the error sequence, and use the error root mean square criterion to calculate the gradient of the power coefficient and update the power coefficient;

[0010] S5: Calculate the error mean and variance according to the error sequence, and calculate the adaptive threshold according to the error mean and variance;

[0011] S6: adjusting the power coefficient according to the adaptive threshold and adjusting the filtering output of the power weight adaptive shift filter according to the adjusted power coefficient to achieve harmonic suppression of the long cable.

[0012] Furthermore, in step S1, the calculation expression of the power weight adaptive shift filter is:

[0013] ;

[0014] in, is a power weight adaptive shift filter, is the filter order, is the filter weight, For the The power coefficients of the filter order, is a complex variable, is a plural set.

[0015] Furthermore, in step S2, the inverter output data of the submersible motor is used as the input data of the power weight adaptive shift filter. The calculation expression of the filter output of the power weight adaptive shift filter is:

[0016] ;

[0017] in, For the The filtered output of the power-shifted weighted adaptive shift filter, For the Second shift The input sequence of the filter is is a set of integers.

[0018] Furthermore, in step S3, the calculation expression of the error sequence is:

[0019] ;

[0020] in, For the The error sequence of times shift, For the times shifted input sequence, is the filter order, is the filter weight, For the The power coefficients of the filter order, For the Second shift The input sequence of the filter.

[0021] Furthermore, the calculation expression of the root mean square error criterion is:

[0022] ;

[0023] in, is the root mean square error criterion, To find the mean function, For the shift the input sequence, is the filter order, is the filter weight, For the The power coefficients of the filter order, For the Second shift The input sequence of the filter.

[0024] Furthermore, the error root mean square criterion is used to find the gradient of the power coefficient and update the power coefficient. The calculation expression for the power coefficient update is:

[0025] ;

[0026] in, After the update The power coefficient, Before the update The power coefficient, is the compensation factor, For the The error sequence of times shift, For the Second shift The input sequence of the filter is is a symbolic function.

[0027] Furthermore, in step S5, the calculation expression of the adaptive threshold is:

[0028] ;

[0029] in, For the The adaptive threshold of the shift, is the first forgetting factor, is the second forgetting factor, For the The adaptive threshold of the shift, For the The mean error of the shift, is the confidence coefficient, For the The standard deviation of the error of the shift, For the The mean error of the shift, For the The error sequence of times shift, No. The standard deviation of the error per shift.

[0030] Furthermore, in step S6,

[0031]

[0032] in, After the update The power coefficient, Before the update The power coefficient, For the The error sequence of times shift, For the Adaptive threshold for sub-shift.

[0033] The present invention also provides a deployment method for deploying the above-mentioned FPGA-based adaptive shifting long cable harmonic suppression method on a multi-channel parallel FPGA architecture, comprising the following steps:

[0034] S100: Selecting a system clock frequency, where the system clock frequency is determined by the well depth;

[0035] S200: Determine resource usage of the input signal buffer module, the parameter storage module, and the adaptive filtering module according to the filter length, the data bit width, and the system clock;

[0036] S300: The power weight adaptive shift filter adopts a two-stage pipeline structure. The first stage pipeline structure is used to process the reading of power coefficients and the shift accumulation operation of data. The second stage pipeline structure is used for adaptive update of power coefficients.

[0037] S400: performing cross error calculation on the filtering results of each channel of the power weight adaptive shift filter to obtain multiple errors, and performing weighted combination on the multiple errors;

[0038] The error between the filtered outputs of multiple parallel channels and the same reference signal is calculated, and the multiple errors are weighted and combined. The calculation expression is:

[0039] ;

[0040] in, is the cross error, is the number of parallel channels, For the The weight coefficient of each channel, For the times shifted input sequence, For the Channel No. The filtered output of the shifted power weight adaptive shifted filter;

[0041] S500: performing weighted averaging on the filtering results of multiple parallel channels.

[0042] Furthermore, the multi-channel parallel FPGA architecture includes:

[0043] An input signal buffer module, which is a 20×16-bit FIFO shift register for storing the inverter output data of the submersible motor;

[0044] A parameter storage module for storing power coefficients;

[0045] The adaptive filtering module includes a power weight adaptive shift filter, which is a cascade of 20 16-bit shift adders for calculating the filter output of the power weight adaptive shift filter and adjusting the power coefficient.

[0046] The above one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:

[0047] The present invention reduces computational complexity while improving harmonic suppression performance by adaptively adjusting power coefficients and combining a multi-channel parallel FPGA architecture, thus solving the problems of high harmonic content, long processing delay, and high cost in long-line cable systems.

[0048] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 The present invention provides a flow chart of an FPGA-based adaptive shifting long cable harmonic suppression method.

[0051] Figure 2 It is a flow chart of a deployment method provided by the present invention.

[0052] Figure 3 This is a timing relationship diagram between key signals when the present invention uses FPGA parallel architecture data transmission.

[0053] Figure 4 Schematic diagram of voltage waveforms before and after long cable harmonic filtering according to an embodiment of the present invention.

[0054] Figure 5 It is a schematic diagram of the changes in harmonic components of long cable harmonics in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] To make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The following embodiments are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0056] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0057] The following combination Figures 1 to 5The present invention describes an FPGA-based adaptive shifting long cable harmonic suppression method and deployment method.

[0058] like Figure 1 As shown, an FPGA-based adaptive shifting long cable harmonic suppression method includes:

[0059] S1: Construct a power weight adaptive shift filter;

[0060] The calculation expression of the power weight adaptive shift filter is:

[0061] ;

[0062] in, is a power weight adaptive shift filter, is the filter order, is the filter weight, For the The power coefficients of the filter order, is a complex variable, is a plural set.

[0063] S2: obtaining a power coefficient of a power weight adaptive shift filter and inverter output data of a submersible motor, and calculating a filter output of the power weight adaptive shift filter according to the power coefficient and the inverter output data of the submersible motor;

[0064] The inverter output data of the submersible motor is used as the input data of the power weight adaptive shift filter. The calculation expression of the filter output of the power weight adaptive shift filter is:

[0065] ;

[0066] in, For the The filtered output of the power-shifted weighted adaptive shift filter, For the Second shift The input sequence of the filter is is a set of integers.

[0067] The output data of the submersible motor's frequency converter is stored through a shift storage module, which includes N-stage B-bit shift registers connected in series; the power coefficient is stored through a parameter storage module; the filter output is obtained by calculating the power weight adaptive shift filter; through N-stage parallel B-bit shift accumulation, each stage accumulates , and then perform cascade summation to obtain the filtered output.

[0068] The standard FIR filter is:

[0069] ;

[0070] in, is the transfer function of the standard FIR filter, For the standard FIR filter Order input, standard FIR filter uses floating-point multiplication operation.

[0071] The present invention simplifies the floating-point multiplication operation in the standard FIR filter into an integer power shift operation, greatly reducing the computational complexity and saving computational resources.

[0072] S3: Calculate the error sequence based on the filter output and the inverter output data of the submersible motor;

[0073] The calculation expression of the error sequence is:

[0074] ;

[0075] in, For the The error sequence of times shift, For the times shifted input sequence, is the filter order, is the filter weight, For the The power coefficients of the filter order, For the Second shift The input sequence of the filter.

[0076] S4: Construct an error root mean square criterion based on the error sequence, and use the error root mean square criterion to calculate the gradient of the power coefficient and update the power coefficient;

[0077] The calculation expression of the root mean square error criterion is:

[0078] ;

[0079] in, is the root mean square error criterion, To find the mean function, For the times shifted input sequence, is the filter order, is the filter weight, For the The power coefficients of the filter order, For the Second shift The input sequence of the filter.

[0080] The error root mean square criterion is used to find the gradient of the power coefficient, and the calculation expression for updating the power coefficient is:

[0081]

[0082] in, After the update The power coefficient, Before the update The power coefficient, is the compensation factor, For the The error sequence of times shift, For the Second shift The input sequence of the filter is is a symbolic function.

[0083] In some specific embodiments of the present invention, the value range of is (0, 1), which is used to control the convergence speed.

[0084] S5: Calculate the error mean and variance according to the error sequence, and calculate the adaptive threshold according to the error mean and variance;

[0085] The calculation expression of the adaptive threshold is:

[0086] ;

[0087] in, For the The adaptive threshold of the shift, is the first forgetting factor, is the second forgetting factor, For the The adaptive threshold of the shift, For the The mean error of the shift, is the confidence coefficient, For the The standard deviation of the error of the shift, For the The mean error of the shift, For the The error sequence of times shift, For the The standard deviation of the error per shift.

[0088] In some specific embodiments of the present invention, and The value range is (0,1). The value is (2,3), the first forgetting factor , the second forgetting factor It is related to the depth of the submersible pump and the harmonic content, and is a constant less than 1; the confidence coefficient It is related to the system noise characteristics and error propagation, and its initial range is between 2 and 3. After a lot of simulation analysis and combined with actual working conditions, when the electric submersible pump is inserted into the depth of 500m to 3000m and the harmonic content is between 5% and 25%, 、 The optimal value is 0.995. The optimal value of is about 2.8;

[0089] Practical application tests at different well sites have shown that the above parameters can adapt to the actual operating conditions of most oil wells and meet the electric submersible pump installation depth and development requirements of various domestic oil fields. During actual deployment, they can be fine-tuned within a range of ±5% based on the specific working conditions on site.

[0090] The iterative formula for the error mean is:

[0091] ;

[0092] The iterative formula for error variance is:

[0093] ;

[0094] The calculation expression of the adaptive threshold is:

[0095] ;

[0096] S6: adjusting the power coefficient according to the adaptive threshold and adjusting the filter output of the power weight adaptive shift filter according to the adjusted power coefficient to achieve harmonic suppression of long cables;

[0097] ;

[0098] in, After the update The power coefficient, Before the update The power coefficient, For the The error sequence of times shift, For the Adaptive threshold for sub-shift.

[0099] like Figure 2 As shown, a deployment method for deploying an FPGA-based adaptive shifting long cable harmonic suppression method on a multi-channel parallel FPGA architecture includes:

[0100] S100: Selecting a system clock frequency, where the system clock frequency is determined by the well depth;

[0101] In some specific embodiments of the present invention, the system clock frequency is 100 MHz to 500 MHz, which is suitable for well depths of 500 m to 3000 m.

[0102] S200: Determine resource usage of the input signal buffer module, the parameter storage module, and the adaptive filtering module according to the filter length, the data bit width, and the system clock;

[0103] S300: The power weight adaptive shift filter adopts a two-stage pipeline structure. The first stage pipeline structure is used to process the reading of power coefficients and the shift accumulation operation of data. The second stage pipeline structure is used for adaptive update of power coefficients.

[0104] The two-stage pipeline structure of the present invention establishes an independent data processing path for each parallel channel, and each channel performs shift operations, power calculations and filtering operations simultaneously.

[0105] S400: performing cross error calculation on the filtering results of each channel of the power weight adaptive shift filter to obtain multiple errors, and performing weighted combination on the multiple errors;

[0106] The error between the filtered outputs of multiple parallel channels and the same reference signal is calculated, and the multiple errors are weighted and combined. The calculation expression is:

[0107] ;

[0108] in, is the cross error, is the number of parallel channels, For the The weight coefficient of each channel, For the times shifted input sequence, For the Channel No. The filtered output of the shifted power weight adaptive shifted filter;

[0109] S500: performing weighted averaging on the filtering results of multiple parallel channels.

[0110] The robustness of the system can be effectively improved through reasonable distribution of weights.

[0111] Multi-channel parallel FPGA architecture includes:

[0112] An input signal buffer module, which is a 20×16-bit FIFO shift register for storing the inverter output data of the submersible motor;

[0113] Parameter storage module, used to store power coefficients,

[0114] The adaptive filtering module includes a power weight adaptive shift filter, which is a cascade of 20 16-bit shift adders for calculating the filter output of the power weight adaptive shift filter and adjusting the power coefficient.

[0115] The submersible motor drive system of an oil field has a known well depth of 2500 meters. The motor rated power is 160kW, the rated voltage is 690V, the inverter switching frequency is 4kHz, and the dead time is , using FPJP-3*95mm 2 According to the measured data on the well, the 5th harmonic component in each phase voltage of the cable is as high as 20% of the fundamental component, the 7th harmonic component is as high as 15% of the fundamental component, the 11th harmonic component is as high as 8% of the fundamental component, and the 13th harmonic component is as high as 4% of the fundamental component, causing a serious deterioration of the system power factor and power quality.

[0116] According to the actual working conditions, the filter order N=20, the quantization bit width B=16, and the system clock frequency are selected. At the same time, based on a large number of experiments and expert experience, the compensation factor in the adaptive filter , in the weight update step, , .

[0117] Algorithm hardware deployment: The input signal buffer module uses a 20×16-bit FIFO shift register to store the input voltage signal sequence. ; The parameter storage module size is 20×4, used to store the corresponding power coefficients The adaptive filter module is composed of 20 16-bit shift adders in cascade to calculate the filter output. :

[0118] ;

[0119] Calculate the error signal:

[0120] ;

[0121] The iterative formula for the error mean is:

[0122] ;

[0123] The iterative formula for error variance is:

[0124] ;

[0125] The calculation expression of the adaptive threshold is:

[0126] ;

[0127] The power coefficients are dynamically updated, and the filter output of the power weight adaptive shift filter is calculated based on the updated power coefficients.

[0128] like Figure 3 The figure shows the timing relationship between key signals when using the FPGA parallel architecture for data transmission. The master clock (CLK) frequency has a 50% duty cycle. On the rising edge of the master clock, the enable signal (EN) is activated, and the data signal (DATA) then remains stable after the setup time. The update signal (UPDATE) is triggered on the next clock cycle after the data stabilizes, controlling the update timing of the weight parameters.

[0129] like Figure 4 Figure (a) shows the voltage waveform before filtering. Figure 4 Figure (b) shows the voltage waveform after being processed by a 20th-order adaptive shift filter. Figure 4 As shown in the figure, the voltage waveform distortion is significantly improved after processing, and the waveform is close to a sine curve.

[0130] like Figure 5 As shown in the figure, the changes of each harmonic component are quantitatively analyzed. After filtering, the 5th harmonic content is reduced from 16% to 3%, the 7th harmonic is reduced from 12% to 2%, the 11th harmonic is reduced from 7% to 1%, and the 13th harmonic is reduced from 4% to 0.6%. The harmonic suppression effect is significant.

[0131] The LC passive filter, FIR digital filter and the present invention are used to filter the harmonic data of the same long cable. The comprehensive performance indicators of different filters are shown in Table 1.

[0132] Table 1 Comprehensive performance indicators of different filters

[0133]

[0134] The present invention realizes dynamic optimization of filter coefficients by constructing a power weight structure and introducing adaptive threshold criteria for error mean and variance. Combined with a multi-channel parallel FPGA architecture, it reduces computational complexity while improving harmonic suppression performance, solving the problems of high harmonic content, long processing delay, and high cost in long-line cable systems.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An FPGA-based adaptive shifting long cable harmonic suppression method, characterized in that: include: S1: Construct a power weight adaptive shift filter; S2: obtaining a power coefficient of a power weight adaptive shift filter and inverter output data of a submersible motor, and calculating a filter output of the power weight adaptive shift filter according to the power coefficient and the inverter output data of the submersible motor; S3: Calculate the error sequence based on the filter output and the inverter output data of the submersible motor; S4: Construct an error root mean square criterion based on the error sequence, and use the error root mean square criterion to calculate the gradient of the power coefficient and update the power coefficient; S5: Calculate the error mean and variance according to the error sequence, and calculate the adaptive threshold according to the error mean and variance; S6: adjusting the power coefficient according to the adaptive threshold and adjusting the filtering output of the power weight adaptive shift filter according to the adjusted power coefficient to achieve harmonic suppression of the long cable.

2. The FPGA-based adaptive shifting long cable harmonic suppression method according to claim 1 is characterized in that: In step S1, the calculation expression of the power weight adaptive shift filter is: ； in, is a power weight adaptive shift filter, is the filter order, is the filter weight, For the The power coefficients of the filter order, is a complex variable, is a plural set.

3. The FPGA-based adaptive shifting long cable harmonic suppression method according to claim 2 is characterized in that: In step S2, the inverter output data of the submersible motor is used as the input data of the power weight adaptive shift filter. The calculation expression of the filter output of the power weight adaptive shift filter is: ； in, For the The filtered output of the power-shifted weighted adaptive shift filter, For the Second shift The input sequence of the filter is is a set of integers.

4. The FPGA-based adaptive shifting long cable harmonic suppression method according to claim 1 is characterized in that: In step S3, the calculation expression of the error sequence is: ； in, For the The error sequence of times shift, For the times shifted input sequence, is the filter order, is the filter weight, For the The power coefficients of the filter order, For the Second shift The input sequence of the filter.

5. The FPGA-based adaptive shifting long cable harmonic suppression method according to claim 1, characterized in that: The calculation expression of the root mean square error criterion is: ； in, is the root mean square error criterion, To find the mean function, For the times shifted input sequence, is the filter order, is the filter weight, For the The power coefficients of the filter order, For the Second shift The input sequence of the filter.

6. The FPGA-based adaptive shifting long cable harmonic suppression method according to claim 5, characterized in that: The error root mean square criterion is used to find the gradient of the power coefficient and update the power coefficient. The calculation expression for the power coefficient update is: ； in, After the update The power coefficient, Before the update The power coefficient, is the compensation factor, For the The error sequence of times shift, For the Second shift The input sequence of the filter is is a symbolic function.

7. The FPGA-based adaptive shifting long cable harmonic suppression method according to claim 1, characterized in that: In step S5, the calculation expression of the adaptive threshold is: ； in, For the The adaptive threshold of the shift, is the first forgetting factor, is the second forgetting factor, For the The adaptive threshold of the shift, For the The mean error of the shift, is the confidence coefficient, For the The standard deviation of the error of the shift, For the The mean error of the shift, For the The error sequence of times shift, For the The standard deviation of the error per shift.

8. The FPGA-based adaptive shifting long cable harmonic suppression method according to claim 1, characterized in that: In step S6, ； in, After the update The power coefficient, Before the update The power coefficient, For the The error sequence of times shift, For the Adaptive threshold for sub-shift.

9. A deployment method, characterized in that: The method for deploying the FPGA-based adaptive shifting long cable harmonic suppression method according to any one of claims 1 to 8 on a multi-channel parallel FPGA architecture comprises the following steps: S100: Selecting a system clock frequency, where the system clock frequency is determined by the well depth; S200: Determine resource usage of the input signal buffer module, the parameter storage module, and the adaptive filtering module according to the filter length, the data bit width, and the system clock; S300: The power weight adaptive shift filter adopts a two-stage pipeline structure. The first stage pipeline structure is used to process the reading of power coefficients and the shift accumulation operation of data. The second stage pipeline structure is used for adaptive update of power coefficients. S400: performing cross error calculation on the filtering results of each channel of the power weight adaptive shift filter to obtain multiple errors, and performing weighted combination on the multiple errors; The error between the filtered outputs of multiple parallel channels and the same reference signal is calculated, and the multiple errors are weighted and combined. The calculation expression is: ； in, is the cross error, is the number of parallel channels, For the The weight coefficient of each channel, For the times shifted input sequence, For the Channel No. The filtered output of the shifted power weight adaptive shifted filter; S500: performing weighted averaging on the filtering results of multiple parallel channels.

10. A deployment method according to claim 9, characterized in that: Multi-channel parallel FPGA architecture includes: An input signal buffer module, which is a 20×16-bit FIFO shift register for storing the inverter output data of the submersible motor; A parameter storage module for storing power coefficients; The adaptive filtering module includes a power weight adaptive shift filter, which is a cascade of 20 16-bit shift adders for calculating the filter output of the power weight adaptive shift filter and adjusting the power coefficient.

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