Image output control device and method

Abstract

The invention discloses an image output control device. The image output control apparatus includes a storage device and a controller. The storage device sequentially stores a plurality of first input image frames corresponding to a first frame rate and a plurality of second input image frames corresponding to a second frame rate. The controller records an initial write-in position of the second input image frames in the storage device, and reads the first image frame and the second image frame from the storage device according to a read position. When the read position does not exceed the start write position, the controller reads the first and second image frames from the first input image frames of the storage device corresponding to the first frame rate. When the read position reaches or exceeds the start write position, the controller reads the first and second picture frames from the second input picture frames of the storage device corresponding to the second frame rate.

Description

Technical Field

[0001] The present application relates to image output with motion compensation, and more particularly to an image output control device and method suitable for variable frame rate. Background Art

[0002] In image processing applications, motion estimation and motion compensation (MEMC) technology can be used to generate an interpolated picture between two original pictures, making the image smoother. In multimedia content with Quick Media Switching (QMS) or variable frame rate, the frame rate of the video will switch dynamically, so how to control the image output after MEMC compensation is important. Summary of the invention

[0003] The present application provides an image output control device. The image output control device includes a storage device and a controller. The storage device is configured to sequentially store a plurality of first input frames corresponding to a first frame rate and a plurality of second input frames corresponding to a second frame rate in image data. The controller is configured to record the starting write position of the second input frames in the storage device, and provide a control signal to the storage device to set the reading position of the storage device so as to read the first frame and the second frame from the storage device. When the reading position of the storage device does not exceed the starting write position, the controller reads the first frame and the second frame from the first input frames stored in the storage device corresponding to the first frame rate. When the reading position of the storage device reaches or exceeds the starting write position, the controller reads the first frame and the second frame from the second input frames stored in the storage device corresponding to the second frame rate.

[0004] Furthermore, the present application provides an image output control method. The image output control method includes: writing image data to a storage device, wherein the image data includes a plurality of first input frames corresponding to a first frame rate and a plurality of second input frames corresponding to a second frame rate; when the written image data is transformed from the first input frames to the second input frames, recording the starting write position of the second input frames in the storage device; setting the read position of the storage device so as to read the first frame and the second frame from the storage device; when the read position of the storage device does not exceed the starting write position, reading the first input frames of the storage device corresponding to the first frame rate as the first frame and the second frame; and when the read position of the storage device reaches or exceeds the starting write position, reading the second input frames of the storage device corresponding to the second frame rate as the first frame and the second frame.

[0005] In summary, the content of the output image frame provided by the image output control device and method corresponds to the actual frame rate, and thus has better fluency. Therefore, the phenomenon of acceleration or deceleration of the image caused by frame drop or freeze during the transition period of frame rate conversion can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood when reading the following detailed description and the accompanying drawings. It should be noted that various features in the drawings are not drawn to scale, in accordance with standard operating practices in the art. In fact, the size of certain features may be deliberately enlarged or reduced in order to be clearly described.

[0007] Figure 1 Schematic diagram of an image output control device according to an embodiment of the present disclosure.

[0008] Figure 2 It is a schematic diagram of a storage device according to an embodiment of the present disclosure.

[0009] Figure 3 A schematic diagram of a controller according to an embodiment of the present disclosure.

[0010] Figure 4 The flowchart of an access control circuit reading a storage device when a frame rate is changed according to an embodiment of the present disclosure is shown.

[0011] Figure 5 The present invention is a flowchart of an image compensation circuit compensating a phase when a frame rate is converted according to an embodiment of the present invention.

[0012] Fig. 6A and Figure 6B The figure is a relationship diagram between image frames and time in the image output control device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] Figure 1 Schematic diagram of an image output control device 100 according to an embodiment of the present disclosure. The image output control device 100 can perform image processing such as interpolation compensation on the input image frame IMGin in the image data and provide the output image frame IMGout to a display (not shown) for playback. In some embodiments, the image output control device 100 is implemented in an integrated circuit (IC). The interpolation compensation can be motion estimation and motion compensation (MEMC) or other image compensation.

[0014] The image output control device 100 includes a storage device 110 and a controller 120. The controller 120 may provide a control signal Ctrl to the storage device 110 to control the access operation of the storage device 110. In some embodiments, the storage device 110 may include a memory or a buffer. When receiving image data with a variable frame rate (for example, multimedia content including 24 Hz frames and 60 Hz frames), the image output control device 100 will sequentially store each received input frame IMGin to the storage device 110. In addition, according to the frame rate FR of each input frame IMGin, the controller 120 can detect the frame rate change of the image data and record the storage position of the corresponding input frame IMGin in the storage device 110. The information of the frame rate FR can be provided by other devices or included in the data of the input frame IMGin.

[0015] The controller 120 is configured to read out the image frames IMG_R1 and IMG_R2 from the storage device 110, and perform interpolation compensation on the image frames IMG_R1 and IMG_R2 to generate an interpolated image frame between the image frames IMG_R1 and IMG_R2 as the output image frame IMGout. When it is detected that the frame rate of the input image frame IMGin changes, the controller 120 further provides a control signal Ctrl to the storage device 110 so as to read out the image frames IMG_R1 and IMG_R2 corresponding to the frame rate of the stored input image frame IMGin. For multimedia content with Quick Media Switching (QMS), the output image frames provided by the conventional image output controller will not match the actual frame rate, thus causing the video to be accelerated or decelerated. Compared with the conventional image output controller, the content of the output image frame IMGout provided by the image output control device 100 corresponds to the actual frame rate, so the video will have better fluency.

[0016] Figure 2Schematic diagram of a storage device 110 according to an embodiment of the present disclosure. The storage device 110 includes a plurality of buffers BUF0-BUFn and selectors 112 and 114. Each input image frame IMGin is stored in a separate buffer. In some embodiments, the buffers BUF0-BUFn are different buffers in a buffer. The selector 112 can write the input image frame IMGin to the corresponding buffer corresponding to the write position (or write address) assigned by the control signal Ctrl. In some embodiments, the selector 112 writes each input image frame IMGin to the buffer BUF0 to the buffer BUFn in sequence according to the control signal Ctrl. In some embodiments, the selector 112 may include a switching circuit or a demultiplexer. Similarly, the selector 114 reads out the image frames IMG_R1 and IMG_R2 from the corresponding buffer corresponding to the read position (or read address) assigned by the control signal Ctrl. In some embodiments, the image frames IMG_R1 and IMG_R2 are two adjacent input image frames IMGin written continuously to the storage device 110. In some embodiments, the selector 114 may include a switching circuit or a multiplexer. In some embodiments, the storage device 110 may be a memory, and the storage device 110 may store the input frame IMGin and the read frames IMG_R1 and IMG_R2 according to access information (such as a read address, a write address, etc.) in the control signal Ctrl.

[0017] Figure 3 Schematic diagram of a controller 120 according to an embodiment of the present disclosure. The controller 120 includes an access control circuit 122 and an image compensation circuit 126. The access control circuit 122 is configured to provide a control signal Ctrl to control the access operation of the storage device 110. The access control circuit 122 includes a register 124. The access control circuit 122 stores the write position of the input image frame IMGin and the read position of the image frames IMG_R1 and IMG_R2 in the register 124, and provides the write position and the read position to the storage device 110 through the control signal Ctrl. In addition, when the frame rate FR of the input image frame IMGin changes, the access control circuit 122 stores the write position of the input image frame IMGin corresponding to the new frame rate in the register 124 as the starting write position for the frame rate conversion. According to the start writing position of the frame rate conversion, the access control circuit 122 can dynamically adjust the reading positions of the image frames IMG_R1 and IMG_R2 so as to read the corresponding image frames IMG_R1 and IMG_R2 from the storage device 110 in accordance with the variable frame rate.

[0018] refer to Figure 4 , Figure 4 This is a flow chart of the access control circuit 122 reading the storage device 110 when the frame rate is changed according to an embodiment of the present disclosure.

[0019] In operation S410, the access control circuit 122 detects that the input image frame IMGin written to the storage device 110 is converted from a previous frame rate to a next frame rate. For example, the input image frame IMGin written to the storage device 110 is converted from a first frame rate FR1 (e.g., a previous frame rate or a frame rate before conversion) to a second frame rate FR2 (e.g., a next frame rate or a frame rate after conversion).

[0020] In operation S420, the access control circuit 122 records the write position of the first input image frame IMGin corresponding to the second frame rate FR2 in the storage device 110 in the register 124 as the start write position of the frame rate conversion. In some embodiments, the start write position of the frame rate conversion is the write position of the last input image frame IMGin corresponding to the first frame rate FR1.

[0021] In operation S430 , the access control circuit 122 determines whether the read positions of the image frames IMG_R1 and IMG_R2 in the storage device 110 exceed or reach the start writing position of the recorded frame rate conversion.

[0022] In operation S440, when the read position does not exceed the starting write position of the frame rate conversion, the access control circuit 122 sets the read position of the storage device 110 corresponding to the first frame rate FR1 (i.e., the previous frame rate) so as to read the image frames corresponding to the first frame rate FR1 in the storage device 110, so that the image frames IMG_R1 and IMG_R2 can be read from the storage device 110 corresponding to the first frame rate FR1.

[0023] In operation S450, when the read position exceeds or reaches the start writing position of the frame rate conversion, the access control circuit 122 sets the read position of the storage device 110 corresponding to the second frame rate FR2 (i.e., the converted frame rate) so as to read the image frames corresponding to the second frame rate FR2 in the storage device 110, so that the image frames IMG_R1 and IMG_R2 can be read from the storage device 110 corresponding to the second frame rate FR2 until the next frame rate conversion occurs or the reading of the storage device 110 is completed. Therefore, the image content read in operations S440 and S450 is consistent with its frame rate.

[0024] Reference Figure 3, the access control circuit 122 further provides the frame rate information FR_info to the image compensation circuit 126, so as to provide the image compensation circuit 126 with information such as the frame rates corresponding to the image frames IMG_R1 and IMG_R2 or the frame rate ratio of the image frames IMG_R1 and IMG_R2. In some embodiments, the image frames IMG_R1 and IMG_R2 are two consecutive adjacent image frames, and the image frame IMG_R1 is the previous image frame of the image frame IMG_R2. In some embodiments, the image compensation circuit 126 obtains the image frames IMG_R1 and IMG_R2 from the storage device 110 at the same time. In some embodiments, the image compensation circuit 126 obtains the image frames IMG_R1 and IMG_R2 from the storage device 110 in sequence.

[0025] According to the frame rate information FR_info and the display frame rate (or refresh rate) of the display (not shown), the image compensation circuit 126 obtains the compensation phase (or mixing coefficient) MC_phase corresponding to the image frames IMG_R1 and IMG_R2, and compensates the image frames IMG_R1 and IMG_R2 according to the compensation phase MC_phase to generate and provide an output image frame IMGout corresponding to the display frame rate to the display. Generally speaking, the display frame rate of the display is greater than the frame rate of the image frames IMG_R1 and IMG_R2 or is equal to the frame rate of the image frames IMG_R1 or IMG_R2. For example, when the display frame rate of the display is 120 Hz and the frame rate of the image frames IMG_R1 and IMG_R2 is 24 Hz, the image compensation circuit 126 obtains 5 compensation phase values ​​of the compensation phase according to the frame rate ratio of the display and the image frames IMG_R1 and IMG_R2 (i.e., 120 Hz / 24 Hz). Therefore, the image compensation circuit 126 can interpolate and compensate (or mix) the image frames IMG_R1 and IMG_R2 according to each compensation phase value of the compensation phase to generate a separate output image frame IMGout. In other words, for the image frames IMG_R1 and IMG_R2 from the storage device 110, the image compensation circuit 126 provides 5 output image frames IMGout to the display according to the 5 compensation phase values ​​of the compensation phase.

[0026] The controller 120 of the present disclosure may be implemented in any suitable form, including hardware circuits, software, firmware, or any combination thereof. At least a portion of the controller 120 may be selectively implemented as computer software running on one or more image processors, data processors, and / or digital signal processors or configurable module components (e.g., FPGA).

[0027] Figure 5 Flow chart of the image compensation circuit 126 compensating the phase during frame rate conversion according to an embodiment of the present disclosure.

[0028] In operation S510, after the access control circuit 122 detects that the input image frame IMGin written to the storage device 110 is converted from the first frame rate FR1 (e.g., the previous frame rate or the frame rate before conversion) to the second frame rate FR2 (e.g., the next frame rate or the frame rate after conversion), the image compensation circuit 126 of the controller 120 determines whether the image frames IMG_R1 and IMG_R2 are provided with output image frames IMGout according to the compensation phase values ​​corresponding to the compensation phase of the first frame rate FR1 (i.e., the previous frame rate) based on the frame rate information FR_info. The number of compensation phase values ​​is determined by the frame rates of the read image frames IMG_R1 and IMG_R2 and the display frame rate.

[0029] In operation S520, when the image frames IMG_R1 and IMG_R2 are not compensated according to all the compensation phase values ​​to provide the output image frame IMGout (i.e., a portion of the compensation phase values ​​have not been used to compensate the image frames IMG_R1 and IMG_R2), the access control circuit 122 maintains the read position of the storage device 110, so that the image compensation circuit 126 can continue to compensate the image frames IMG_R1 and IMG_R2 according to the first frame rate FR1 (i.e., the previous frame rate) and according to the remaining compensation phase values ​​(i.e., the compensation phase values ​​that have not been used) to provide the output image frame IMGout.

[0030] In operation S530, when the image frames IMG_R1 and IMG_R2 have been compensated according to all the compensation phase values ​​and the output image frame IMGout is provided, the access control circuit 122 determines whether all the input image frames IMGin corresponding to the first frame rate FR1 in the storage device 110 have been read. In some embodiments, the access control circuit 122 determines whether all the input image frames IMGin corresponding to the first frame rate FR1 have been read according to whether the read position of the storage device 110 reaches the start writing position of the frame rate conversion in the register 124.

[0031] In operation S540, when the input image frames IMGin corresponding to the first frame rate FR1 in the storage device 110 have not been completely read, the access control circuit 122 will continue to set the next read position of the storage device 110 to continue reading the image frames IMG_R1 and IMG_R2 corresponding to the first frame rate FR1, so that the image compensation circuit 126 can compensate the image frames IMG_R1 and IMG_R2 corresponding to the first frame rate FR1 (i.e., the previous frame rate) to provide the output image frame IMGout until all the input image frames IMGin corresponding to the first frame rate FR1 in the storage device 110 have been read.

[0032] In operation S550, after all input image frames IMGin corresponding to the first frame rate FR1 in the storage device 110 have been read, the access control circuit 122 will continue to set the next read position of the storage device 110 to read the image frames IMG_R1 and IMG_R2 corresponding to the second frame rate FR2 (i.e., the next frame rate), so that the image compensation circuit 126 can compensate the image frames IMG_R1 and IMG_R2 corresponding to the second frame rate FR2 to provide the output image frame IMGout until the next frame rate conversion occurs or the reading of the storage device 110 is completed.

[0033] Fig. 6A and Figure 6B 1 is a diagram showing the relationship between image frames and time in the image output control device 100 according to an embodiment of the present disclosure. In this embodiment, the storage device 110 has eight buffers BUF0-BUF7. In addition, the image output control device 100 is configured to convert and output image data with a frame rate of 60 Hz (i.e., 60 FPS) and a frame rate of 24 Hz (i.e., 24 FPS) to a display with a display frame rate (or refresh rate) of 120 Hz. Fig. 6A and Figure 6B In the embodiment, the time period tp is determined by the display frame rate 120 Hz of the display. In addition, according to the ratio of the display frame rate to the image frame rate, the image frame with a frame rate of 60 Hz corresponds to two time periods tp, and the image frame with a frame rate of 60 Hz corresponds to five time periods tp.

[0034] exist Fig. 6A , the image data having a frame rate of 60 Hz, frames A, B, C, D, E, F, G and H, and frames I, J, K and L having a frame rate of 24 Hz are sequentially written to the buffer of the storage device 110, wherein each frame is written to a separate buffer. For example, during time periods tp0 and tp1, frame A is written to the buffer BUF0 as the input frame IMGin. Then, during time periods tp2 and tp3, frame B is written to the buffer BUF1 as the input frame IMGin, and so on. As previously described, the write position of the input frame IMGin is determined by the controller 120.

[0035] In time periods tp4 and tp5, frame H is written to buffer BUF7 as input frame IMGin. At the same time, corresponding to the read position of control signal Ctrl, frames A and B stored in buffers BUF0 and BUF1 are read as frames IMG_R1 and IMG_R2, respectively. In this embodiment, frame A and frame B are two consecutive frames. According to the frame rates of frames A and B and the display frame rate of the display, the image compensation circuit 126 obtains two compensation phase values ​​P0 and P1 of the compensation phase MC_phase of frames A and B. In time period tp4, the image compensation circuit 126 compensates frames A and B according to the compensation phase value P0 to obtain compensated frame AB0, and provides compensated frame AB0 as output frame IMGout to the display. Next, during the time period tp5, the image compensation circuit 126 compensates the image frame A and the image frame B according to the compensation phase value P1 to obtain the compensated image frame AB1, and provides the compensated image frame AB1 as the output image frame IMGout to the display. In some embodiments, the image content of the compensated image frame AB0 is determined by the image frame A, and the image content of the compensated image frame AB1 is determined by the image frame A and the image frame B in a weighted manner.

[0036] exist Fig. 6A and Figure 6B In the example, corresponding to two frames with a frame rate of 60 Hz, the image compensation circuit 126 obtains two compensation phase values ​​P0 and P1 of the compensation phase MC_phase, and corresponding to two frames with a frame rate of 24 Hz, the image compensation circuit 126 obtains five compensation phase values ​​P0, P1, P2, P3 and P4 of the compensation phase MC_phase. It is worth noting that the compensation operation of the image compensation circuit 126 is only for illustration and is not intended to limit the present disclosure, and any image dynamic compensation method can be applied to the present disclosure.

[0037] During the time period tp6 to the time period tp10, the image frame I with a frame rate of 24 Hz is written as the input image frame IMGin to the buffer BUF0, and the image frame A previously stored in the buffer BUF0 has been read out during the time periods tp4 and tp5. When the image frame I is input to the storage device 110 (for example, during the time period tp6), the controller 120 detects that the input image frame IMGin is converted from a frame rate of 60 Hz to a frame rate of 24 Hz (operation S410), and records the starting writing position of the frame rate conversion (operation S420), for example, recording the starting writing position of the frame rate conversion as the position of the buffer BUF0.

[0038] In the time period tp6, corresponding to the read position of the control signal Ctrl, the frames B and C stored in the buffers BUF1 and BUF2 are read as the frames IMG_R1 and IMG_R2, respectively. Then, the image compensation circuit 126 compensates the frames B and C according to the compensation phase value P0 to obtain the compensated frame BC0, and provides the compensated frame BC0 as the output frame IMGout to the display.

[0039] In the time period tp7, since the read position has not exceeded the start writing position of the frame rate conversion (operation S430), the access control circuit 122 sets the read position of the storage device 110 corresponding to the frame rate 60 Hz (i.e., the previous frame rate) to read the storage device 110 (operation S440). At the same time, since the image compensation circuit 126 has not compensated the image frame B and the image frame C according to the compensation phase value P1 (operation S510), the controller 120 maintains the read position to continue to read out the image frame B and the image frame C, and compensates the image frame B and the image frame C according to the compensation phase value P1 to obtain the compensated image frame BC1, and provides the compensated image frame BC1 as the output image frame IMGout to the display (operation S520). In some embodiments, the image content of the compensated image frame BC0 is determined by the image frame B, and the image content of the compensated image frame BC1 is determined by the image frame B and the image frame C in a weighted manner.

[0040] In time periods tp8 and tp9, since the read position has not exceeded the start write position of the frame rate conversion (operation S430), the access control circuit 122 sets the read position of the storage device 110 corresponding to the frame rate 60 Hz (i.e., the previous frame rate) so as to read the storage device 110 (operation S440). In addition, since all the frames corresponding to the frame rate 60 Hz in the storage device 110 have not been read (operation S530), the controller 120 sets the read position to the buffers BUF2 and BUF3 (operation S540). Thus, the frames C and D stored in the buffers BUF2 and BUF3 are read as the frames IMG_R1 and IMG_R2, respectively. In time periods tp8 and tp9, the image compensation circuit 126 compensates the frames C and D according to the compensation phase values ​​P0 and P1 to obtain the compensated frames CD0 and CD1, respectively, and provides them as the output frames IMGout to the display.

[0041] During the time period tp11 to the time period tp15 , the image frame K with a frame rate of 24 Hz is written into the buffer BUF2 as the input image frame IMGin, and the image frame C previously stored in the buffer BUF2 has been read out during the time period tp6 to the time period tp9 .

[0042] In the time periods tp11 and tp12, since the read position has not exceeded the start writing position of the frame rate conversion (operation S430) and the image frames corresponding to the frame rate of 60 Hz in the storage device 110 have not been read out (operation S530), the controller 120 sets the read position to the buffers BUF6 and BUF7 (operation S540). Therefore, the image frames G and H stored in the buffers BUF6 and BUF7 are read out as the image frames IMG_R1 and IMG_R2, respectively. The image compensation circuit 126 compensates the image frames G and H according to the compensation phase values ​​P0 and P1 to obtain the compensated image frames GH0 and GH1, respectively, and provides them as the output image frames IMGout to the display.

[0043] In the time period tp13, since the read position reaches the start writing position of the frame rate conversion (operation S430), the access control circuit 122 sets the read position of the storage device 110 corresponding to the frame rate 24 Hz (i.e., the next frame rate) so as to read the storage device 110 (operation S450). In addition, all the image frames corresponding to the frame rate 60 Hz (i.e., the previous frame rate) in the storage device 110 have been read (operation S530), so the controller 120 sets the read position to the buffers BUF7 and BUF0 (operation S550). Therefore, the image frames H and I stored in the buffers BUF7 and BUF0 are read in the time period tp13 to the time period tp17 as the image frames IMG_R1 and IMG_R2, respectively. During the time period tp13 to the time period tp17, the image compensation circuit 126 compensates the image frames H and I according to the compensation phase values ​​P0 to P4 to obtain compensated image frames HI0, HI1, HI2, HI3 and HI4 respectively and provide them as output image frames IMGout to the display.

[0044] exist Fig. 6AIn the frame rate change transition period 610 from the time period tp6 (i.e., the frame rate of the input image frame IMGin changes) to the time period tp12 (i.e., the image frames corresponding to the frame rate of 60 Hz in the storage device 110 have all been read), the controller 120 can calculate, select and use the image frames corresponding to the frame rate of 60 Hz to generate the output image frame IMGout based on the frame rate of 60 (i.e., the previous frame rate), until the image frames corresponding to the frame rate of 60 Hz have been completely read. Therefore, compared with the conventional image output control device that directly uses the new frame rate (i.e., the next frame rate) to read and generate the output image frame when the frame rate of the input image frame IMGin changes, the content of the output image frame IMGout provided by the image output control device 100 corresponds to its actual frame rate, and therefore has better fluency. In addition, when the image data with a variable frame rate is dynamically switched, the image output control device 100 can avoid the phenomenon of acceleration or deceleration of the image caused by frame drop or freeze during the transition period of the frame rate change. In a conventional image output control device, when the number of buffers increases, it is more likely that the image content of the output image frame will not match the actual frame rate during the transition period of the frame rate conversion.

[0045] exist Figure 6B , the image data having a frame rate of 24 Hz, the image frames M, N, O and P, and the image frames Q, R, S, T, U, V, W and X having a frame rate of 60 Hz are sequentially used as input image frames IMGin and written into the buffer of the storage device 110, wherein each image frame is written into a separate buffer. As described above, the writing position of the input image frame IMGin is determined by the controller 120.

[0046] During time periods tp20 and tp21, the image frame Q having a frame rate of 60 Hz is written as the input image frame IMGin to the buffer BUF0, and the image frame I previously stored in the buffer BUF0 has been read out during the previous time period. When the image frame Q is input to the storage device 110 (e.g., during time period tp20), the controller 120 detects that the input image frame IMGin is converted from a frame rate of 24 Hz to a frame rate of 60 Hz (operation S410), and records the starting writing position of the frame rate conversion (operation S420), for example, recording the starting writing position of the frame rate conversion as the position of the buffer BUF0.

[0047] In the time period tp20, since the read position has not exceeded the start writing position of the frame rate conversion (operation S430), the access control circuit 122 sets the read position of the storage device 110 corresponding to the frame rate 24 Hz (i.e., the previous frame rate) to read the storage device 110 (operation S440). At the same time, since the image compensation circuit 126 has not compensated the image frames M and N according to the compensation phase values ​​P3 and P4 (operation S510), the controller 120 maintains the read position to continue reading out the image frames M and N, and compensates the image frames M and N according to the compensation phase values ​​P3 and P4 in the time periods tp20 and tp21, respectively, to provide the compensated image frames MN3 and MN4 as output image frames IMGout to the display (operation S520).

[0048] In time periods tp22 and tp23, the image frame R with a frame rate of 60 Hz is written to the buffer BUF1 as the input image frame IMGin. In addition, the image frames N and O stored in the buffers BUF5 and BUF6 are read as the image frames IMG_R1 and IMG_R2, respectively. Then, the image compensation circuit 126 compensates the image frames N and O according to the compensation phase values ​​P0 and P1, respectively, to obtain compensated image frames NO0 and NO1, and provides them to the display as output image frames IMGout. Then, in time periods tp24 and tp25, the image frame S is written to the buffer BUF1 as the input image frame IMGin. In addition, the image frames N and O stored in the buffers BUF5 and BUF6 continue to be read as the image frames IMG_R1 and IMG_R2, respectively. Next, the image compensation circuit 126 compensates the image frame N and the image frame O according to the compensation phase values ​​P2 and P3 to obtain compensated image frames NO2 and NO3, and provides them as output image frames IMGout to the display. This is repeated until, at the time period tp26, all the image frames corresponding to the frame rate 24 Hz (i.e., the previous frame rate) in the storage device 110 have been read (operation S530) and compensated accordingly to provide the output image frame IMGout (operation S550).

[0049] At time period tp27, since the read position reaches the start writing position of the frame rate conversion (operation S430), the access control circuit 122 sets the read position of the storage device 110 corresponding to the frame rate 60 Hz (i.e., the next frame rate) so as to read the storage device 110 (operation S450). In addition, all the image frames corresponding to the frame rate 24 Hz (i.e., the previous frame rate) in the storage device 110 have been read (operation S530), so the controller 120 sets the read position to the buffers BUF7 and BUF0 (operation S550). Therefore, the image frames P and Q stored in the buffers BUF7 and BUF0 are read at time periods tp27 and tp28 as image frames IMG_R1 and IMG_R2, respectively. During time periods tp27 and tp28 , the image compensation circuit 126 compensates the image frame P and the image frame Q according to the compensation phase values ​​P0 and P1 to obtain compensated image frames PQ0 and PQ1 respectively and provide them as output image frames IMGout to the display.

[0050] exist Figure 6B In the frame rate change transition period 620 from the time period tp20 (i.e., the frame rate of the input image frame IMGin changes) to the time period tp26 (i.e., the image frames corresponding to the frame rate of 24 Hz in the storage device 110 have all been read), the controller 120 can calculate, select and use the image frames corresponding to the frame rate of 24 Hz based on the frame rate of 24 Hz (i.e., the previous frame rate) to generate the output image frame IMGout until the image frames corresponding to the frame rate of 24 Hz have been completely read. Therefore, compared with the conventional image output control device that directly uses the new frame rate (i.e., the next frame rate) to read and generate the output image frame when the frame rate of the input image frame IMGin changes, the content of the output image frame IMGout provided by the image output control device 100 corresponds to its actual frame rate, and therefore has better fluency. Furthermore, when the image data with a variable frame rate is dynamically switched, the image output control device 100 can avoid the acceleration or deceleration of the image caused by frame drop or freeze during the transition period of the frame rate change.

[0051] Although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art should be able to make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the attached claims.

[0052]

Explanation of symbols

[0053] 100: Image output control device

[0054] 110: Storage device

[0055] 112,114: Selector

[0056] 120: Controller

[0057] 122: Access control circuit

[0058] 124: register

[0059] 126: Image compensation circuit

[0060] 610,620: Frame rate change transition period

[0061] BUF0-BUFn: Buffer

[0062] Ctrl: control signal

[0063] FR: Frame rate

[0064] FR_info: frame rate information

[0065] IMGin: Input image frame

[0066] IMGout: Output image frame

[0067] IMG_R1,IMG_R2: Image frame

[0068] MC_phase: compensation phase

[0069] S410-S450,S510-S560: Operation

[0070] tp,tp1-tp28: time period

Claims

1. An image output control device, comprising: A storage device configured to sequentially store a plurality of first input frames corresponding to a first frame rate and a plurality of second input frames corresponding to a second frame rate in the image data; a controller configured to record the start writing position of the plurality of second input frames in the storage device, and provide a control signal to the storage device to set the reading position of the storage device so as to read the first frame and the second frame from the storage device, Wherein, when the reading position of the storage device does not exceed the starting writing position, the controller reads the first frame and the second frame from the multiple first input frames stored in the storage device corresponding to the first frame rate, and when the reading position of the storage device reaches or exceeds the starting writing position, the controller reads the first frame and the second frame from the multiple second input frames stored in the storage device corresponding to the second frame rate.

2. The image output control device of claim 1, wherein the controller compensates the first image frame and the second image frame to provide a plurality of output image frames to a display, wherein the plurality of output image frames correspond to a display frame rate of the display. 3 . The image output control device according to claim 2 , wherein the display frame rate is greater than or equal to the first frame rate or the second frame rate. 4 . The image output control device as claimed in claim 2 , wherein when the read position of the storage device does not exceed the start writing position, the number of the plurality of output frames is determined by a ratio of the display frame rate to the first frame rate. 5 . The image output control device as claimed in claim 2 , wherein when the read position of the storage device reaches or exceeds the start writing position, the number of the plurality of output frames is determined by a ratio of the display frame rate to the second frame rate.

6. An image output control device as described in claim 1, wherein corresponding to each of the reading positions of the storage device, the controller provides a plurality of compensation phase values ​​corresponding to the display frame rate of the display according to the frame rates of the first image frame and the second image frame, and corresponding to each of the compensation phase values, the controller provides an output image frame to the display according to the first image frame and the second image frame.

7. An image output control device as described in claim 6, wherein when the first image frame and the second image frame are the multiple first input image frames, the controller provides the multiple compensation phase values ​​according to the first frame rate, and the number of the multiple compensation phase values ​​is determined by the ratio of the display frame rate to the first frame rate.

8. An image output control device as described in claim 6, wherein when the first image frame and the second image frame are the multiple second input image frames, the controller provides the multiple compensation phase values ​​according to the second frame rate, and the number of the multiple compensation phase values ​​is determined by the ratio of the display frame rate to the second frame rate.

9. An image output control device as described in claim 6, wherein when the first image frame and the second image frame are the first input image frame and the second input image frame respectively, the controller provides the multiple compensation phase values ​​according to the second frame rate, and the number of the multiple compensation phase values ​​is determined by the ratio of the display frame rate to the second frame rate.

10. An image output control method, comprising: Writing image data to a storage device, wherein the image data includes a plurality of first input image frames corresponding to a first frame rate and a plurality of second input image frames corresponding to a second frame rate; When the written image data is transformed from the plurality of first input frames to the plurality of second input frames, recording the start writing position of the plurality of second input frames in the storage device; Setting a reading position of the storage device so as to read a first image frame and a second image frame from the storage device; When the reading position of the storage device does not exceed the start writing position, reading the plurality of first input frames of the storage device according to the first frame rate to serve as the first frame and the second frame; as well as When the read position of the storage device reaches or exceeds the start writing position, the plurality of second input frames of the storage device are read according to the second frame rate to serve as the first frame and the second frame.

Images