Tester for 3D camera
By designing a tester for 3D cameras and using the FPGA signal processing module for signal measurement and simulation, the problem of insufficient signal control and measurement accuracy in the prior art is solved, and a more efficient and convenient signal testing and development process is achieved.
Patent Information
- Application Number
- CN202411546567.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-03-14
AI Technical Summary
During the testing and development of 3D cameras, it is difficult for the existing technology to achieve accurate signal control and measurement, and the existing equipment is large in size and complex in use, which cannot meet the needs of on-site construction.
A tester for 3D cameras is designed, including a control module and an FPGA signal processing module, which measures or simulates the machine signal through the FPGA signal processing module to provide accurate signal control and measurement functions.
It improves the measurement simulation accuracy, simplifies the use of equipment, reduces the requirements for on-site construction personnel, and makes it easier to perform signal measurement and control on-site.
Smart Images
Figure CN119629283A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of testing technology, and in particular to a tester for a 3D camera. Background Art
[0002] Laser line scan 3D cameras are a commonly used 3D imaging device for capturing the geometry and surface details of objects. These cameras usually require external trigger signals and control signals to ensure accurate data acquisition and camera operation. The trigger signal is usually provided by an encoder, while the control signal is usually provided by an optocoupler. In addition, there are other input and output signals for controlling the camera or the camera controlling external machinery based on the detection results.
[0003] At present, there are some difficulties in the camera testing and development process. First, testers need to simulate external signals to test whether the camera is normal. Second, in actual use, if the camera does not work properly, it is necessary to detect whether the signal provided by the external machine is normal to determine the problem.
[0004] At present, in the development stage, the machine is mainly used to provide signals for the camera. The signal quality is poor and it is impossible to achieve very precise control. Due to the limitations of the mechanical properties of the machine, it is unable to generate signals for various extreme conditions.
[0005] During the on-site implementation phase, if the on-site use is abnormal, it is necessary to measure the signal and power supply generated by the machine. This measurement process often requires the use of instruments such as oscilloscopes and multimeters. Oscilloscopes and other equipment are large and inconvenient to carry, complex to use, and require too much from on-site construction personnel. Moreover, measurement equipment that is not specially designed for this scenario cannot measure many parameters. Summary of the invention
[0006] The content of this application is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this application is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.
[0007] Some embodiments of the present application propose a tester for a 3D camera to solve the technical problems mentioned in the above background technology section.
[0008] As a first aspect of the present application, some embodiments of the present application provide a tester for a 3D camera, including: A control module, used for providing control logic; FPGA signal processing module, at least used to measure or simulate machine signals; Wherein, the control module is signal-connected to the FPGA signal processing module; The FPGA signal processing module includes: Signal input terminal, used to measure machine signals; Signal output terminal, used to simulate machine signals to control camera operation; Wherein, the signal input terminal is electrically connected to the machine, and the signal output terminal is electrically connected to the camera.
[0009] Optionally, the FPGA signal processing module includes: An encoder signal generator, for generating an encoder signal with controllable frequency and / or quantity; Wherein, the encoder signal generator signal is electrically connected to the signal output terminal.
[0010] Optionally, the FPGA signal processing module includes: A pulse signal generator, used to generate a pulse signal with a preset pulse width to test the influence of noise of each signal on the camera; Wherein, the pulse signal generator is electrically connected to the signal output terminal.
[0011] Optionally, the FPGA signal processing module includes: A first multiplexer, wherein the input end of the multiplexer is respectively connected to the signal input terminal, the encoder signal generator and the pulse signal generator, and the output end of the multiplexer is connected to the signal output terminal.
[0012] Optionally, the machine signal includes one or more of an encoder's abz three-phase signal, an optocoupler signal, and a level signal.
[0013] Optionally, the FPGA signal processing module includes: A signal measurement module, at least used for measuring machine signals; A second multiplexer, wherein an input end of the second multiplexer is electrically connected to the signal input terminal, and an output end of the second multiplexer is electrically connected to the signal measurement module.
[0014] Optionally, the FPGA signal processing module includes: A transceiver module, used to realize data transmission between the FPGA signal processing module and the control module; A third multiplexer, wherein an input end of the third multiplexer is electrically connected to the signal input terminal, and an output end of the third multiplexer is electrically connected to the transceiver module.
[0015] Optionally, the FPGA signal processing module includes an SPI interface, and the SPI interface is electrically connected to the control module.
[0016] Optionally, the tester for a 3D camera further comprises a functional device, wherein the functional device is electrically connected to the control module.
[0017] Optionally, the functional device includes one or more of a button module, an indicator light module, a power measurement module, a U disk interface, a USB interface and a power control module.
[0018] The beneficial effect of the present application is that it provides a tester for a 3D camera that measures or simulates machine signals through an FPGA signal processing module to improve measurement simulation accuracy and is easy to use. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The illustrative embodiment drawings and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application.
[0020] In addition, throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the components and elements are not necessarily drawn to scale.
[0021] In the attached picture: Figure 1 is a principle block diagram of a tester according to an embodiment of the present application; Figure 2 It is a principle block diagram of an FPGA signal processing module in a tester according to an embodiment of the present application.
[0022] Description of reference numerals: 10. Tester; 200. Control module; 100, FPGA signal processing module; 101, signal input terminal; 102, signal output terminal; 103. Encoder signal generator; 104. Pulse signal generator; 105. A first multiplexer; 106. signal measurement module; 107. second multiplexer; 108. transceiver module; 109. third multiplexer; 110, SPI interface; 300. Functional device. DETAILED DESCRIPTION
[0023] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.
[0024] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.
[0025] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.
[0026] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".
[0027] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.
[0028] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.
[0029] like Figure 1 and Figure 2 As shown, the present application provides a tester 10 for a 3D camera, including: a control module 200 and an FPGA signal processing module 100 .
[0030] The control module 200 is used to provide control logic. Specifically, the control module 200 can be an MCU. The FPGA signal processing module 100 is at least used to measure or simulate machine signals. The control module 200 is signal-connected to the FPGA signal processing module 100 .
[0031] The FPGA signal processing module 100 includes: a signal input terminal 101 and a signal output terminal 102 .
[0032] The signal input terminal 101 is used to measure the machine signal; the signal output terminal 102 is used to simulate the machine signal to control the camera operation; wherein the signal input terminal 101 is electrically connected to the machine, and the signal output terminal 102 is electrically connected to the camera.
[0033] The FPGA signal processing module 100 tests the signal by directly measuring the duration between two edges of a signal. For the duration of the high level, the time between the rising edge before the high level and the falling edge after the high level is tested.
[0034] For signal generation, different high and low level signals are generated according to the settings of the MCU. Since the time when the FPGA runs the code can be accurately matched to the crystal clock frequency of its input, it can work at 100MHZ, and the signal duration resolution can be 10 nanoseconds, with high measurement accuracy.
[0035] By adopting the above technical solution, the machine signal is measured or simulated through the FPGA signal processing module 100, which can improve the measurement simulation accuracy and facilitate use.
[0036] In some embodiments, the FPGA signal processing module 100 includes: an encoder signal generator 103. The encoder signal generator 103 is electrically connected to the signal output terminal 102, and is used to generate an encoder signal with controllable frequency and / or quantity. In some embodiments, the FPGA signal processing module 100 includes: a pulse signal generator 104 .
[0037] The pulse signal generator 104 is electrically connected to the signal output terminal 102 and is used to generate a pulse signal with a preset pulse width to test the influence of the noise of each signal on the camera.
[0038] Specifically, the test method includes the following steps: (1) The camera enters the acquisition state.
[0039] (2) The computer sends a command to the tester 10 to set the frequency and quantity of the encoder signal to be simulated. The tester 10 is triggered, generates an encoder signal, and starts collecting data.
[0040] (3) Wait until the encoder signal generated by the tester 10 ends, compare the collected data on the computer side, and compare the timestamps of the data. Compare the collected image with the theoretical image to determine whether the camera can process the encoder signal normally and whether the situation can work normally.
[0041] (4) The camera sets the signal filtering value, the tester 10 sets the signal duration, and the signal is generated after the noise duration. The computer program determines whether the camera receives the signal and whether the signal processing is normal.
[0042] In some embodiments, the FPGA signal processing module 100 includes: a first multiplexer 105 (MUX). The input end of the multiplexer is respectively connected to the signal input terminal 101 , the encoder signal generator 103 and the pulse signal generator 104 , and the output end of the multiplexer is connected to the signal output terminal 102 .
[0043] In some embodiments, the signal types of the signal input terminal 101 and the signal output terminal 102 are the same. The machine signal includes one or more of the ABZ three-phase signal of the encoder, the optocoupler signal, and the level signal. All signals are connected to the FPGA, and any signal can be converted into a signal such as USART according to the FPGA design.
[0044] In some embodiments, the FPGA signal processing module 100 includes: a signal measurement module 106 and a second multiplexer 107 (MUX).
[0045] Specifically, the signal measuring module 106 is at least used to measure the machine signal; the input end of the second multiplexer 107 is electrically connected to the signal input terminal 101 , and the output end of the second multiplexer 107 is electrically connected to the signal measuring module 106 .
[0046] Specifically, the optocoupler signal measurement method includes the following steps: (1) Connect the signal generated by the machine to the tester 10.
[0047] (2) Actual operation of the machine.
[0048] (3) The tester 10 sends the period and quantity of the encoder signal to the computer, and the user compares the value with the machine equipment.
[0049] (4) The control machine generates an io signal, and the tester 10 measures the duration, level value, and whether there are glitches of the signal, and sends the measurement information of the signal to the computer, which is displayed on the computer and compared with the machine setting value.
[0050] (5) The tester 10 displays the optocoupler signal waveform and the optocoupler triggering duration on the computer for the user to check.
[0051] The level signal measurement method includes the following steps: (1) The camera level signal is set as output, and the tester 10 signal is set as input. The computer controls the camera to generate high and low signals.
[0052] (2) The machine level signal is set as input, the tester 10 is set as output, the tester 10 outputs high and low levels, and the machine signal display is checked to determine whether the machine reads the level signal normally.
[0053] In some embodiments, the FPGA signal processing module 100 includes: a transceiver module 108 and a third multiplexer 109 (MUX).
[0054] Specifically, the transceiver module 108 is used to realize data transmission between the FPGA signal processing module 100 and the control module 200; the input end of the third multiplexer 109 is electrically connected to the signal input terminal 101, and the output end of the third multiplexer 109 is electrically connected to the transceiver module 108.
[0055] In some embodiments, the FPGA signal processing module 100 includes an SPI interface 110 , and the SPI interface 110 is electrically connected to the control module 200 .
[0056] In some embodiments, the tester 10 for a 3D camera further includes a functional device 300 , and the functional device 300 is electrically connected to the control module 200 .
[0057] In some embodiments, the functional device 300 includes one or more of a button module, an indicator light module, a power measurement module, a U disk interface, a USB interface, and a power control module 200 .
[0058] Specifically, the USB interface is used to connect to a computer so that the tester 10 can be controlled by the computer. For simple scenarios, it is not necessary to connect to a computer for control, and the buttons on the device can be used directly.
[0059] The tester 10 can be connected to a computer, accept the software control of the computer (host computer), provide signals for the device under development, and perform automated testing. Therefore, for complex functions, the host computer software can be directly used, with graphical display, making the operation simpler.
[0060] The USB interface is used to plug in a USB flash drive to save device logs. In scenarios where long-term monitoring is required, all data can be directly recorded in the USB flash drive for easy follow-up investigation.
[0061] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.
Claims
1. A tester for a 3D camera, characterized in that: include: A control module, used for providing control logic; FPGA signal processing module, at least used to measure or simulate machine signals; Wherein, the control module is signal-connected to the FPGA signal processing module; The FPGA signal processing module includes: Signal input terminal, used to measure machine signals; Signal output terminal, used to simulate machine signals to control camera operation; Wherein, the signal input terminal is electrically connected to the machine, and the signal output terminal is electrically connected to the camera.
2. The tester for a 3D camera according to claim 1, characterized in that: The FPGA signal processing module includes: An encoder signal generator, for generating an encoder signal with controllable frequency and / or quantity; Wherein, the encoder signal generator signal is electrically connected to the signal output terminal.
3. The tester for a 3D camera according to claim 2, characterized in that: The FPGA signal processing module includes: A pulse signal generator, used to generate a pulse signal with a preset pulse width to test the influence of noise of each signal on the camera; Wherein, the pulse signal generator is electrically connected to the signal output terminal.
4. The tester for a 3D camera according to claim 3, characterized in that: The FPGA signal processing module includes: A first multiplexer, wherein the input end of the multiplexer is respectively connected to the signal input terminal, the encoder signal generator and the pulse signal generator, and the output end of the multiplexer is connected to the signal output terminal.
5. The tester for a 3D camera according to claim 1, characterized in that: The machine signal includes one or more of the encoder's abz three-phase signal, an optical coupler signal, and a level signal.
6. The tester for a 3D camera according to claim 1, characterized in that: The FPGA signal processing module includes: A signal measurement module, at least used for measuring machine signals; A second multiplexer, wherein an input end of the second multiplexer is electrically connected to the signal input terminal, and an output end of the second multiplexer is electrically connected to the signal measurement module.
7. The tester for a 3D camera according to claim 1, characterized in that: The FPGA signal processing module includes: A transceiver module, used to realize data transmission between the FPGA signal processing module and the control module; A third multiplexer, wherein an input end of the third multiplexer is electrically connected to the signal input terminal, and an output end of the third multiplexer is electrically connected to the transceiver module.
8. The tester for a 3D camera according to claim 1, characterized in that: The FPGA signal processing module includes an SPI interface, and the SPI interface is electrically connected to the control module.
9. The tester for a 3D camera according to claim 1, characterized in that: The tester for a 3D camera further includes a function device electrically connected to the control module.
10. The tester for a 3D camera according to claim 9, characterized in that: The functional device includes one or more of a button module, an indicator light module, a power measurement module, a U disk interface, a USB interface and a power control module.