Three-dimensional memory and preparation method thereof

Abstract

The invention relates to a three-dimensional memory and a preparation method thereof. The three-dimensional memory is provided with an array region and a peripheral region positioned beside the array region, and comprises at least one step structure and a plurality of signal line leads, the step structure is located in the peripheral area and comprises a plurality of conductive steps and a plurality of insulating steps which are alternately stacked in the direction perpendicular to the substrate. The signal line leads are positioned on the surfaces of the corresponding conductive steps and are electrically connected with the conductive steps; the maximum difference value between the parasitic capacitance loads of the signal line leads is smaller than or equal to a target threshold value. The performance of the three-dimensional memory can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers and other electronic devices. It consists of a number of memory cells arranged in an array. With the development of memory technology, in order to further pursue the miniaturization of device structure, the process is changed from planar to three-dimensional, that is, the three-dimensional arrangement of memory cells has become the main development direction of DRAM devices.

[0003] In current three-dimensional memories, in order to solve the problem that signal lines are difficult to lead out after stacking, a staircase design is usually used to lead out the signal lines connected to each storage unit in layers. That is, the staircase structure can be composed of multiple dielectric layers and multiple conductive layers alternately stacked, so that any conductive layer can be used to lead out the signal lines connected to the storage units in the corresponding layer.

[0004] However, in the ladder structure, since the parasitic capacitance load caused by each conductive layer decreases from bottom to top, based on the "barrel effect," the performance of the memory is easily limited by the maximum parasitic capacitance load of the conductive layer, which has an adverse effect on the three-dimensional development of the memory. Summary of the invention

[0005] Based on this, the embodiments of the present disclosure provide a three-dimensional memory and a method for manufacturing the same, so as to effectively improve the performance of the three-dimensional memory.

[0006] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present disclosure provide a three-dimensional memory. The three-dimensional memory has an array area and a peripheral area located next to the array area, including: at least one step structure and a plurality of signal line leads. The step structure is located in the peripheral area, including: a plurality of conductive steps and a plurality of insulating steps alternately stacked in a direction perpendicular to the substrate. The signal line leads are respectively located on the surface of the corresponding conductive steps and are electrically connected to the conductive steps; wherein the maximum difference between the parasitic capacitance loads of the signal line leads is less than or equal to the target threshold.

[0007] In some embodiments, the parasitic capacitive loads of the signal line leads are equal or approximately equal.

[0008] In some embodiments, the thickness of each insulating step gradually decreases in a direction away from the substrate.

[0009] In some embodiments, the thickness of each insulating step decreases uniformly along a direction away from the substrate.

[0010] In some embodiments, the difference in thickness between any two adjacent insulating steps ranges from 5 nm to 10 nm.

[0011] In some embodiments, the dielectric constants of the insulating steps are the same.

[0012] In some embodiments, multiple signal line leads include a first type of signal line lead and a second type of signal line lead; wherein, the insulating step corresponding to the first type of signal line lead is located on the side of the insulating step corresponding to the second type of signal line lead close to the substrate, and the thickness of the insulating step corresponding to the first type of signal line lead is greater than the thickness of the insulating step corresponding to the second type of signal line lead.

[0013] In some embodiments, the thickness of each insulating step is the same, and the dielectric constant of each insulating step gradually increases in a direction away from the substrate.

[0014] In some embodiments, the thickness and / or width of each conductive step is the same or substantially the same.

[0015] In some embodiments, a maximum parasitic capacitance load among the parasitic capacitance loads of the signal line leads is less than or equal to 9 fF.

[0016] On the other hand, according to some embodiments, the present disclosure also provides a method for preparing a three-dimensional memory, comprising the following steps.

[0017] In the peripheral region of the substrate, a plurality of conductive steps and a plurality of insulating steps are formed which are alternately stacked in a direction perpendicular to the substrate to obtain a stepped structure.

[0018] A signal line lead electrically connected to the conductive step is formed on the surface of each conductive step; wherein the dielectric constant and thickness of each insulating step are determined by matching the design distribution of the conductive step and the insulating step in the stepped structure so that the maximum difference between the parasitic capacitance loads of each signal line lead is less than or equal to the target threshold.

[0019] The embodiments of the present disclosure may or at least have the following advantages:

[0020] In the embodiment of the present disclosure, by making the maximum difference between the parasitic capacitance loads of the multiple signal line leads connected to the conductive steps in the ladder structure less than or equal to the target threshold, the parasitic capacitance loads of the signal line leads can be balanced to effectively reduce the maximum parasitic capacitance load among the parasitic capacitance loads corresponding to the signal line leads. In this way, compared with the related art in which the parasitic capacitance loads on the multiple signal line leads connected to the conductive steps decrease layer by layer from bottom to top, the embodiment of the present disclosure can eliminate the limitation problem on the memory performance caused by the maximum parasitic capacitance load in the "barrel effect", thereby effectively improving the performance of the three-dimensional memory, for example, it is beneficial to improve the storage capacity and storage density of the three-dimensional memory.

[0021] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A three-dimensional schematic diagram of a three-dimensional memory provided in some embodiments;

[0024] Figure 2 A three-dimensional schematic diagram of another three-dimensional memory provided in some embodiments;

[0025] Figure 3 A schematic top view of a three-dimensional memory provided in some embodiments;

[0026] Figure 4 A schematic diagram of the distribution of a ladder structure in a three-dimensional memory provided in some embodiments;

[0027] Figure 5 A schematic diagram of the distribution of a ladder structure in a three-dimensional memory provided in some other embodiments;

[0028] Figure 6 is a cross-sectional schematic diagram of a stepped structure provided in some embodiments;

[0029] Figure 7 is a cross-sectional schematic diagram of a stepped structure provided in some other embodiments;

[0030] Figure 8 is a cross-sectional schematic diagram of a stepped structure provided in yet some embodiments;

[0031] Fig. 9 is a cross-sectional schematic diagram of a stepped structure provided in yet some embodiments;

[0032] Fig.10 Figure (a) is a thickness distribution diagram of each insulating step in a different step structure provided in some embodiments; Fig.10 Figure (b) is Fig.10 FIG. 8 (a) shows a curve diagram of the change in parasitic capacitance load corresponding to the change in thickness of each insulating step in different step structures.

[0033] Description of reference numerals:

[0034] 1-substrate, R1-array region, R2-peripheral region, 2-step structure, 21-conductive step, 22-insulating step, 3-signal line lead, 31-first type signal line lead, 32-second type signal line lead, 4-storage array structure, U-storage unit, 41-transistor, 411-first semiconductor layer, 412-first gate dielectric layer, 413-first gate, 42-capacitor, 421-first electrode, 422-dielectric layer, 423-second electrode, 5-select transistor, 51-second semiconductor layer, 52-second gate dielectric layer, 53-second gate, BL-bit line, CBL-common bit line, WL1-first word line, WL2-second word line, M1-first target layer group, M2-second target layer group. DETAILED DESCRIPTION

[0035] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intervening element or layer. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0040] In the stepped structure of the three-dimensional memory, the parasitic capacitance load of each conductive layer decreases layer by layer from bottom to top. After analysis, the size of the parasitic capacitance is proportional to the volume of the conductor and inversely proportional to the distance between adjacent conductors (i.e., the thickness of the insulating medium). However, the plane area of ​​the conductive layer in the stepped structure (i.e., the positive projection area on the substrate) decreases in the direction away from the substrate. In addition, the insulating medium of the same thickness is usually set between any adjacent conductive layers in the stepped structure, which causes the parasitic capacitance load of each conductive layer to decrease layer by layer in the direction away from the substrate. In this way, the parasitic capacitance load of the lower conductive layer close to the substrate in the stepped structure is significantly greater than the parasitic capacitance load of the upper conductive layer away from the substrate. However, the driving capability design of the three-dimensional memory is determined by the maximum parasitic capacitance load. Therefore, based on the "barrel effect", this phenomenon easily causes the load capacitance of the three-dimensional memory to be too large, resulting in the need to design a larger storage capacitor, thereby limiting the storage density of the three-dimensional memory and increasing the manufacturing cost, resulting in an adverse effect on the three-dimensional development of the memory.

[0041] Based on this, some embodiments of the present disclosure provide a three-dimensional memory for balancing the parasitic capacitance load caused by each conductive layer in a stepped structure to reduce the maximum parasitic capacitance load, thereby effectively improving the performance of the three-dimensional memory, such as improving the storage density of the three-dimensional memory.

[0042] See also Figure 1 to Figure 4The three-dimensional memory has an array area R1 and a peripheral area R2 located next to the array area R1. The three-dimensional memory includes: at least one step structure 2 and a plurality of signal line leads 3. The step structure 2 is located in the peripheral area R2 of the substrate 1, and includes: a plurality of conductive steps 21 and a plurality of insulating steps 22 alternately stacked along a direction perpendicular to the substrate 1 (for example, the Z direction). The signal line leads 3 are respectively located on the surface of the corresponding conductive steps 21 and are electrically connected to the conductive steps 21; wherein the maximum difference between the parasitic capacitance loads of each signal line lead 3 is less than or equal to the target threshold.

[0043] Here, the parasitic capacitance load of the signal line lead 3 refers to the parasitic capacitance formed on the target conductive step 21 electrically connected thereto due to the adjacent conductive steps 21 and the insulating steps 22. The parasitic capacitance load of the signal line lead 3 below can also be equivalently expressed as the parasitic capacitance load of the corresponding conductive step 21.

[0044] It can be understood that when different layers of insulating steps 22 are made of the same material and have the same thickness, the signal line lead 3 corresponding to the second conductive step 21 will usually have the largest parasitic capacitance load in the direction away from the substrate 1. Moreover, the parasitic capacitance loads of the signal line leads 3 corresponding to the conductive steps 21 of each layer above the second conductive step 21 will gradually decrease in the direction away from the substrate 1. Therefore, in the embodiment of the present disclosure, the maximum difference between the parasitic capacitance loads of each signal line lead 3 is less than or equal to the target threshold, which means that the parasitic capacitance loads of each signal line lead 3 are made consistent or have a smaller difference by adjusting the material and / or thickness of the insulating steps 22 corresponding to the conductive steps 21 of different layers. Some possible implementations of the step structure 2 in the embodiment of the present disclosure will be described in detail below.

[0045] Furthermore, illustratively, the target threshold is zero.

[0046] Illustratively, the target threshold is less than or equal to 9 fF.

[0047] Illustratively, the target threshold is less than or equal to 5 fF.

[0048] In order to clearly illustrate the electrical connection relationship between the conductive step 21 and the signal line lead 3 in the three-dimensional memory, Figure 1 and Figure 2 The insulating steps 22 are omitted, and only the distribution of the conductive steps 21 in the stepped structure 2 is illustrated.

[0049] In some embodiments, see Figure 1 and Figure 2 The three-dimensional memory further includes a memory array structure 4 located in the array region R1. The memory array structure 4 includes, for example, a plurality of memory cells U arranged in an array and stacked in a direction perpendicular to the substrate 1.

[0050] For example, a plurality of memory cells U are stacked along a direction perpendicular to the substrate 1 (e.g., the Z direction), and arranged in rows along a first direction parallel to the substrate 1 (e.g., the X direction), and arranged in columns along a second direction parallel to the substrate 1 (e.g., the Y direction). The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) intersect, for example, orthogonal. That is, a plurality of memory cells U can be arranged in an array in a plane parallel to the substrate 1, and stacked from bottom to top along a direction perpendicular to the substrate 1, to obtain a three-dimensional memory.

[0051] Here, the memory cells U are arranged on the substrate 1, and the array arrangement of the memory cells U includes a regular array arrangement or a honeycomb array arrangement. Moreover, the honeycomb array arrangement can be understood as multiple rows of memory cells U, and the staggered distribution between adjacent rows of memory cells U makes the geometric center of each memory cell U in a column of memory cells U not on a straight line. The honeycomb array arrangement is only used to illustrate the relative position of the geometric center of the memory cell U, and does not limit the outer contour shape of the memory cell U itself.

[0052] For example, the substrate 1 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0053] For example, the memory unit U can be understood as a memory unit on a logic circuit, such as a single transistor single capacitor (1T1C) or a double transistor without a capacitor (2T0C) as a memory unit U, without limiting the wiring characteristics or shape and structural characteristics of the memory unit U. In some of the following embodiments, a single transistor single capacitor (1T1C) is used as an example of the memory unit U, but it is not limited thereto.

[0054] In some embodiments, see Figure 3, the memory cell U adopts a 1T1C structure, including a transistor 41 and a storage capacitor 42. The transistor 41 includes a first gate 413 and a first gate dielectric layer 412 and a first semiconductor layer 411 surrounding the sidewall of the first gate 413; wherein the first gate 413 is electrically connected to the first word line WL1; the first semiconductor layer 411 serves as the channel region and source and drain of the transistor 41, and the outer walls of the first semiconductor layer 411 on both sides opposite to each other in the X direction are electrically connected to the bit line BL and the first electrode 421 of the capacitor 42, respectively. The capacitor 42 also includes a dielectric layer 422 covering the first electrode 421 and a second electrode 423 covering the dielectric layer 422. The first word line WL1 can extend in a direction perpendicular to the substrate 1. The bit line BL can extend in the Y direction. In addition, a plurality of memory cells U can be arranged in rows spaced apart in the Y direction.

[0055] For example, a column of memory cells U shares the same bit line BL.

[0056] By way of example, two adjacent columns of memory cells U are respectively located on two sides of a bit line BL and share the same bit line BL.

[0057] For example, please continue to see Figure 3 The three-dimensional memory further includes: a common bit line CBL arranged in the same layer as the bit line BL; wherein each bit line BL is electrically connected to the common bit line CBL in the same layer through a corresponding selection transistor 5. The selection transistor 5 includes a second gate 53 and a second gate dielectric layer 52 and a second semiconductor layer 51 surrounding the side wall of the second gate 53; wherein the second gate 53 is electrically connected to the second word line WL2; the second semiconductor layer 51 serves as a channel region and a source and drain of the selection transistor 5, and the outer walls of the second semiconductor layer 51 opposite to each other in the Y direction are electrically connected to the bit line BL and the common bit line CBL respectively.

[0058] Here, being arranged in the same layer means that the heights of the two from the surface of the substrate 1 are substantially the same.

[0059] It is necessary to add that Figure 2 and Figure 3 It is understood that, in some embodiments, each conductive step 21 in the stepped structure 2 may be an external terminal corresponding to the common bit line CBL.

[0060] In some embodiments, see Figure 4 , each layer structure in the memory array structure 4 can generally be formed by alternately stacking multiple conductive pattern layers (including semiconductor layers) and multiple insulating pattern layers. Accordingly, the conductive step 21 in the step structure 2 can be formed based on the same conductive material layer as the conductive pattern layer in the memory array structure 4, and the insulating step 22 in the step structure 2 can be formed based on the same insulating material layer as the insulating pattern layer in the memory array structure 4.

[0061] For example, the material of the insulating material layer may be one or a combination of multiple insulating materials such as nitride, oxide or oxynitride.

[0062] In some examples, the conductive material layer includes, but is not limited to, a polysilicon (Poly) layer.

[0063] In some embodiments, see Figure 1 and Figure 4 The signal line lead 3 is disposed on the upper surface of the corresponding conductive step 21 and extends in a direction perpendicular to the upper surface (eg, in a Z direction perpendicular to the substrate 1 ).

[0064] By way of example, the signal line lead 3 includes but is not limited to a columnar structure, such as a circular column, a rectangular column, a prism or a special-shaped column.

[0065] By way of example, the material of the signal line lead 3 includes, but is not limited to, metal, such as metal tungsten or metal copper.

[0066] In some embodiments, see Figure 5 The step structure 2 may be disposed on one side of the memory array structure 4. The step structure 2 includes a plurality of conductive steps 21 stacked in a direction perpendicular to the substrate 1. Figure 5 The insulating steps between adjacent conductive steps 21 are omitted in the figure, but it can be understood that adjacent conductive steps 21 can be insulated from each other by corresponding insulating steps.

[0067] For example, the number of the conductive steps 21 may be 16, 32, or 64.

[0068] In some examples, such as Figure 1 , Figure 4 and Figure 5 As shown in FIG. 1 , a plurality of signal line leads 3 may be linearly arranged along the arrangement direction of each conductive step 21 .

[0069] In the embodiment of the present disclosure, by making the maximum difference between the parasitic capacitance loads of the multiple signal line leads 3 connected to the conductive steps 21 in the stepped structure 2 less than or equal to the target threshold, the parasitic capacitance loads of the signal line leads 3 can be balanced to effectively reduce the maximum parasitic capacitance load among the parasitic capacitance loads corresponding to the signal line leads 3. In this way, compared with the related art in which the parasitic capacitance loads on the multiple signal line leads 3 connected to the conductive steps 21 decrease layer by layer from bottom to top, the embodiment of the present disclosure can eliminate the limitation problem on the memory performance caused by the maximum parasitic capacitance load in the "barrel effect", thereby effectively improving the performance of the three-dimensional memory, for example, it is beneficial to improve the storage capacity and storage density of the three-dimensional memory.

[0070] It is worth mentioning that the maximum difference between the parasitic capacitance loads of the signal line leads 3 is less than or equal to the target threshold, and there are the following multiple possible implementations.

[0071] In some possible implementations, the parasitic capacitance loads of the signal line leads 3 are equal or substantially equal.

[0072] Accordingly, the target threshold is, for example, zero.

[0073] It can be understood that when the parasitic capacitance loads of the signal line leads 3 of each layer are equal or approximately equal, the maximum difference between the parasitic capacitance loads of each signal line lead 3 tends to zero; that is, it can ensure that the parasitic capacitance loads of each layer of conductive steps 21 in the stepped structure 2 are relatively balanced, so as to avoid large differences in the parasitic capacitance loads of each layer of conductive steps 21 due to different physical parameters of each layer of conductive steps 21.

[0074] For some possible implementations, see Figure 6 , along the direction away from the substrate 1 , the thickness of each insulating step 22 gradually decreases.

[0075] In the embodiment of the present disclosure, each conductive step 21 of the step structure 2 is stacked to match the requirements, and the parasitic capacitance of each conductive step 21 can be adjusted accordingly by adjusting the thickness of each insulating step 22, so as to achieve the effect of adjusting the parasitic capacitance load of each signal line lead 3. In this way, compared with the related art, the embodiment of the present disclosure gradually reduces the thickness of each insulating step 22 in the direction away from the substrate 1, which is conducive to relatively reducing the parasitic capacitance of the conductive step 21 on the side close to the substrate 1, and relatively increasing the parasitic capacitance of the conductive step 21 on the side away from the substrate 1, so as to achieve the balance of the parasitic capacitance load of each layer of conductive steps 21 in the step structure 2, thereby avoiding the parasitic capacitance load of each layer of conductive steps 21 having a large difference due to the different physical parameters of each layer of conductive steps 21.

[0076] It should be added that, in the embodiment of the present disclosure, the materials of the insulating steps 22 can be kept consistent, that is, the insulating steps 22 have the same dielectric constant. In this way, it is easy to adjust the parasitic capacitance of the corresponding conductive step 21 by simply determining the thickness of the insulating step 22. However, this is not limited to this, and it is also allowed that the materials of the insulating steps 22 are inconsistent, or the materials of some insulating steps 22 are inconsistent.

[0077] Illustratively, the dielectric constants of the insulating steps 22 are the same.

[0078] In addition, the thickness of each insulating step 22 gradually decreases, which may be specifically expressed as: a constant gradient decrease, a step-like decrease, or a group-like decrease.

[0079] In some embodiments, see Figure 6, along the direction away from the substrate 1, the thickness of each insulating step 22 decreases with a constant gradient.

[0080] Here, the thickness of each insulating step 22 decreases with a constant gradient, which means that the difference in thickness between any two adjacent insulating steps 22 is a constant value or a substantially constant value.

[0081] In some examples, the difference in thickness between any two adjacent insulating steps 22 ranges from 5 nm to 10 nm.

[0082] For example, along the direction away from the substrate 1 , the thickness of each insulating step 22 has a decreasing gradient of 5 nm, 6 nm, 8 nm, 9 nm or 10 nm.

[0083] In some other examples, the difference in thickness between any two adjacent insulating steps 22 may also be less than 5 nm. For example, the number of stacked insulating steps 22 is much greater than 64 layers.

[0084] In other embodiments, see Figure 7 , the thickness of each insulating step 22 can be reduced in a step-like manner along the direction away from the substrate 1; that is, the thickness of the insulating step 22 of the target layer group can be kept consistent along the direction away from the substrate 1, and the thickness of the insulating step 22 between adjacent target layer groups or outside the target layer group can be reduced along the direction away from the substrate 1.

[0085] Here, the target layer group can be set to match the position distribution of the conductive steps 21 in the step structure 2 and the morphological characteristics of the conductive steps 21. For example, the target layer group can be set to Figure 7 The first target layer group M1 and the second target layer group M2 are shown in FIG. 1 ; the first target layer group M1 is close to the substrate 1 and may include three insulating steps 22; the second target layer group M2 is located in the middle area of ​​the step structure 2 along the direction perpendicular to the substrate 1 and may include four insulating steps 22. It can be seen that the number of insulating steps 22 in different target layer groups may be the same or different.

[0086] In some other embodiments, see Figure 8 , along the direction away from the substrate 1, the thickness of each insulating step 22 can be reduced in groups. For example, the plurality of signal line leads 3 include a first type of signal line lead 31 and a second type of signal line lead 32; wherein the insulating step 22 corresponding to the first type of signal line lead 31 is located on a side of the insulating step 22 corresponding to the second type of signal line lead 32 close to the substrate 1, and the thickness of the insulating step 22 corresponding to the first type of signal line lead 31 is greater than the thickness of the insulating step 22 corresponding to the second type of signal line lead 32.

[0087] Here, the insulating step 22 corresponding to the first type signal line lead 31 refers to: the insulating step 22 between the conductive step 21 connected to the first type signal line lead 31 and the adjacent conductive step 21; specifically, it can be the insulating step 22 above or below the conductive step 21 connected to the first type signal line lead 31, or it can be the insulating steps 22 on both sides of the conductive step 21 connected to the first type signal line lead 31. Similarly, the insulating step 22 corresponding to the second type signal line lead 32 refers to: the insulating step 22 between the conductive step 21 connected to the second type signal line lead 32 and the adjacent conductive step 21; specifically, it can be the insulating step 22 above or below the conductive step 21 connected to the second type signal line lead 32, or it can be the insulating steps 22 on both sides of the conductive step 21 connected to the second type signal line lead 32.

[0088] In the embodiment of the present disclosure, according to the distance between the insulating step 22 corresponding to the signal line lead 3 and the substrate 1, the plurality of signal line leads 3 can be divided into two groups of first-type signal line leads 31 and second-type signal line leads 32. Among them, the conductive step 21 connected to the first-type signal line lead 31 and the corresponding insulating step 22 are located in the middle and lower area of ​​the step structure 2. This part of the conductive step 21 is prone to have a large parasitic capacitance load. Therefore, in the embodiment of the present disclosure, the thickness of the insulating step 22 corresponding to the first-type signal line lead 31 can be gradually reduced in the direction away from the substrate 1, for example, with a constant gradient; or, the thickness of the insulating step 22 corresponding to the first-type signal line lead 31 can be set to a relatively large constant value. The conductive step 21 connected to the second-type signal line lead 32 and the corresponding insulating step 22 are located in the middle and upper area of ​​the stepped structure 2. The parasitic capacitance load of this part of the conductive step 21 is relatively small. Therefore, the thickness of the insulating step 22 corresponding to the second-type signal line lead 32 may not be adjusted in the embodiment of the present disclosure, for example, it may be maintained at a small constant value; or, the thickness of the insulating step 22 corresponding to the second-type signal line lead 32 may gradually decrease in the direction away from the substrate 1, for example, decrease with a constant gradient.

[0089] In addition, it can be understood that among the thicknesses of the insulating steps 22 corresponding to multiple first-type signal line leads 31 and multiple second-type signal line leads 32, the minimum thickness of the insulating step 22 corresponding to the first-type signal line lead 31 should be greater than the maximum thickness of the insulating step 22 corresponding to the second-type signal line lead 32.

[0090] It should be added that, in some examples, the ratio of the number of stacked layers of the first-type signal line leads 31 corresponding to the insulating steps 22 to the number of stacked layers of the second-type signal line leads 32 corresponding to the insulating steps 22 may range from 1:1 to 3:1.

[0091] For example, the ratio of the number of stacked layers of the first-type signal line leads 31 corresponding to the insulating steps 22 to the number of stacked layers of the second-type signal line leads 32 corresponding to the insulating steps 22 is 1:1, 2:1 or 3:1.

[0092] For other possible implementations, see Fig. 9 The thickness of each insulating step 22 is the same, and the dielectric constant of each insulating step 22 gradually increases in a direction away from the substrate 1.

[0093] By way of example, the materials of the insulating steps 22 are different.

[0094] It can be understood that the parasitic capacitance is proportional to the dielectric constant k of the insulating step 22 corresponding to the conductive step 21. In the embodiment of the present disclosure, each conductive step 21 of the stepped structure 2 is stacked according to the matching requirements, and the parasitic capacitance of each conductive step 21 can be adjusted accordingly by adjusting the dielectric constant k (for example, material) of each insulating step 22, so as to achieve the effect of adjusting the parasitic capacitance load of each signal line lead 3. In this way, compared with the related art, the embodiment of the present disclosure gradually increases the dielectric constant k of each insulating step 22 in the direction away from the substrate 1, which is conducive to relatively reducing the parasitic capacitance of the conductive step 21 on the side close to the substrate 1, and relatively increasing the parasitic capacitance of the conductive step 21 on the side away from the substrate 1, so as to achieve the balance of the parasitic capacitance load of each layer of the conductive step 21 in the stepped structure 2, thereby avoiding the parasitic capacitance load of each layer of the conductive step 21 having a large difference due to the different physical parameters of each layer of the conductive step 21.

[0095] It should be added that, in some embodiments, the thickness and / or width of each conductive step 21 in the stepped structure 2 is the same or substantially the same. In this way, it is easy to adjust the parasitic capacitance of the corresponding conductive step 21 by only determining the thickness or dielectric constant of the insulating step 22 .

[0096] Here, the thickness of the conductive step 21 is the dimension of the conductive step 21 in a direction perpendicular to the substrate 1. The width of the conductive step 21 is the dimension of the conductive step 21 in a direction parallel to the substrate 1 and perpendicular to its extension direction.

[0097] For example, see Figure 1 , the thickness of each conductive step 21 in the stepped structure 2 is the same or substantially the same.

[0098] For example, see Figure 2 , the widths of the conductive steps 21 in the stepped structure 2 are the same or substantially the same.

[0099] For example, see Figure 4 , the thickness and width of each conductive step 21 in the stepped structure 2 are the same or substantially the same.

[0100] In some embodiments, the maximum parasitic capacitance load among the parasitic capacitance loads of the signal line leads 3 is less than or equal to 9 fF.

[0101] In summary, please refer to Fig.10 In (a) and (b), in some embodiments of the present disclosure, taking the stacking number of 64 layers of conductive steps 21 in the stepped structure 2 as an example, different insulating step 22 settings are adopted to verify the parasitic capacitance load of each signal line lead 3 in the three-dimensional memory.

[0102] See also Fig.10 As shown in FIG. 1 (a), in the first method, the thickness of each insulating step 22 remains the same, for example, 50 nm.

[0103] In method 2, the maximum thickness of each insulating step 22 is 200nm; and the thickness of each insulating step 22 decreases gradually with a gradient of 10nm in the direction away from the substrate 1, and after the thickness of the corresponding insulating step 22 is reduced to 50nm, the thickness of other insulating steps 22 above the insulating step 22 (for example, the insulating step corresponding to the second type of signal line) is maintained at 50nm.

[0104] In method three, the maximum thickness of each insulating step 22 is 200nm; and the thickness of each insulating step 22 decreases gradually with a gradient of 5nm in the direction away from the substrate 1, and after the thickness of the corresponding insulating step 22 is reduced to 50nm, the thickness of other insulating steps 22 above the insulating step 22 (for example, the insulating step corresponding to the second type of signal line) is maintained at 50nm.

[0105] Accordingly, in the three-dimensional memory using the above-mentioned method 1, method 2 and method 3, the parasitic capacitance load of each conductive step 21 in the three-dimensional memory can be detected and obtained respectively. Fig.10 As shown in Figure (b).

[0106] See also Fig.10 As shown in FIG. 2( b ), in the three-dimensional memory using the above-mentioned method 1, the parasitic capacitance load of each conductive step 21 decreases linearly in the direction away from the substrate 1 ; and the maximum value of the parasitic capacitance load of each conductive step 21 is about 15 fF.

[0107] In the three-dimensional memory using the second method, the parasitic capacitance load of each conductive step 21 increases first and then decreases in the direction away from the substrate 1; and the maximum value of the parasitic capacitance load of each conductive step 21 is about 12 fF.

[0108] In the three-dimensional memory using the third method, the parasitic capacitance load of each conductive step 21 increases first and then decreases in the direction away from the substrate 1; and the maximum value of the parasitic capacitance load of each conductive step 21 is about 9 fF.

[0109] From the above, the more layers of insulating steps 22 with adjusted thickness in the three-dimensional memory, the smaller the maximum difference between the parasitic capacitance loads of the corresponding conductive steps 21, for example, can be less than or equal to 9fF. The embodiments provided in the embodiments of the present disclosure can effectively balance the parasitic capacitance loads of the conductive steps 21 in the stepped structure 2 to reduce the maximum value of the parasitic capacitance load.

[0110] In addition, it can be understood that the driving capability of the three-dimensional memory usually depends on the parasitic capacitance of the conductive step 21 (such as the common bit line CBL). After reducing the maximum parasitic capacitance load and effectively balancing the parasitic capacitance loads of each conductive step 21, the embodiment of the present disclosure can effectively improve the performance of the three-dimensional memory, for example, it is beneficial to improve the storage capacity and storage density of the three-dimensional memory.

[0111] Some embodiments of the present disclosure also provide a method for preparing a three-dimensional memory, which is used to prepare the three-dimensional memory in some of the above embodiments. The preparation method also has the technical advantages of the above three-dimensional memory. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0112] In some embodiments, a method for preparing a three-dimensional memory includes the following steps.

[0113] S100, in the peripheral area of ​​the substrate, a plurality of conductive steps and a plurality of insulating steps are alternately stacked in a direction perpendicular to the substrate to obtain a stepped structure. The dielectric constant and thickness of each insulating step are determined to match the design distribution of the conductive steps and the insulating steps in the stepped structure, so that the maximum difference between the parasitic capacitance loads of each signal line lead is less than or equal to the target threshold.

[0114] S200 , forming signal line leads electrically connected to the conductive steps on the surface of each conductive step.

[0115] It should be noted that the dielectric constant and thickness of each insulating step are determined by matching the design distribution of the conductive step and the insulating step in the stepped structure, and can be determined by referring to the relevant structural features in some of the aforementioned embodiments. In addition, the thickness and thickness decreasing rate of each insulating step, as well as the dielectric constant of each insulating step, can be further optimized according to the total number of conductive steps in the stepped structure, the process limitations of the stepped structure, etc.

[0116] In some embodiments, the thickness of each insulating step gradually decreases in the direction away from the substrate. In addition, the thickness of each insulating step gradually decreases, which can be specifically expressed as: equal gradient decrease, step-by-step decrease, or group-by-group decrease. The dielectric constant of each insulating step is the same. In the embodiment of the present disclosure, the thickness of each insulating step gradually decreases in the direction away from the substrate, which makes it easy to form a thicker insulating step first, and then gradually reduce the thickness until the process limit thickness, thereby completing the preparation of the step structure.

[0117] In some other embodiments, the thickness of each insulating step is the same, and the dielectric constant of each insulating step gradually increases in a direction away from the substrate. For example, the materials of each insulating step are different.

[0118] In addition, it can be understood that in some embodiments, the method for preparing a three-dimensional memory further includes: forming a memory array structure in the array region of the substrate. The memory array structure can refer to the relevant descriptions in some of the above embodiments, which will not be described here.

[0119] It can be understood that in some embodiments, each layer structure in the storage array structure can generally be formed by alternately stacking multiple conductive pattern layers (including semiconductor layers) and multiple insulating pattern layers. Accordingly, the conductive steps in the step structure can be patterned based on the same conductive material layer as the conductive pattern layers in the storage array structure, and the insulating steps in the step structure can be patterned based on the same insulating material layer as the insulating pattern layers in the storage array structure.

[0120] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A three-dimensional memory, characterized in that: It has an array area and a peripheral area located beside the array area; The three-dimensional memory comprises: At least one stepped structure located in the peripheral area; the stepped structure comprises: a plurality of conductive steps and a plurality of insulating steps alternately stacked in a direction perpendicular to the substrate; A plurality of signal line leads are respectively located on the surface corresponding to the conductive steps and are electrically connected to the conductive steps; wherein the maximum difference between the parasitic capacitance loads of the signal line leads is less than or equal to the target threshold.

2. The three-dimensional memory according to claim 1, characterized in that: The parasitic capacitance loads of the signal line leads are equal or substantially equal.

3. The three-dimensional memory according to claim 1, characterized in that: Along the direction away from the substrate, the thickness of each insulating step gradually decreases.

4. The three-dimensional memory according to claim 3, characterized in that: Along the direction away from the substrate, the thickness of each insulating step decreases with equal gradient.

5. The three-dimensional memory according to claim 4, characterized in that: The difference in thickness between any two adjacent insulating steps ranges from 5 nm to 10 nm.

6. The three-dimensional memory according to any one of claims 3 to 5, characterized in that: The dielectric constants of the insulating steps are the same.

7. The three-dimensional memory according to claim 1, characterized in that: The multiple signal line leads include a first type of signal line leads and a second type of signal line leads; wherein the insulating step corresponding to the first type of signal line leads is located on the side of the insulating step corresponding to the second type of signal line leads close to the substrate; the thickness of the insulating step corresponding to the first type of signal line leads is greater than the thickness of the insulating step corresponding to the second type of signal line leads.

8. The three-dimensional memory according to claim 1, characterized in that: The thickness of each of the insulating steps is the same, and the dielectric constant of each of the insulating steps gradually increases in a direction away from the substrate.

9. The three-dimensional memory according to claim 1, characterized in that: The thickness and / or width of each of the conductive steps are the same or substantially the same.

10. The three-dimensional memory according to claim 1, characterized in that: The maximum parasitic capacitance load among the parasitic capacitance loads of the signal line leads is less than or equal to 9 fF.

11. A method for preparing a three-dimensional memory, characterized in that: include: In the peripheral region of the substrate, a plurality of conductive steps and a plurality of insulating steps are formed which are alternately stacked in a direction perpendicular to the substrate to obtain a stepped structure; A signal line lead electrically connected to the conductive step is formed on the surface of each of the conductive steps; wherein the dielectric constant and thickness of each of the insulating steps are determined to match the design distribution of the conductive step and the insulating step in the stepped structure so that the maximum difference between the parasitic capacitance loads of each of the signal line leads is less than or equal to the target threshold.

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