Semiconductor device

Abstract

A semiconductor device includes a gate electrode structure, a memory channel structure, and a contact plug. The gate electrode structure includes gate electrodes sequentially stacked on the substrate in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other. Each gate electrode extends in a second direction substantially parallel to the upper surface of the substrate. A memory channel structure extends through the gate electrode structure. The contact plug partially extends through the gate electrode structure to contact an upper surface of a first gate electrode among the gate electrodes. The contact plug is electrically insulated from the second gate electrode over the first gate electrode. At least a portion of the contact plug has a width that decreases in a stepped manner from its top toward its bottom in a first direction.

Description

Technical Field

[0001] The present inventive concept relates to semiconductor devices and more particularly to vertical memory devices. Background Art

[0002] In electronic systems that require data storage, high-capacity semiconductor devices that can store high-capacity data are required. Therefore, a method of increasing the data storage capacity of a semiconductor device has been studied. For example, a semiconductor device including a memory cell that can be stacked three-dimensionally has been proposed.

[0003] There is a need to develop a method of efficiently forming a contact plug for transferring an electrical signal to a memory cell in a semiconductor device. Summary of the invention

[0004] Some example embodiments provide a semiconductor device having improved electrical characteristics.

[0005] According to example embodiments, a semiconductor device may include a gate electrode structure, a memory channel structure, and a contact plug. The gate electrode structure may be on a substrate and may include gate electrodes sequentially stacked and spaced apart from each other in a first direction, the first direction being substantially perpendicular to the upper surface of the substrate. Each gate electrode may extend in a second direction, the second direction being substantially parallel to the upper surface of the substrate. The memory channel structure may extend through the gate electrode structure. The contact plug may partially extend through the gate electrode structure to contact the upper surface of a first gate electrode among the gate electrodes. The contact plug may extend through a second gate electrode located above the first gate electrode but be electrically insulated from the second gate electrode. At least a portion of the contact plug may have a width that decreases in a stepwise manner from its top toward the bottom in the first direction.

[0006] According to example embodiments, a semiconductor device may include a gate electrode structure, a memory channel structure, an insulating interlayer, and a contact plug. The gate electrode structure may be on a substrate and may include gate electrodes sequentially stacked and spaced apart from each other in a first direction, the first direction being substantially perpendicular to an upper surface of the substrate. Each gate electrode may extend in a second direction, the second direction being substantially parallel to an upper surface of the substrate. The memory channel structure may extend through the gate electrode structure. The insulating interlayer may be disposed on the gate electrode structure and the memory channel structure. The contact plug may extend through the insulating interlayer and a portion of the gate electrode structure to contact an upper surface of a first gate electrode of the gate electrodes. The contact plug may extend through a second gate electrode of the gate electrodes but be electrically insulated from the second gate electrode, the second gate electrode being above the first gate electrode of the gate electrodes. The contact plug may include a first lower portion and a second lower portion stacked in the first direction and extending through the portion of the gate electrode structure, and an upper portion on the second lower portion and extending through the insulating interlayer. Each of the first lower portion and the second lower portion may have a width that decreases in a stepwise manner from its top toward its bottom in the first direction.

[0007] According to example embodiments, a semiconductor device may include a gate electrode structure, a memory channel structure, a support structure, an insulating interlayer, and a first contact plug. The gate electrode structure may include a first gate electrode and a second gate electrode. The first gate electrodes may be on a first region and a second region of a substrate and may be sequentially stacked and spaced apart from each other in a first direction, the first direction being substantially perpendicular to an upper surface of the substrate. Each gate electrode may extend in a second direction, the second direction being substantially parallel to an upper surface of the substrate. The second gate electrode may be above the first gate electrode on a portion of the first region and the second region of the substrate adjacent to the first region. The memory channel structure may extend through the gate electrode structure on the first region of the substrate. The support structure may extend through the first gate electrode on the second region of the substrate. The insulating interlayer may be on the substrate and may cover the gate electrode structure, the memory channel structure, and the support structure. Each first contact plug may extend through the insulating interlayer and at least one first gate electrode to contact a first first gate electrode among the first gate electrodes. Each first contact plug may extend through a second first gate electrode among the first gate electrodes but be electrically insulated from the second first gate electrode, the second first gate electrode being located above the first first gate electrode among the first gate electrodes. Each of the first contact plugs may include an upper portion extending through the insulating interlayer and a lower portion below the upper portion. At least a portion of the lower portion may have a width that decreases from a top toward a bottom thereof in a first direction.

[0008] In a method of manufacturing a semiconductor device according to example embodiments, a process for forming a contact plug that may contact a corresponding one of gate electrodes to be electrically connected thereto may be simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 8 are a top view and a cross-sectional view illustrating a method of forming a hole according to some example embodiments.

[0010] Figures 9 to 12 are a top view and a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0011] Figures 13 to 46 are a top view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0012] Fig.47 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0013] Figures 48 to 55 It shows the manufacturing Fig.47 A cross-sectional view of a method for a semiconductor device. DETAILED DESCRIPTION

[0014] With reference to the accompanying drawings, the above and other aspects and features of the semiconductor device and the method for manufacturing the same according to the example embodiments will become readily understood from the detailed description below. It will be understood that although the terms "first", "second" and / or "third" may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structures and / or processes, these various materials, layers, regions, pads, electrodes, patterns, structures and / or processes should not be limited by these terms. These terms are only used to distinguish one material, layer, region, pad, electrode, pattern, structure or process from another material, layer, region, pad, electrode, pattern, structure or process. Therefore, "first", "second" and / or "third" may be selectively or interchangeably used for each material, layer, region, electrode, pad, pattern, structure or process, respectively.

[0015] Hereinafter, a vertical direction substantially perpendicular to the upper surface of the substrate may be referred to as a first direction D1, and two directions intersecting each other among horizontal directions substantially parallel to the upper surface of the substrate may be referred to as a second direction D2 and a third direction D3, respectively. In some example embodiments, the second direction D2 and the third direction D3 may be substantially perpendicular to each other. In the accompanying drawings, each of the first to third directions D1, D2, and D3 may include both the direction indicated by the arrow and the direction opposite thereto.

[0016] Although the terms "same," "equal," or "equivalent" are used in the description of example embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0017] When the terms "about," "substantially," or "approximately" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about," "substantially," or "approximately" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but rather that the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially," it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0018] As used herein, expressions such as "at least one of" when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0019] Figures 1 to 8 are top views and cross-sectional views illustrating methods of forming holes according to some example embodiments. For example, Figure 1 , Figure 3 , Figure 5 and Figure 7 It is a top view. Figure 2 , Figure 4 , Figure 6 and Figure 8 They are respectively cross-sectional views taken along line CC' of the corresponding top view.

[0020] refer to Figure 1 and Figure 2 , the insulating layers 20 and the sacrificial layers 30 may be alternately and repeatedly stacked on the substrate 10 to form a mold layer.

[0021] The substrate 10 may include a semiconductor material (e.g., silicon, germanium, silicon-germanium, etc.) or a III-V compound semiconductor (e.g., GaP, GaAs, GaSb, etc.). In some example embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0022] In some example embodiments, the insulating layer 20 may include oxide (eg, silicon oxide), and the sacrificial layer 30 may include a material having an etch selectivity with respect to the insulating layer 20 (eg, insulating nitride such as silicon nitride).

[0023] A first photoresist pattern can be formed on the uppermost sacrificial layer 30 among the sacrificial layers 30, the uppermost sacrificial layer 30 among the sacrificial layers 30 can be set at the uppermost level among the sacrificial layers 30, and the first photoresist pattern can be used as an etching mask to perform a first etching process to partially remove the two upper layers of the mold layer, that is, the uppermost sacrificial layer 30 among the sacrificial layers 30 and the uppermost insulating layer 20 among the insulating layers 20 (the uppermost insulating layer 20 among the insulating layers 20 can be set at the uppermost level among the insulating layers 20), and thus the first to eighth holes 41, 42, 43, 44, 45, 46, 47 and 48 can be formed to expose the upper surface of the sacrificial layer 30 among the sacrificial layers 30 (the sacrificial layer 30 is set at the second level from the top).

[0024] In some example embodiments, each of the first to eighth holes 41 , 42 , 43 , 44 , 45 , 46 , 47 , and 48 may have a first width W1 in the horizontal direction and a first depth P1 from an upper surface of an uppermost sacrificial layer 30 among the sacrificial layers 30 in the first direction D1 .

[0025] refer to Figure 3 and Figure 4 , the topmost sacrificial layer 30 among the sacrificial layers 30, the sacrificial layers 30 disposed at the second level from the top among the sacrificial layers 30, the topmost insulating layer 20 among the insulating layers 20, and the insulating layer 20 disposed at the second level from the top among the insulating layers 20 can be partially removed to form the ninth to twelfth holes 52, 54, 56 and 58, the ninth to twelfth holes 52, 54, 56 and 58 are spaced apart from each other in the second direction D2 and expose the upper surface of a sacrificial layer 30 among the sacrificial layers 30 (the sacrificial layer 30 is disposed at the third level from the top among the sacrificial layers 30).

[0026] In some example embodiments, the ninth to twelfth holes 52, 54, 56 and 58 can be formed by performing a second etching process on two upper layers in the mold layer (i.e., the uppermost sacrificial layer 30 in the sacrificial layer 30 and the uppermost insulating layer 20 in the insulating layer 20) and two upper layers below the second hole 42, the fourth hole 44, the sixth hole 46 and the eighth hole 48 (i.e., the sacrificial layer 30 in the sacrificial layer 30 disposed at the second level from the top and the insulating layer 20 in the insulating layer 20 disposed at the second level from the top) using a second photoresist pattern as an etching mask, wherein the etching mask can expose portions of the upper surface of the uppermost sacrificial layer 30 in the sacrificial layer 30 adjacent to the even-numbered holes (i.e., the second hole 42, the fourth hole 44, the sixth hole 46 and the eighth hole 48) in the first to eighth holes 41, 42, 43, 44, 45, 46, 47 and 48.

[0027] Therefore, each of the ninth to twelfth holes 52, 54, 56, and 58 may include a lower portion having a first width W1 and extending through a sacrificial layer 30 disposed at a second level from above among the sacrificial layers 30 and an insulating layer 20 disposed at a second level from above among the insulating layers 20, and an upper portion having a second width W2 greater than the first width W1 and extending through an uppermost sacrificial layer 30 among the sacrificial layers 30 and an uppermost insulating layer 20 among the insulating layers 20. Each of the ninth to twelfth holes 52, 54, 56, and 58 may have a second depth P2 from an upper surface of an uppermost sacrificial layer 30 among the sacrificial layers 30 in the first direction D1, and the second depth P2 may be greater than the first depth P1.

[0028] When forming the ninth to twelfth holes 52 , 54 , 56 and 58 , the first hole 41 , the ninth hole 52 , the third hole 43 , the tenth hole 54 , the fifth hole 45 , the eleventh hole 56 , the seventh hole 47 and the twelfth hole 58 may be formed to be spaced apart from each other in this order in the second direction D2 .

[0029] refer to Figure 5 and Figure 6 , the topmost sacrificial layer 30 among the sacrificial layers 30, the sacrificial layers 30 among the sacrificial layers 30 respectively arranged at the second level, the third level and the fourth level from the top among the sacrificial layers 30, the topmost insulating layer 20 among the insulating layers 20, and the insulating layers 20 among the insulating layers 20 respectively arranged at the second level, the third level and the fourth level from the top among the insulating layers 20 can be partially removed to form the thirteenth to sixteenth holes 63, 64, 67 and 68, and the thirteenth to sixteenth holes 63, 64, 67 and 68 are spaced apart from each other in the second direction D2 and expose the upper surface of the sacrificial layer 30 among the sacrificial layers 30 arranged at the fourth level from the top or the upper surface of the sacrificial layer 30 among the sacrificial layers 30 arranged at the fifth level from the top among the sacrificial layers 30.

[0030] In some example embodiments, the thirteenth to sixteenth holes 63, 64, 67, and 68 may be etched by using the third photoresist pattern as an etching mask to respectively etch two upper layers of the mold layer (that is, the uppermost sacrificial layer 30 of the sacrificial layers 30 and the uppermost insulating layer 20 of the insulating layers 20) and two upper layers below the third hole 43, the tenth hole 54, the seventh hole 47, and the twelfth hole 58 (that is, the sacrificial layers 30 of the sacrificial layers 30 respectively disposed at the third level and the fourth level from the top and the insulating layer 20 respectively disposed at the third level and the fourth level from the top among the sacrificial layers 30). The insulating layer 20 is disposed at a third level and a fourth level from the top in the insulating layer 20 to form a third etching process, and the etching mask can expose the upper surface of the uppermost sacrificial layer 30 in the sacrificial layer 30 and the portions adjacent to the third hole, the fourth hole, the seventh hole and the eighth hole among the first hole 41, the ninth hole 52, the third hole 43, the tenth hole 54, the fifth hole 45, the eleventh hole 56, the seventh hole 47 and the twelfth hole 58 spaced apart from each other in the second direction D2 (that is, the third hole 43, the tenth hole 54, the seventh hole 47 and the twelfth hole 58).

[0031] Therefore, each of the thirteenth hole 63 and the fifteenth hole 67 may include a lower portion having a first width W1 and extending through the sacrificial layers 30 disposed at the third level from the top among the sacrificial layers 30 and the insulating layers 20 disposed at the third level from the top among the insulating layers 20, and an upper portion having a third width W3 greater than the second width W2 and extending through the uppermost sacrificial layer 30 among the sacrificial layers 30, the sacrificial layers 30 disposed at the second level from the top among the sacrificial layers 30, the uppermost insulating layer 20 among the insulating layers 20, and the insulating layers 20 disposed at the second level from the top among the insulating layers 20. Each of the thirteenth hole 63 and the fifteenth hole 67 may have a third depth P3 from the upper surface of the uppermost sacrificial layer 30 among the sacrificial layers 30 in the first direction D1, and the third depth P3 may be greater than the second depth P2.

[0032] In addition, each of the fourteenth hole 64 and the sixteenth hole 68 may include a lower portion, a middle portion and an upper portion, the lower portion having a first width W1 and extending through the sacrificial layer 30 in the sacrificial layer 30 set at the fourth level from the top and the insulating layer 20 in the insulating layer 20 set at the fourth level from the top, the middle portion having a second width W2 and extending through the sacrificial layer 30 in the sacrificial layer 30 set at the third level from the top and the insulating layer 20 in the insulating layer 20 set at the third level from the top, and the upper portion having a third width W3 greater than the second width W2 and extending through the topmost sacrificial layer 30 in the sacrificial layer 30 and the sacrificial layer 30 in the sacrificial layer 30 set at the second level from the top, the topmost insulating layer 20 in the insulating layer 20 and the insulating layer 20 in the insulating layer 20 set at the second level from the top. Each of the fourteenth hole 64 and the sixteenth hole 68 may have a fourth depth P4 from an upper surface of an uppermost one of the sacrificial layers 30 in the first direction D1 , and the fourth depth P4 may be greater than the third depth P3 .

[0033] When forming the thirteenth to sixteenth holes 63, 64, 67 and 68, the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the fifth hole 45, the eleventh hole 56, the fifteenth hole 67 and the sixteenth hole 68 may be formed to be spaced apart from each other in this order in the second direction D2.

[0034] refer to Figure 7 and Figure 8 , the topmost sacrificial layer among the sacrificial layers 30, the sacrificial layers 30 among the sacrificial layers 30 respectively arranged at the second to fifth levels, the sacrificial layers 30 among the sacrificial layers 30 respectively arranged at the sixth to eighth levels from the top, the topmost insulating layer 20 among the insulating layers 20, the insulating layers 20 among the insulating layers 20 respectively arranged at the second to fourth levels, and the insulating layers 20 among the insulating layers 20 respectively arranged at the fifth to eighth levels from the top can be partially removed to form the seventeenth to twentieth holes 75, 76, 77 and 78, and the seventeenth to twentieth holes 75, 76, 77 and 78 are spaced apart from each other in the second direction D2 and expose the upper surface of the sacrificial layer 30 set at one of the sixth to ninth levels among the sacrificial layers 30.

[0035] In some example embodiments, the seventeenth to twentieth holes 75, 76, 77, and 78 may be etched by using the fourth photoresist pattern as an etching mask to etch two upper layers in the mold layer (e.g., the uppermost sacrificial layer 30 in the sacrificial layers 30 and the uppermost insulating layer 20 in the insulating layers 20) and two upper layers below the fifth hole 45, the eleventh hole 56, the fifteenth hole 67, and the sixteenth hole 68 (e.g., the sacrificial layers in the sacrificial layers 30 respectively disposed at the second to fifth levels from the top and the sacrificial layers in the insulating layers 20 respectively disposed at the insulating layers 20). A fourth etching process is used to form the insulating layer 20 at the second to fifth levels from the top of the insulating layer 20, and the etching mask can expose portions of the upper surface of the uppermost sacrificial layer 30 in the sacrificial layer 30 that are adjacent to the fifth hole 45, the eleventh hole 56, the fifteenth hole 67 and the sixteenth hole 68, respectively (for example, the fifth hole, the sixth hole, the seventh hole and the eighth hole among the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the fifth hole 45, the eleventh hole 52, the fifteenth hole 63 and the sixteenth hole 68 spaced apart from each other in the second direction D2).

[0036] Therefore, the seventeenth hole 75 may include a lower portion having a first width W1 and extending through the sacrificial layers 30 disposed at the fifth level from the top among the sacrificial layers 30 and the insulating layers 20 disposed at the fifth level from the top among the insulating layers 20, and an upper portion having a fourth width W4 greater than the third width W3 and extending through the uppermost sacrificial layer 30 among the sacrificial layers 30, the sacrificial layers 30 disposed at the second to fourth levels from the top among the sacrificial layers 30, the uppermost insulating layer 20 among the insulating layers 20, and the insulating layers 20 disposed at the second to fourth levels from the top among the insulating layers 20. The seventeenth hole 75 may have a fifth depth P5 from the upper surface of the uppermost sacrificial layer 30 among the sacrificial layers 30 in the first direction D1, and the fifth depth P5 may be greater than the fourth depth P4.

[0037] In addition, the eighteenth hole 76 may include a lower portion, a middle portion, and an upper portion, the lower portion having a first width W1 and extending through the sacrificial layer 30 in the sacrificial layer 30 that is set at the sixth level from the top and the insulating layer 20 in the insulating layer 20 that is set at the sixth level from the top, the middle portion having a second width W2 and extending through the sacrificial layer 30 in the sacrificial layer 30 that is set at the fifth level from the top and the insulating layer 20 in the insulating layer 20 that is set at the fifth level from the top, and the upper portion having a fourth width W4 and extending through the topmost sacrificial layer 30 in the sacrificial layer 30, the sacrificial layers 30 in the sacrificial layers 30 that are respectively set at the second to fourth levels from the top, the topmost insulating layer 20 in the insulating layer 20, and the insulating layers in the insulating layer 20 that are respectively set at the second to fourth levels from the top. The eighteenth hole 76 may have a sixth depth P6 from the upper surface of the uppermost sacrificial layer 30 among the sacrificial layers 30 in the first direction D1 , and the sixth depth P6 may be greater than the fifth depth P5 .

[0038] In addition, the nineteenth hole 77 may include a lower portion, a middle portion, and an upper portion, the lower portion having a first width W1 and extending through the sacrificial layer 30 in the sacrificial layer 30 that is set at the seventh level from the top and the insulating layer 20 in the insulating layer 20 that is set at the seventh level from the top, the middle portion having a third width W3 and extending through the sacrificial layer 30 in the sacrificial layer 30 that is respectively set at the fifth level and the sixth level from the top and the insulating layer 20 in the insulating layer 20 that is respectively set at the fifth level and the sixth level from the top, the upper portion having a fourth width W4 and extending through the topmost sacrificial layer 30 in the sacrificial layer 30, the sacrificial layers 30 in the sacrificial layer 30 that are respectively set at the second to fourth levels from the top, the topmost insulating layer 20 in the insulating layer 20, and the insulating layer 20 in the insulating layer 20 that are respectively set at the second to fourth levels from the top. The nineteenth hole 77 may have a seventh depth P7 from the upper surface of the uppermost sacrificial layer 30 among the sacrificial layers 30 in the first direction D1 , and the seventh depth P7 may be greater than the sixth depth P6 .

[0039] In addition, the twentieth hole 78 may include a lower portion having a first width W1 and extending through one of the sacrificial layers 30 disposed at an eighth level from the top among the sacrificial layers 30 and one of the insulating layers 20 disposed at an eighth level from the top among the insulating layers 20, a first middle portion having a second width W2 and extending through one of the sacrificial layers 30 disposed at a seventh level from the top among the sacrificial layers 30 and one of the insulating layers 20 disposed at a seventh level from the top among the insulating layers 20, and an upper portion, The second middle portion has a third width W3 and extends through the sacrificial layers 30 respectively disposed at the fifth and sixth levels from the top among the sacrificial layers 30 and the insulating layers 20 respectively disposed at the fifth and sixth levels from the top among the insulating layers 20, and the upper portion has a fourth width W4 and extends through the uppermost sacrificial layer among the sacrificial layers 30, the sacrificial layers respectively disposed at the second to fourth levels from the top among the sacrificial layers 30, the uppermost insulating layer 20 among the insulating layers 20, and the insulating layers 20 respectively disposed at the second to fourth levels from the top among the insulating layers 20. The twentieth hole 78 may have an eighth depth P8 from the upper surface of the uppermost sacrificial layer 30 among the sacrificial layers 30 in the first direction D1, and the eighth depth P8 may be greater than the seventh depth P7.

[0040] When forming the seventeenth to twentieth holes 75, 76, 77 and 78, the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the seventeenth hole 75, the eighteenth hole 76, the nineteenth hole 77 and the twentieth hole 78 can be formed to be spaced apart from each other in this order in the second direction D2.

[0041] Through the above process, the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the seventeenth hole 75, the eighteenth hole 76, the nineteenth hole 77 and the twentieth hole 78 (each of which may partially extend through the mold layer) may be formed to be spaced apart from each other in the second direction D2. The first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the seventeenth hole 75, the eighteenth hole 76, the nineteenth hole 77 and the twentieth hole 78 may respectively expose different sacrificial layers disposed at different levels in the sacrificial layer 30, and may respectively have different depths P1, P2, P3, P4, P5, P6, P7 and P8.

[0042] Therefore, when the sacrificial layer 30 is replaced with a gate electrode comprising a conductive material, insulating spacers are formed on the side walls of the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the seventeenth hole 75, the eighteenth hole 76, the nineteenth hole 77 and the twentieth hole 78, and contact plugs are formed therein, each of which can contact a corresponding gate electrode among the gate electrodes to be electrically connected thereto, and may not be electrically connected to other gate electrodes among the gate electrodes arranged at other levels.

[0043] In some example embodiments, each of the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the seventeenth hole 75, the eighteenth hole 76, the nineteenth hole 77, and the twentieth hole 78 may have a width in the horizontal direction, which may decrease from the highest level toward the lowest level in the first direction D1.

[0044] In some example embodiments, a first etching process may be performed to form eight holes (e.g., first to eighth holes 41, 42, 43, 44, 45, 46, 47, and 48) extending through an uppermost sacrificial layer 30 among the sacrificial layers 30 and an uppermost insulating layer 20 among the insulating layers 20, a second etching process for partially removing the sacrificial layer 30 at one level among the sacrificial layers 30 and the insulating layer 20 at one level among the insulating layers 20 may be performed, and a second etching process for partially removing the sacrificial layer 30 at two levels among the sacrificial layers 30 and the insulating layer 20 at two levels may be performed. The third etching process of the insulating layer 20 at two levels in the insulating layer 20, respectively, and the fourth etching process for partially removing the sacrificial layer 30 at four levels in the sacrificial layer 30 and the insulating layer 20 at four levels in the insulating layer 20, respectively, may be performed, so that eight holes (e.g., the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the seventeenth hole 75, the eighteenth hole 76, the nineteenth hole 77, and the twentieth hole 78) spaced from each other in the second direction D2 and respectively exposing the upper surface of the sacrificial layer 30 at different levels may be formed. However, the inventive concept may not be limited thereto.

[0045] For example, eight holes (e.g., the first hole 41, the ninth hole 52, the thirteenth hole 63, the fourteenth hole 64, the seventeenth hole 75, the eighteenth hole 76, the nineteenth hole 77, and the twentieth hole 78) can be defined as a hole group (e.g., a group of holes), eight hole groups (e.g., eight groups of holes) spaced apart from each other in the second direction D2 can be formed to partially pass through the mold layer, and a process substantially the same as or similar to the second to fourth etching processes can be performed on the hole group, so that 64 holes that respectively expose the upper surface of the sacrificial layer 30 at different levels in the sacrificial layer 30 can be formed to be spaced apart from each other in the second direction D2.

[0046] Therefore, the 8n The upper surface of the sacrificial layer 30 is 8 n The number of holes (n is a natural number) may be formed to be spaced apart from each other in the second direction D2. In some example embodiments, by changing the number of holes included in each hole group or the number of hole groups, the 2 holes at different levels are exposed. n The upper surface of the sacrificial layer 30 is 2 n Holes (n is a natural number) may be formed to be spaced apart from each other in the second direction D2.

[0047] Figures 9 to 12 are a top view and a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0048] In particular, Fig. 9 and Fig.10 It is a top view. Fig.11 It is along Fig.10 A cross-sectional view taken along line AA' of Fig.12 It is along Fig.10 A cross-sectional view taken along line BB'. Figures 10 to 12 About Fig. 9 A graph of region X.

[0049] Fig.10 The upper wiring and upper via are not shown to avoid complexity of the drawing.

[0050] refer to Figures 9 to 12 The semiconductor device may include a lower circuit pattern, a common source plate (CSP), a gate electrode structure, first to third dividing patterns 610, 615 and 660, a first supporting structure 350 and a second supporting structure 430, a first memory channel structure 550 and a second memory channel structure 720, first to ninth upper contact plugs 761, 762, 763, 764, 765, 766, 767, 768 and 769, first to third spacers 305, 375 and 455, a through via 790, first to fourth upper vias 810, 820, 825 and 830, and first to fourth upper wirings 850, 860, 865 and 870.

[0051] In addition, the semiconductor device may include a sacrificial layer structure 250, a supporting layer 260, a supporting pattern 265, a channel connection pattern 580, a second barrier pattern 590, a first insulating pattern 264 and a second insulating pattern 275, first to tenth insulating interlayers 140, 190, 390, 470, 560, 630, 730, 770, 800 and 840, an etching stop layer 640 and first to third mold layers.

[0052] The substrate 100 may include a semiconductor material (eg, silicon, germanium, silicon-germanium, etc.) or a III-V compound semiconductor (eg, GaP, GaAs, GaSb, etc.) In some example embodiments, the substrate 100 may be a SOI substrate or a GOI substrate.

[0053] The substrate 100 may include a first region I, a second region II, and a third region III. In some example embodiments, the first region I of the substrate 100 may be a cell array region in which a memory cell is formed, the second region II of the substrate 100 may be an extension region in which an upper contact plug for transmitting an electrical signal to the memory cell is formed, and the first region I and the second region II may form a cell region together. The third region III of the substrate 100 may be a peripheral circuit region in which a peripheral circuit pattern is formed. In some example embodiments, the second region II may surround the first region I, or may be disposed at each of the opposite sides in the second direction D2 of the first region I. The third region III may surround the first region I and the second region II.

[0054] In some example embodiments, the semiconductor device may have a cell-on-periphery (COP) structure. That is, a lower circuit pattern may be disposed on the substrate 100, and a memory cell, an upper contact plug, and an upper circuit pattern may be disposed above the lower circuit pattern. The lower circuit pattern may include, for example, a lower transistor, a lower contact plug, a lower wiring, a lower via, etc. However, the inventive concept may not be limited thereto, and the semiconductor device may not have a COP structure.

[0055] For example, the lower transistor may include a lower gate structure 130 on the substrate 100 and impurity regions 105 at upper portions of the substrate 100 adjacent to the lower gate structure 130. The impurity regions 105 may serve as a source and a drain, respectively. The lower gate structure 130 may include a lower gate insulating pattern 110 and a lower gate electrode 120 sequentially stacked on the substrate 100.

[0056] The first insulating interlayer 140 may be disposed on the substrate 100 and may cover the lower transistor. The first lower contact plug 150 may extend through the first insulating interlayer 140 to contact each of the impurity regions 105. The second lower contact plug may extend through the first insulating interlayer 140 to contact the lower gate electrode 120.

[0057] The first lower wiring 160 may be disposed on the first insulating interlayer 140 and may contact an upper surface of the first lower contact plug 150. The lower via 170 and the second lower wiring 182 may be sequentially stacked on the first lower wiring 160. The third lower wiring 184 may be further disposed on the third region III of the substrate 100 at the same level as the second lower wiring 182.

[0058] The second insulating interlayer 190 may be disposed on the first insulating interlayer 140 , and may cover the first to third lower wirings 160 , 182 , and 184 and the lower via 170 .

[0059] The CSP 200 may be disposed on the second insulating interlayer 190. The CSP 200 may include, for example, polysilicon doped with n-type impurities. In some example embodiments, the CSP 200 may include a metal silicide layer and a polysilicon layer doped with n-type impurities stacked in sequence. The metal silicide layer may include, for example, tungsten silicide.

[0060] The sacrificial layer structure 250 , the channel connection pattern 580 , the support layer 260 , and the support pattern 265 may be disposed on the CSP 200 .

[0061] The channel connection pattern 580 may be disposed on the first region I of the substrate 100 and may include an air gap therein. The sacrificial layer structure 250 may be disposed on the second region II of the substrate 100 .

[0062] The channel connection pattern 580 may include polysilicon doped with n-type impurities or undoped polysilicon. The sacrificial layer structure 250 may include first to third sacrificial layers 220, 230, and 240 sequentially stacked in the first direction D1. Each of the first sacrificial layer 220 and the third sacrificial layer 240 may include an oxide (e.g., silicon oxide), and the second sacrificial layer 230 may include a nitride (e.g., silicon nitride).

[0063] Support layer 260 may be disposed on channel connection pattern 580 and sacrificial layer structure 250, and may also be disposed in first opening 261 extending through channel connection pattern 580 and sacrificial layer structure 250 to expose the upper surface of CSP 200. Hereinafter, a portion of the support layer disposed in first opening 261 may be referred to as support pattern 265.

[0064] The support pattern 265 may have various layouts in a top view. In some example embodiments, a plurality of support patterns 265 may be spaced apart from each other in the second direction D2 and the third direction D3 on the first region I of the substrate 100. In addition, the support pattern 265 may be on a portion of the second region II of the substrate 100 and surround the first region I of the substrate 100, and may have a rectangular ring shape in a top view. In addition, a plurality of support patterns 265 (each of which may extend in the second direction D2) may be spaced apart from each other in the third direction D3 on the second region II of the substrate 100.

[0065] Each of the support layer 260 and the support pattern 265 may include a material having an etch selectivity with respect to the first to third sacrificial layers 220 , 230 , and 240 , for example, polysilicon doped with n-type impurities.

[0066] The first insulating pattern 264 may be disposed on the third region III of the substrate 100 and may extend through the sacrificial layer structure 250 and the support layer 260 to contact the upper surface of the CSP 200. The first insulating pattern 264 may overlap the third lower wiring 184 in the first direction D1. The first insulating pattern 264 may include oxide (e.g., silicon oxide) or insulating nitride (e.g., silicon nitride).

[0067] The gate electrode structure may include gate electrodes, which may be respectively formed at a plurality of levels spaced apart from each other along the first direction D1 on the support layer 260 and the support pattern 265 , and each gate electrode may extend in the second direction D2 .

[0068] In some example embodiments, the gate electrode structure may include first and second gate electrodes 600 and 650 sequentially stacked in the first direction D1. The first gate electrodes 600 may be disposed at multiple levels, and the second gate electrode 650 may be disposed at a single level, or a plurality of second gate electrodes 650 may be disposed at multiple levels.

[0069] In some example embodiments, some of the first gate electrodes 600 may be used as ground select lines (GSL), other ones of the first gate electrodes 600 may be used as word lines, and still other ones of the first gate electrodes 600 may be used as GIDL gate electrodes (which may be used to erase data stored in the first memory channel structure 550 using a gate induced drain leakage (GIDL) phenomenon).

[0070] For example, the bottommost first gate electrode 600 among the first gate electrodes 600 and the first gate electrode 600 at the second level from the bottom among the first gate electrodes 600 can be used as GSLs, the first gate electrode 600 at the third level from the bottom among the first gate electrodes 600 among the first gate electrodes 600 can be a GIDL gate electrode, and the first gate electrodes 600 at other levels among the first gate electrodes 600 can be used as word lines, respectively.

[0071] The second gate electrode 650 may function as a string selection line (SSL).

[0072] The gate electrode 600 may include a gate conductive pattern and a gate barrier pattern covering a surface of the gate conductive pattern. The gate conductive pattern may include a metal having low resistance (e.g., tungsten, titanium, tantalum, platinum, etc.), and the gate barrier pattern may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0073] In some example embodiments, the second gate electrode 650 may include, for example, polysilicon doped with n-type impurities.

[0074] The second insulating pattern 275 may be disposed between adjacent ones of the first gate electrodes 600 in the first direction D1 and between the first gate electrode 600 and the supporting layer 260 or the supporting pattern 265. The second insulating pattern 275 may include oxide (eg, silicon oxide).

[0075] In some example embodiments, each of the first gate electrodes 600 included in the gate electrode structure may extend in the second direction D2 on the first region I and the second region II of the substrate 100, and the lengths of the first gate electrodes 600 stacked in the first direction D1 in the second direction D2 may be substantially the same as each other. The second gate electrode 650 included in the gate electrode structure may extend in the second direction D2 on portions of the first region I and the second region II of the substrate 100 adjacent to the first region I, and the length of the second gate electrode 650 in the second direction may be smaller than the length of the first gate electrode 600 in the second direction D2.

[0076] In some example embodiments, the thickness of each first gate electrode 600 in the first direction D1 may be substantially constant in the second direction D2, and thus, the thickness of each first gate electrode 600 at an end in the second direction D2 may be substantially the same as the thickness of the other portion thereof in the first direction D1.

[0077] In some example embodiments, the plurality of gate electrode structures may be spaced apart from each other in the third direction D3.The first to third mold layers may be disposed on the third region III of the substrate 100 and may contact each of the gate electrode structures.

[0078] For example, the first to third mold layers may be sequentially stacked in the first direction D1, and each of the first to third mold layers may include the second insulating layer 270 and the fourth sacrificial layer 280 alternately and repeatedly stacked in the first direction D1. The first spacer 305 may be interposed between the first mold layer and the second mold layer, and the second spacer 375 and the third insulating interlayer 390 may be interposed between the second mold layer and the third mold layer.

[0079] In some example embodiments, each second insulating layer 270 may be disposed at the same level as a corresponding one of the second insulating patterns 275 and may contact a sidewall of a corresponding one of the second insulating patterns 275. Each fourth sacrificial layer 280 may be disposed at the same level as a corresponding one of the first gate electrodes 600 and may contact a sidewall of the second barrier pattern 590.

[0080] The second insulating pattern 275 may include oxide (eg, silicon oxide), and the fourth sacrificial layer 280 may include insulating nitride (eg, silicon nitride).

[0081] In some example embodiments, the first dividing pattern 610 may extend in the second direction D2 on the CSP 200 on the first and second regions I and II of the substrate 100 and may divide the first gate electrodes 600 respectively included in adjacent ones of the gate electrode structures in the third direction D3.

[0082] In some example embodiments, the first dividing patterns 610 may extend through the third to sixth insulating interlayers 390, 470, 560, and 630, the etch stop layer 640, the first and second gate electrodes 600 and 650, the support layer 260, the support pattern 265, and the sacrificial layer structure 250. In some example embodiments, the first dividing patterns 610 may be spaced apart from each other by a constant distance in the third direction D3.

[0083] In some example embodiments, each gate electrode structure divided by the first dividing pattern 610 and the first and second memory channel structures 550 and 720 extending through each gate electrode structure may collectively form a memory block, and a plurality of memory blocks may be arranged in the third direction D3.

[0084] The second dividing pattern 615 may be disposed between adjacent first dividing patterns 610 in the third direction D3 among the first dividing patterns 610, and may extend through the third to sixth insulating interlayers 390, 470, 560, and 630, the etch stop layer 640, the first and second gate electrodes 600 and 650, the support layer 260, the support pattern 265, and the sacrificial layer structure 250. In some example embodiments, a plurality of second dividing patterns 615 may be spaced apart from each other in the second direction D2.

[0085] The third dividing pattern 660 may extend in the second direction D2 on portions of the first and second regions I and II of the substrate 100 adjacent to the first region I, and may extend through the second gate electrode 650 and the etch stop layer 640 to contact an upper surface of the sixth insulating interlayer 630. In some example embodiments, the third dividing pattern 660 may be disposed between adjacent ones of the first and second dividing patterns 610 and 615.

[0086] Each of the first to third dividing patterns 610 , 615 , and 660 may include oxide (eg, silicon oxide) or insulating nitride (eg, silicon nitride).

[0087] refer to Figures 9 to 12 as well as Fig.30The first memory channel structure 550 may be disposed on the first region I of the substrate 100 to contact the upper surface of the CSP 200, and may extend through the channel connection pattern 580, the support layer 260, the first gate electrode 600, the second insulating pattern 275, and the third and fourth insulating interlayers 390 and 470 in each memory block.

[0088] In some example embodiments, the first memory channel structure 550 may include: a first filling pattern 530, which may extend in the first direction D1 and have a columnar shape; a first channel 520, which may cover the sidewalls and lower surface of the first filling pattern 530 and have a cup shape; a first charge storage structure 510, which is on the outer sidewalls and lower surface of the first channel 520; and a first cover pattern 540, which contacts the upper surface of the first channel 520, the upper surface of the first filling pattern 530, and the upper surface of the first charge storage structure 510.

[0089] The first charge storing structure 510 may include a first tunnel insulating pattern 500 , a first charge storing pattern 490 , and a first blocking pattern 480 sequentially stacked in a horizontal direction from an outer sidewall of the first channel 520 .

[0090] In some example embodiments, a plurality of first memory channel structures 550 may be spaced apart from one another in the second direction D2 and the third direction D3 in each memory block on the first region I of the substrate 100 to form a first memory channel structure array, and the plurality of first memory channel structures 550 included in the first memory channel structure array may be connected to one another by a channel connection pattern 580. For example, the first charge storage structure 510 may not be formed on a portion of an outer wall of each first channel 520, and the channel connection pattern 580 may contact the outer sidewalls of the first channels 520 to electrically connect the first channels 520 to one another.

[0091] The first support structure 350 and the second support structure 430 may be stacked on the second region II of the substrate 100 in the first direction D1 and may contact the upper surface of the CSP 200. The first support structure 350 and the second support structure 430 may extend through the sacrificial layer structure 250, the first gate electrode 600, the second insulating pattern 275, and the third insulating interlayer 390 in the first direction D1. In some example embodiments, a plurality of first support structures 350 may be spaced apart from each other in the second direction D2 and the third direction D3 on the second region II of the substrate 100, and a plurality of second support structures 430 may be spaced apart from each other in the second direction D2 and the third direction D3 on the second region II of the substrate 100.

[0092] Each of the first support structure 350 and the second support structure 430 may include an oxide (eg, silicon oxide), and in some example embodiments, the first support structure 350 and the second support structure 430 may include substantially the same material to be merged with each other (eg, to form an integral structure).

[0093] The second memory channel structure 720 may include a second filling pattern 700, a second channel 690, a second charge storage structure 680, and a second capping pattern 710, which may correspond to the first memory channel structure 550. In some example embodiments, the second memory channel structure 720 may extend through the sixth insulating interlayer 630, the etch stop layer 640, and the second gate electrode 650 to at least partially contact an upper surface of the first memory channel structure 550.

[0094] In some example embodiments, the second channel 690 may include a lower portion, a central portion, and an upper portion, the lower portion extending through the sixth insulating interlayer 630 and having a first width, the central portion extending through the etch stop layer 640 and having a second width, and the upper portion extending through a portion of the second gate electrode 650 and having a third width. Each of the first width and the third width may be greater than the second width. The upper portion of the second channel 690 may have a cup shape, and the second filling pattern 700 may fill a space formed by the upper portion of the second channel 690.

[0095] The second charge storage structure 680 may extend through the second gate electrode 650 to cover the sidewalls of the upper portion and the lower surface of the edge portion of the second channel 690 and the sidewalls of the second capping pattern 710. The second charge storage structure 680 may include a second tunnel insulating pattern, a second charge storage pattern, and a third blocking pattern sequentially stacked in a horizontal direction from the outer sidewall of the second channel 690, which may correspond to the first charge storage structure 510.

[0096] The second capping pattern 710 may contact upper surfaces of upper portions of the second channels 690 and upper surfaces of the second filling patterns 700 , and may also contact inner sidewalls of the second charge storing structures 680 .

[0097] In some example embodiments, the second memory channel structure 720 may contact a corresponding first memory channel structure 550 in the first memory channel structures 550, so that a plurality of second memory channel structures 720 may be spaced apart from each other in the second direction D2 and the third direction D3 in each memory block on the first region I of the substrate 100 to form a second memory channel structure array.

[0098] The first and second channels 520 and 690 may include, for example, undoped polysilicon, the first and second filling patterns 530 and 700 may include oxide (eg, silicon oxide), and the first and second capping patterns 540 and 710 may include, for example, polysilicon doped with impurities.

[0099] The first tunnel insulation pattern 500 and the second tunnel insulation pattern may include oxide (e.g., silicon oxide), the first charge storage pattern 490 and the second charge storage pattern may include nitride (e.g., silicon nitride), and the first barrier pattern 480 and the third barrier pattern may include oxide (e.g., silicon oxide).

[0100] The second barrier pattern 590 may cover upper and lower surfaces of each first gate electrode 600 and sidewalls of each first gate electrode 600 that may face the first memory channel structure 550, the first and second support structures 350 and 430, and the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767, and 768. The second barrier pattern 590 may include a metal oxide (e.g., aluminum oxide or hafnium oxide).

[0101] The third insulating interlayer 390 may be disposed between the lower first gate electrode 600 in the first gate electrode 600 in the gate electrode structure and the upper first gate electrode 600 in the first gate electrode 600 , and the fourth insulating interlayer 470 may be disposed between the topmost first gate electrode 600 and the second gate electrode 650 in the first gate electrode 600 in the gate electrode structure.

[0102] The fifth insulating interlayer 560 and the sixth insulating interlayer 630 may be disposed on the fourth insulating interlayer 470. The fifth insulating interlayer 560 may be disposed on the fourth insulating interlayer 470. The fifth insulating interlayer 560 may be disposed on the second region II of the substrate 100, and the sixth insulating interlayer 630 may be disposed on the first region I of the substrate 100.

[0103] An etch stop layer 640 and a second gate electrode 650 may be sequentially stacked on the sixth insulating interlayer 630 .

[0104] The seventh insulating interlayer 730 may be disposed on the fifth insulating interlayer 560 and the second gate electrode 650 , and the eighth to tenth insulating interlayers 770 , 800 , and 840 may be sequentially stacked on the seventh insulating interlayer 730 .

[0105] Each of the first to fifth insulating interlayers 140, 190, 390, 470, and 560, each of the seventh to tenth insulating interlayers 730, 770, 800, and 840, and the etch stop layer 640 may include an oxide (e.g., silicon oxide), some of which may be merged with each other. The sixth insulating interlayer 630 may include an insulating nitride (e.g., silicon nitride).

[0106] Each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 can extend through the fourth insulating interlayer 470, the fifth insulating interlayer 560 and the seventh insulating interlayer 730, the second barrier pattern 590 and a portion of the gate electrode structure on the second region II of the substrate 100, and can contact the upper surface of the corresponding first gate electrode 600 in the first gate electrode structure to be electrically connected thereto.

[0107] That is, each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767, and 768 may contact an upper surface of a corresponding one of the first gate electrodes 600 in the gate electrode structure, and may extend through some of the first gate electrodes 600 over the corresponding one of the first gate electrodes 600. However, each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767, and 768 may be electrically insulated from the first gate electrode 600 disposed over the corresponding one of the first gate electrodes 600 by the first to third spacers 305, 375, and 455.

[0108] In some example embodiments, the second support structure 430 may be disposed at corresponding vertices of a rectangle in a plan view. In some example embodiments, the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767, and 768 may be spaced apart from each other in the second direction D2 on the second region II of the substrate 100.

[0109] The first gate electrode 600 included in the gate electrode structure can have substantially the same length in the second direction D2, so that each upper contact plug (that is, each of the second to eighth upper contact plugs 762, 763, 764, 765, 766, 767 and 768) except the first upper contact plug 761 of the third region III closest to the substrate 100 can contact the upper surface of the corresponding first gate electrode 600 of the first gate electrode 600 that is not its end portion.

[0110] In some example embodiments, each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 may include an upper portion extending through the fourth insulating interlayer 470, the fifth insulating interlayer 560 and the seventh insulating interlayer 730 and a lower portion of the gate electrode structure partially extending through the upper portion, and a lower surface of the upper portion may have a width smaller than a width of an upper surface of the lower portion.

[0111] The lower portion of each of the first to sixth upper contact plugs 761, 762, 763, 764, 765 and 766 may include a first lower portion lower than the lower surface of the third insulating interlayer 390 and a second lower portion substantially coplanar with or higher than the lower surface of the third insulating interlayer 390.

[0112] In some example embodiments, each of the first to sixth upper contact plugs 761, 762, 763, 764, 765, and 766 may include a portion in which a width decreases in a stepwise manner from a top toward a bottom thereof in the first direction D1. In some example embodiments, a width of an upper surface of a first lower portion of each of the first to sixth upper contact plugs 761, 762, 763, 764, 765, and 766 may be greater than a width of a lower surface of a second lower portion.

[0113] In some example embodiments, the first to third spacers 305 , 375 , and 455 may be disposed on a sidewall of a lower portion of each of the first to eighth upper contact plugs 761 , 762 , 763 , 764 , 765 , 766 , 767 , and 768 , and may contact a sidewall of the second barrier pattern 590 and a sidewall of the second insulating pattern 275 .

[0114] For example, the third spacer 455 may be disposed on a sidewall of a lower portion of each of the seventh upper contact plug 767 and the eighth upper contact plug 768. In addition, the third spacer 455 may be disposed on a sidewall of a second lower portion of each of the first to sixth upper contact plugs 761, 762, 763, 764, 765, and 766, and the second spacer 375 may be disposed on a sidewall of a first lower portion of each of the first to sixth upper contact plugs 761, 762, 763, 764, 765, and 766. In some example embodiments, the second spacer 375 and the third spacer 455 may not contact each other.

[0115] The first spacer 305 may be disposed under a portion of the second lower portion of each of the first upper contact plug 761 and the second upper contact plug 762. The first spacer 305 may be disposed under the second spacer 375 and may not contact the second spacer 375.

[0116] The first spacer 305 may also be disposed on the upper surface of the topmost fourth sacrificial layer 280 among the fourth sacrificial layers 280 included in the first mold layer and on the upper surface of the second barrier pattern 590 in contact with the topmost fourth sacrificial layer 280 among the fourth sacrificial layers 280 in the first mold layer, the second spacer 375 may also be disposed on the upper surface of the topmost fourth sacrificial layer 280 among the fourth sacrificial layers 280 included in the second mold layer and on the upper surface of the second barrier pattern 590 in contact with the topmost fourth sacrificial layer 280 among the fourth sacrificial layers 280 in the second mold layer, and the third spacer 455 may also be disposed on the upper surface of the topmost fourth sacrificial layer 280 among the fourth sacrificial layers 280 included in the third mold layer and on the upper surface of the second barrier pattern 590 in contact with the topmost fourth sacrificial layer 280 among the fourth sacrificial layers 280 in the third mold layer.

[0117] Each of the first to third spacers 305, 375, and 455 may include oxide (eg, silicon oxide), and thus, in some example embodiments, may be merged with (eg, may form a whole with) the second insulating pattern 275 or the third and fourth insulating interlayers 390 and 470.

[0118] Figures 10 to 12 The first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 are illustrated as upper contact plugs that may partially extend through the gate electrode structure to contact a single first gate electrode 600 in the gate electrode structure, however, the present inventive concept may not be limited thereto and the semiconductor device may include more than the eighth upper contact plug.

[0119] The ninth upper contact plug 769 may extend through the seventh insulating interlayer 730 to contact the upper surface of the second gate electrode 650. In some example embodiments, the ninth upper contact plug 769 may be disposed on a portion of the second region II of the substrate 100 adjacent to the first region I. In some example embodiments, the ninth upper contact plug 769 may be disposed between adjacent ones of the first and third dividing patterns 610 and 660 in the third direction D3, and between adjacent ones of the second and third dividing patterns 615 and 660 in the third direction D3.

[0120] The through via 790 can extend in the first direction D1 on the third region III of the substrate 100, and can extend through the upper portion of the second insulating interlayer 190, the first insulating pattern 264, the first to third mold layers, and the third insulating interlayer 390, the fourth insulating interlayer 470, the fifth insulating interlayer 560, the seventh insulating interlayer 730 and the eighth insulating interlayer 770 to contact the upper surface of the third lower wiring 184.

[0121] The first upper via 810 may extend through the seventh to ninth insulating interlayers 730, 770 and 800 to contact an upper surface of the second memory channel structure 720, each second upper via 820 may extend through the eighth insulating interlayer 770 and the ninth insulating interlayer 800 to contact an upper surface of a corresponding one of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768, the third upper via 825 may extend through the eighth insulating interlayer 770 and the ninth insulating interlayer 800 to contact an upper surface of the ninth upper contact plug 769, and the fourth upper via 830 may extend through the ninth insulating interlayer 800 to contact an upper surface of the through via 790.

[0122] The first to fourth upper wirings 850 , 860 , 865 , and 870 may extend through the tenth insulating interlayer 840 to contact upper surfaces of the first to fourth upper vias 810 , 820 , 825 , and 830 , respectively.

[0123] In some example embodiments, the first upper wiring 850 may extend in the third direction D3, and a plurality of first upper wirings 850 may be spaced apart from each other in the second direction D2. The first wiring 850 may function as a bit line.

[0124] Figures 10 to 12 The first to fourth upper wirings 850, 860, 865, and 870 and the first to fourth vias 810, 820, 825, and 830 are respectively shown as upper wirings and upper vias, however, the inventive concept may not be limited thereto. Therefore, the upper wirings and upper vias may have various layouts, and the semiconductor device may further include upper wirings and / or upper vias at an upper level.

[0125] Each of the first to ninth upper contact plugs 761, 762, 763, 764, 765, 766, 767, 768 and 769, the through via 790, the first to fourth upper vias 810, 820, 825 and 830, and the first to fourth upper wirings 850, 860, 865 and 870 may include a conductive material, such as metal, metal nitride, metal silicide, etc.

[0126] The semiconductor device may include a gate electrode structure (which has a first gate electrode 600 stacked in a first direction D1 and a second gate electrode 650 above the topmost first gate electrode 600 among the first gate electrodes 600), first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 respectively contacting the upper surface of the first gate electrode 600, and a ninth upper contact plug contacting the upper surface of the second gate electrode 650.

[0127] Each first gate electrode 600 may extend in the second direction D2 and may have a constant thickness. The first gate electrodes 600 may have substantially the same length in the second direction D2. Therefore, the gate electrode structure may not have a stepped shape, and thus the formation of the gate electrode structure may be simplified.

[0128] Each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 for transmitting an electrical signal to the first gate electrode 600 included in the gate electrode structure not having a step shape can contact the upper surface of the corresponding first gate electrode 600 in the first gate electrode 600 and can extend through the first gate electrode 600 in the first gate electrode 600 above the corresponding first gate electrode 600 in the first gate electrode 600. The first to third spacers 305, 375 and 455 can be arranged between each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 and the first gate electrode 600 in the first gate electrode 600 above the corresponding first gate electrode 600 in the first gate electrode 600, so that each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 can be electrically insulated from the first gate electrode 600 in the first gate electrode 600 above the corresponding first gate electrode 600 in the first gate electrode 600.

[0129] Figures 13 to 46 1 is a top view and a cross-sectional view showing a method of manufacturing a semiconductor device. In particular, Fig.13 , Fig.15 , Fig.19 , Fig. 22 , Fig. 27 , Fig.32 , Fig.35 and Fig.38 It is a top view. Fig.14 , Figures 16 to 18 , Figure 20 to Figure 21 , Figure 23 to Figure 26 , Figure 28 to Figure 31 , Figure 33 to Figure 34 , Figure 36 to Figure 37 and Figures 39 to 46 It is a cross-sectional view.

[0130] Fig.14 , Figures 16 to 18 , Figure 20 to Figure 21 , Figure 23 to Figure 26 , Figure 28 to Figure 31 , Fig.36 , Fig.39 and Figure 41 to Figure 46 are sectional views taken along the line AA' of the corresponding top view, Figure 33 to Figure 34 , Fig.37 and Fig.40It is a cross-sectional view taken along the line BB' of the corresponding top view.

[0131] Figures 13 to 46 yes Fig. 9 of the region X, and Fig.31 yes Fig.30 An enlarged cross-sectional view of region Y.

[0132] refer to Fig.13 and Fig.14 , a lower circuit pattern may be formed on the substrate 100 , and a first insulating interlayer 140 and a second insulating interlayer 190 may be sequentially stacked on the substrate 100 to cover the lower circuit pattern.

[0133] Each element of the lower circuit pattern may be formed through a patterning process or a damascene process.

[0134] CSP 200 and sacrificial layer structure 250 may be sequentially formed on second insulating interlayer 190 , sacrificial layer structure 250 may be partially removed to form first opening 261 exposing an upper surface of CSP 200 , and support layer 260 may be formed on an upper surface of sacrificial layer structure 250 and the exposed upper surface of CSP 200 .

[0135] The sacrificial layer structure 250 may include sequentially stacked first, second, and third sacrificial layers 220, 230, and 240. Each of the first and third sacrificial layers 220 and 240 may include oxide (eg, silicon oxide), and the second sacrificial layer 230 may include nitride (eg, silicon nitride).

[0136] The support layer 260 may include a material having an etching selectivity with respect to the first to third sacrificial layers 220, 230, and 240, such as polysilicon doped with n-type impurities. The support layer 260 may be conformally formed, and thus a first recess may be formed on a portion of the support layer 260 located in the first opening 261. Hereinafter, the portion of the support layer 260 located in the first opening 261 may contact the upper surface of the CSP 200 and may be referred to as a support pattern 265.

[0137] The support pattern 265 may have various layouts in a top view. For example, a plurality of support patterns 265 may be spaced apart from each other in the second direction D2 and the third direction D3 on the first region I of the substrate 100. In addition, the support pattern 265 may extend in the third direction D3 on a portion of the second region II of the substrate 100 adjacent to the first region I. In addition, a plurality of support patterns 265 (each of which may extend in the second direction D2) may be spaced apart from each other in the third direction D3 on the second region II of the substrate 100. Fig.14A support pattern 265 extending in the third direction D3 on a portion of the second region II of the substrate 100 adjacent to the first region I is shown.

[0138] The first insulating pattern 264 may be formed on the third region III of the substrate 100 to partially pass through the CSP 200, the sacrificial layer structure 250, and the support layer 260. In some example embodiments, the first insulating pattern 264 may overlap the third lower wiring 184 in the first direction D1.

[0139] The second insulating layer 270 and the fourth sacrificial layer 280 may be alternately and repeatedly stacked on the support layer 260, the support pattern 265, and the first insulating pattern 264 in the first direction D1, and thus a first mold layer including the second insulating layer 270 and the fourth sacrificial layer 280 may be formed. In example embodiments, the first mold layer may include three second insulating layers 270 and three fourth sacrificial layers 280 stacked in the first direction D1, however, the present inventive concept may not be limited thereto.

[0140] The second insulating layer 270 may include an oxide (eg, silicon oxide), and the fourth sacrificial layer 280 may include a material having an etching selectivity with respect to the second insulating layer 270 , for example, a nitride (such as silicon nitride).

[0141] refer to Fig.15 and Fig.16 , the first mold layer on the second area II of the substrate 100 can be partially removed to form a twenty-first hole 291 and a twenty-second hole 292, which respectively expose the upper surface of the fourth sacrificial layer 280 at the third level from the top among the fourth sacrificial layer 280 and the upper surface of the fourth sacrificial layer 280 at the second level from the top among the fourth sacrificial layer 280.

[0142] In some example embodiments, the twenty-second hole 292 may be formed by partially removing the uppermost fourth sacrificial layer 280 of the fourth sacrificial layers 280 and the uppermost second insulating layer 270 of the second insulating layers 270, and the twenty-second hole 292 may be formed by partially removing the uppermost fourth sacrificial layer 280 of the fourth sacrificial layers 280, the fourth sacrificial layers 280 at the second level from above of the fourth sacrificial layers 280, the uppermost second insulating layer 270 of the second insulating layers 270, and the second insulating layer 270 at the second level from above of the second insulating layers 270. The twenty-first hole 291 may include a lower portion having a relatively small width and an upper portion having a relatively large width.

[0143] In some example embodiments, the plurality of twenty-first holes 291 may be spaced apart from one another in the third direction D3 , and the plurality of twenty-second holes 292 may be spaced apart from one another in the third direction D3 .

[0144] refer to Fig.17 A first spacer layer 300 may be formed on the inner walls of the twenty-first hole 291 and the twenty-second hole 292 and on the upper surface of the topmost fourth sacrificial layer 280 in the fourth sacrificial layer 280, a fifth sacrificial layer may be formed on the first spacer layer 300 to fill the twenty-first hole 291 and the second second hole 292, and a planarization process may be performed on the fifth sacrificial layer until the upper surface of a portion of the first spacer layer 300 on the topmost fourth sacrificial layer 280 in the fourth sacrificial layer 280 is exposed to form a fifth sacrificial pattern 311 and a sixth sacrificial pattern 312 in the twenty-first hole 291 and the second second hole 292, respectively.

[0145] The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0146] The first spacer layer 300 may include oxide (eg, silicon oxide), and the fifth sacrificial layer may include, for example, polysilicon.

[0147] refer to Fig.18 , the second insulating layer 270 and the fourth sacrificial layer 280 may be alternately and repeatedly stacked on the first spacer layer 300 and the fifth and sixth sacrificial patterns 311 and 312 in the first direction D1, and thus a second mold layer including the second insulating layer 270 and the fourth sacrificial layer 280 may be formed.

[0148] refer to Fig.19 and Fig. 20 A twenty-third hole and a twenty-fourth hole may be formed through the first and second mold layers, the support layer 260, and the sacrificial layer structure 250 to expose the upper surface of the CSP 200 on the first region I and the second region II, respectively, and a twenty-fifth hole may be formed through the first and second mold layers, the first insulating pattern 264, and the upper portion of the second insulating interlayer 190 to expose the upper surface of the third lower wiring 184 on the third region III.

[0149] In some example embodiments, a plurality of twenty-third holes may be spaced apart from each other in the second direction D2 and the third direction D3 on the first region I of the substrate 100, and a plurality of twenty-fourth holes may be spaced apart from each other in the second direction D2 and the third direction D3 on the second region II of the substrate 100.

[0150] A seventh sacrificial layer may be formed on the CSP 200, the third lower wiring 184, and the uppermost fourth sacrificial layer 280 of the fourth sacrificial layer 280 of the second mold layer, and, for example, a CMP process may be performed on the seventh sacrificial layer to form first to third sacrificial pillars 322, 324, and 326 in the twenty-third to twenty-fifth holes, respectively. The seventh sacrificial layer may include a metal such as tungsten or polysilicon.

[0151] The upper portions of the first to third sacrificial pillars 322, 324, and 326 may be removed by, for example, an etch-back process to form second to fourth recesses, respectively, and first to third sacrificial capping patterns 332, 334, and 336 may be formed in the second to fourth recesses, respectively. Each of the first to third sacrificial capping patterns 332, 334, and 336 may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0152] refer to Fig.21 , a first sacrificial insulating interlayer 340 can be formed on the topmost fourth sacrificial layer 280 in the fourth sacrificial layer 280 of the second mold layer and the first to third sacrificial cover patterns 332, 334 and 336, a twenty-sixth hole can be formed to pass through the first sacrificial insulating interlayer 340 to expose the upper surface of the second sacrificial cover pattern 334, the second sacrificial cover pattern 334 and the second sacrificial pillar 324 can be removed to form a twenty-fourth hole again, and a first supporting structure 350 can be formed in the twenty-fourth hole and the twenty-sixth hole, respectively.

[0153] Each of the first sacrificial insulating interlayer 340 and the first supporting structure 350 may include an oxide (eg, silicon oxide).

[0154] refer to Fig. 22 and Fig.23 , you can execute Figures 1 to 8 The illustrated process is substantially the same or similar process to form twenty-seventh to thirty-second holes 361 , 362 , 363 , 364 , 365 , and 366 passing through the first sacrificial insulating interlayer 340 and a portion of the second mold layer on the second region II of the substrate 100 .

[0155] In some example embodiments, the twenty-seventh to thirty-second holes 361, 362, 363, 364, 365, and 366 may be formed to be spaced apart from each other in the second direction D2 on the second region II of the substrate 100. The twenty-seventh hole 361 and the twenty-eighth hole 362 may expose the upper surface of the lowermost second insulating layer 270 of the second mold layer and may overlap the fifth and sixth sacrificial patterns 311 and 312, respectively, in the first direction D1.

[0156] The twenty-ninth to thirty-second holes 363, 364, 365, and 366 may respectively expose upper surfaces of corresponding ones of the fourth sacrificial layers 280. For example, the twenty-ninth hole 363 may expose an upper surface of the lowermost one of the fourth sacrificial layers 280 of the second mold layer, and the thirty-second hole 366 may expose an upper surface of the fourth sacrificial layer 280 of the fourth sacrificial layers 280 at the second level from above in the second mold layer.

[0157] Fig. 22 and Fig.23 Six holes (eg, twenty-seventh to thirty-second holes 361, 362, 363, 364, 365, and 366) are shown that respectively expose the upper surface of the fourth sacrificial layer 280 included in the second mold layer. However, the inventive concept may not be limited thereto, and in some example embodiments, more than six holes may be formed.

[0158] In some example embodiments, in a plan view, each of the twenty-seventh to thirty-second holes 361, 362, 363, 364, 365, and 366 may be formed between the first support structures 350. For example, the first support structures 350 may be respectively formed at vertices of a rectangle in a plan view, and each of the twenty-seventh to thirty-second holes 361, 362, 363, 364, 365, and 366 may be formed inside the rectangle in a plan view.

[0159] Through the etching process, the first sacrificial insulating interlayer 340 may be removed.

[0160] refer to Fig.24 A second spacer layer 370 may be formed on inner walls of the twenty-seventh to thirty-second holes 361, 362, 363, 364, 365 and 366, an upper surface of the topmost fourth sacrificial layer 280 in the fourth sacrificial layer 280 of the second mold layer, upper surfaces of the first sacrificial cover pattern 332 and the third sacrificial cover pattern 336, and an upper surface of the first supporting structure 350, an eighth sacrificial layer may be formed on the second spacer layer 370 to fill the twenty-seventh to thirty-second holes 361, 362, 363, 364, 365 and 366, and a planarization process may be performed on the eighth sacrificial layer until a portion of the second spacer layer 370 on the topmost fourth sacrificial layer 280 in the fourth sacrificial layer 280 of the second mold layer is exposed to form seventh to twelfth sacrificial patterns 381, 382, ​​383, 384, 385 and 386 in the twenty-seventh to thirty-second holes 361, 362, 363, 364, 365 and 366, respectively.

[0161] The second spacer layer 370 may include oxide (eg, silicon oxide), and the eighth sacrificial layer may include, for example, polysilicon.

[0162] refer to Fig.25 and Fig.26 A third insulating interlayer 390 may be formed on the second spacer layer 370 and the seventh to twelfth sacrificial patterns 381 , 382 , 383 , 384 , 385 , and 386 , and fourth sacrificial layers 280 and second insulating layers 270 may be alternately and repeatedly stacked on the third insulating interlayer 390 to form a third mold layer including the fourth sacrificial layers 280 and the second insulating layers 270 .

[0163] The third insulating interlayer 390 may include oxide (eg, silicon oxide).

[0164] The first sacrificial cover pattern 332 and the third sacrificial cover pattern 336 exposed by the thirty-third hole 402 and the thirty-fifth hole 406, respectively, and the first sacrificial pillar 322 and the third sacrificial pillar 326 thereunder can be removed to form the twenty-third hole and the twenty-fifth hole again, respectively, and the fourth to sixth sacrificial pillars 412, 414 and 416 can be formed in the twenty-third hole and the twenty-fifth hole and the thirty-third to thirty-fifth holes 402, 404 and 406.

[0165] For example, the fourth sacrificial pillar 412 may be formed in the twenty-third and thirty-third holes 402, the fifth sacrificial pillar 414 may be formed in the thirty-fourth hole 404, and the sixth sacrificial pillar 416 may be formed in the twenty-fifth and thirty-fifth holes 406. In example embodiments, each of the fourth to sixth sacrificial pillars 412, 414, and 416 may include an insulating material containing carbon, such as silicon carbon nitride (SiCN).

[0166] refer to Fig. 27 and Fig.28 A second sacrificial insulating interlayer can be formed on the topmost fourth sacrificial layer 280 in the fourth sacrificial layer 280 of the third mold layer and the fourth to sixth sacrificial pillars 412, 414 and 416, a thirty-sixth hole can be formed through the second sacrificial insulating interlayer to expose the upper surface of the fifth sacrificial pillar 414, and the fifth sacrificial pillar 414 can be removed to form a thirty-fourth hole 404 again.

[0167] The second support structure 430 may be formed in the thirty-fourth hole 404 and the thirty-sixth hole, and a planarization process may be performed until an upper surface of an uppermost fourth sacrificial layer 280 among the fourth sacrificial layers 280 of the third mold layer is exposed.

[0168] Thus, the second sacrificial insulating interlayer may be removed, and the second support structure 430 may remain in the thirty-fourth hole 404. The second support structure 430 may include an oxide (e.g., silicon oxide), and in some example embodiments, the second support structure 430 may include substantially the same material as the first support structure 350 to be merged thereto.

[0169] Can be executed with regard to Figures 1 to 8 The illustrated processes are substantially the same or similar processes to form thirty-seventh to forty-fourth holes 441 , 442 , 443 , 444 , 445 , 446 , 447 , and 448 partially passing through the third mold layer on the second region II of the substrate 100 .

[0170] In some example embodiments, the thirty-seventh to forty-fourth holes 441, 442, 443, 444, 445, 446, 447, and 448 may be formed to be spaced apart from each other in the second direction D2 on the second region II of the substrate 100. The thirty-seventh to forty-second holes 441, 442, 443, 444, 445, and 446 may expose an upper surface of the third insulating interlayer 390 and may overlap the seventh to twelfth sacrificial patterns 381, 382, ​​383, 384, 385, and 386, respectively, in the first direction D1.

[0171] The forty-third hole 447 and the forty-fourth hole 448 may respectively expose the upper surface of the corresponding fourth sacrificial layer 280 in the fourth sacrificial layers 280 of the third mold layer. For example, the forty-third hole 447 may expose the upper surface of the lowermost fourth sacrificial layer 280 in the fourth sacrificial layers 280 in the third mold layer, and the forty-fourth hole 448 may expose the upper surface of the fourth sacrificial layer 280 in the third mold layer at the second level from above.

[0172] Fig. 27 and Fig.28 Eight holes (e.g., thirty-seventh to forty-fourth holes 441, 442, 443, 444, 445, 446, 447, and 448) are shown, which expose the upper surfaces of the corresponding fourth sacrificial layers 280 included in the third mold layer. However, the inventive concept may not be limited thereto, and in some example embodiments, more than eight holes may be formed.

[0173] In some example embodiments, in a plan view, each of the thirty-seventh to forty-fourth holes 441, 442, 443, 444, 445, 446, 447, and 448 may be formed between the second support structures 430. For example, the second support structures 430 may be respectively formed at vertices of a rectangle in a plan view, and each of the thirty-seventh to forty-fourth holes 441, 442, 443, 444, 445, 446, 447, and 448 may be formed inside the rectangle in a plan view.

[0174] refer to Fig.29 A third spacer layer 450 may be formed on inner walls of the thirty-seventh to forty-fourth holes 441, 442, 443, 444, 445, 446, 447, and 448, an upper surface of the uppermost fourth sacrificial layer 280 of the fourth sacrificial layer 280 of the third mold layer, upper surfaces of the fourth sacrificial pillars 412 and the sixth sacrificial pillars 416, and an upper surface of the second supporting structure 430, and a ninth sacrificial layer may be formed on the third spacer layer 450 to fill the thirty-seventh to forty-fourth holes 441, 442, 443, 444, 445, 446, 447, and 448. 442, 443, 444, 445, and a planarization process may be performed on the ninth sacrificial layer until a portion of the third spacer layer 450 on the uppermost fourth sacrificial layer 280 in the fourth sacrificial layer 280 is exposed to form thirteenth to twentieth sacrificial patterns 461, 462, 463, 464, 465, 466, 467 and 468 in the thirty-seventh to forty-fourth holes 441, 442, 443, 444, 445, 446, 447 and 448, respectively.

[0175] The third spacer layer 450 may include oxide (eg, silicon oxide), and the ninth sacrificial layer may include, for example, polysilicon.

[0176] A fourth insulating interlayer 470 may be formed on the third spacer layer 450 and the thirteenth to twentieth sacrificial patterns 461, 462, 463, 464, 465, 466, 467, and 468. The fourth insulating interlayer 470 may include oxide (eg, silicon oxide).

[0177] refer to Fig.30 and Fig.31 , a forty-fifth hole can be formed through the fourth insulating interlayer 470 and the third spacer layer 450 to expose the fourth sacrificial column 412, the fourth sacrificial column 412 can be removed to form the thirty-third hole 402 and the twenty-third hole again, and the first memory channel structure 550 can be formed therein.

[0178] In some example embodiments, the first memory channel structure 550 may include a first filling pattern 530 extending in the first direction D1, a first channel 520 covering a sidewall and a lower surface of the first filling pattern 530, a first charge storage structure 510 covering a sidewall and a lower surface of the first channel 520, and a first capping pattern 540 on the first filling pattern 530, the first channel 520, and the first charge storage structure 510. The first charge storage structure 510 may include a first tunnel insulating pattern 500, a first charge storage pattern 490, and a first blocking pattern 480 sequentially stacked on a sidewall and a lower surface of the first channel 520.

[0179] refer to Fig.32 and Fig.33 , a fifth insulating interlayer 560 can be formed on the fourth insulating interlayer 470 and the first memory channel structure 550, and a second opening 570 can be formed by an etching process to extend in the second direction D2 through the third to fifth insulating interlayers 390, 470 and 560, the first to third mold layers, the support layer 260, the support pattern 265 and the sacrificial layer structure 250 on the first region I and the second region II of the substrate 100.

[0180] In some example embodiments, the second opening 570 may extend through the support pattern 265 to expose the upper surface of the CSP 200 on the second region II of the substrate 100 , and may extend through the support layer 260 and the sacrificial layer structure 250 to expose the upper surface of the CSP 200 on the first region I of the substrate 100 .

[0181] In some example embodiments, the second openings 570 may extend in the second direction D2 to opposite ends of the first to third mold layers in the second direction on the first region I and the second region II of the substrate 100, and a plurality of the second openings 570 may be spaced apart from each other in the third direction D3. Thus, the first to third mold layers may be respectively divided into the first to third molds by the second openings 570 on the first region I and the second region II of the substrate 100, and the second insulating layer 270 and the fourth sacrificial layer 280 in each of the first to third mold layers may be respectively divided into the second insulating pattern 275 and the fourth sacrificial pattern 285, each of which may extend in the second direction D2.

[0182] However, the second opening 570 may not extend on the third region III of the substrate 100, and thus the first to third mold layers may not be respectively divided into the first to third molds on the third region III of the substrate 100. Therefore, the first to third mold layers including the second insulating layers 270 and the fourth sacrificial layers 280 stacked alternately and repeatedly may remain on the third region III of the substrate 100.

[0183] In the etching process, third openings 575 may also be formed to pass through the first to third insulating interlayers 390, 470, and 560, the first to third mold layers, the support layer 260, the support pattern 265, and the sacrificial layer structure to expose the upper surface of the CSP 200 on the first region I and the second region II of the substrate 100. In some example embodiments, the third openings 575 may be formed between the second openings 570 adjacent in the third direction D3 among the second openings 570 on the first region I and the second region II of the substrate 100, and the plurality of third openings 575 may be spaced apart from each other in the second direction D2.

[0184] When the first to third mold layers are separated into first to third molds extending in the second direction D2 through the etching process, the first to third molds may not fall due to the first and second support structures 350 and 430 and the first memory channel structure 550 .

[0185] refer to Fig.34 , a wet etching process may be performed through the second opening 570 and the third opening 575 , and thus the sacrificial layer structure may be removed to form a first gap between the support layer 260 and the CSP 200 on the first region I of the substrate 100 .

[0186] The wet etching process may use an etching solution (e.g., HF and / or H 3 PO 4 ). In some example embodiments, the second opening 570 and the third opening 575 may extend through the support pattern 265 to expose the upper surface of the CSP 200 on the second region II of the substrate 100, rather than extending through the support layer 260 to expose the upper surface of the CSP 200, and thus, when the wet etching process is performed, the sacrificial layer structure 250 may not be removed due to the support pattern 265. In addition, the second opening 570 and the third opening 575 may not be formed on the third region III of the substrate 100, and thus, the sacrificial layer structure on the third region III of the substrate 100 may not be removed.

[0187] When the first gap is formed, a portion of the sidewall of the first charge storage structure 510 may be exposed, and the portion of the sidewall of the first charge storage structure 510 may also be removed by a wet etching process to expose a portion of the outer sidewall of the first channel 520. Therefore, the first charge storage structure 510 may be divided into an upper portion extending through the first to third mold layers to cover most of the outer sidewall of the first channel 520 and a lower portion covering the lower surface of the first channel 520 on the CSP 200.

[0188] A channel connection layer may be formed on sidewalls of the second and third openings 570 and 575 and in the first gap, and, for example, an etch-back process may be performed to remove portions of the channel connection layer in the second and third openings 570 and 575 to form a channel connection pattern 580 in the first gap.

[0189] When the channel connection pattern 580 is formed, the first channels 520 between the second openings 570 adjacent in the third direction D3 of the second openings 570 on the first region I of the substrate 100 may be electrically connected to each other.

[0190] An air gap may be formed in the channel connection pattern 580 .

[0191] refer to Figure 35 to Figure 37 , the fourth sacrificial pattern 285 exposed by the second opening 570 and the third opening 575 can be removed to form a second gap between adjacent second insulating patterns 275 in the first direction D1 in the second insulating patterns 275, and a portion of the outer sidewall of the first charge storage structure 510 included in the first memory channel structure 550, a portion of the sidewall of each of the first support structure 350 and the second support structure 430, and a portion of the sidewall of each of the thirteenth to twentieth sacrificial patterns 461, 462, 463, 464, 465, 466, 467 and 468 can be exposed through the second gap.

[0192] In some example embodiments, the invention can be realized by using a method including, for example, H 3 PO 4 or H 2 SO 4 The fourth sacrificial pattern 285 is removed by a wet etching process using an etching solution of .

[0193] The wet etching process can be performed through the second opening 570 and the third opening 575, and the portion of the fourth sacrificial pattern 285 between adjacent openings in the second opening 570 and the third opening 575 can be completely removed by the etching solution, which can flow from the second opening 570 and the third opening 575 in two opposite directions on the first area I and the second area II of the substrate 100.

[0194] A second blocking layer may be formed on a portion of the outer sidewall of the first charge storage structure 510, a portion of the sidewall of each of the first support structure 350 and the second support structure 430, and a portion of the sidewall of each of the thirteenth to twentieth sacrificial patterns 461, 462, 463, 464, 465, 466, 467 and 468, an inner wall of each second gap, a surface of the second insulating pattern 275, sidewalls of the first to third spacer layers 300, 370 and 450, the third to fifth insulating interlayers 390, 470 and 560 and an upper surface of the fifth insulating interlayer 560, and a first gate electrode layer may be formed on the second blocking layer.

[0195] The first gate electrode layer may be partially removed to form the first gate electrode 600 in each second gap. In some example embodiments, the first gate electrode layer may be partially removed by a wet etching process.

[0196] In some example embodiments, the first gate electrode 600 may extend in the second direction D2, and a plurality of first gate electrodes 600 may be respectively stacked in a plurality of levels spaced apart from each other along the first direction D1 to form an initial gate electrode structure. In some example embodiments, the plurality of initial gate electrode structures may be spaced apart from each other in the third direction D3 through the second opening 570.

[0197] As described above, the plurality of third openings 575 may be spaced apart from each other in the second direction D2 on the first and second regions I and II of the substrate 100 , and thus the preliminary gate electrode structure may not be divided by the third openings 575 in the third direction D3 .

[0198] The second opening 570 and the third opening 575 may be formed only on the first region I and the second region II of the substrate 100 , and thus the fourth sacrificial layer 280 on the third region III of the substrate 100 may not be removed but remain.

[0199] A first dividing layer may be formed on the second barrier layer to fill the second opening 570 and the third opening 575 , and a planarization process may be performed on the first dividing layer and the second barrier layer until an upper surface of the fifth insulating interlayer 560 is exposed.

[0200] Thus, the second barrier layer may be transformed into the second barrier pattern 590 , and the first and second dividing patterns 610 and 615 may be formed in the second and third openings 570 and 575 , respectively.

[0201] refer to Figures 38 to 40, portions of the fifth insulating interlayer 560 on portions adjacent to the first region I on the first region I and the second region II of the substrate 100 can be removed to form a fourth opening exposing the upper surface of the fourth insulating interlayer 470, and a sixth insulating interlayer 630, an etching stop layer 640 and a second gate electrode layer can be sequentially stacked on the upper surface of the fourth insulating interlayer 470 to fill the fourth opening.

[0202] The sixth insulating interlayer 630 may include insulating nitride (eg, silicon nitride), the etch stop layer 640 may include oxide (eg, silicon oxide), and the second gate electrode layer may include, for example, doped polysilicon.

[0203] A fifth opening may be formed through the second gate electrode layer and the etch stop layer 640 to expose the upper surface of the sixth insulating interlayer 630, and a third dividing pattern 660 may be formed in the fifth opening. In some example embodiments, the third dividing pattern 660 may extend in the second direction D2 on portions of the first region I and the second region II of the substrate 100 adjacent to the first region I, and a plurality of third dividing patterns 660 may be spaced apart from each other in the third direction D3. Each third dividing pattern 660 may be formed between adjacent ones of the first dividing pattern 610 and the second dividing pattern 615.

[0204] When the third dividing pattern 660 is formed, the second gate electrode layer may be divided into second gate electrodes 650, each of which may extend in the second direction D2. The second gate electrodes 650 and the preliminary gate electrode structure including the first gate electrode 600 may collectively form a gate electrode structure.

[0205] A forty-sixth hole may be formed through the second gate electrode 650 to expose the upper surface of the etch stop layer 640. In some example embodiments, a plurality of forty-sixth holes may be spaced apart from each other in the second direction D2 and the third direction D3 to partially overlap the first memory channel structure 550 in the first direction D1.

[0206] A second charge storage structure layer may be formed on the sidewall and bottom of the forty-sixth hole, the first to third dividing patterns 610, 615, and 660, and the fifth insulating interlayer 560, and an etch-back process may be performed on the second charge storage structure layer to form a second charge storage structure 680 on edge portions of the sidewall and bottom of the forty-sixth hole. The second charge storage structure 680 may include a third blocking pattern, a second charge storage pattern, and a second tunnel insulating pattern sequentially stacked on the sidewall of the forty-sixth hole.

[0207] The portion of the etch stop layer 640 exposed by the forty-sixth hole and the portion of the sixth insulating interlayer 630 therebelow can be removed to expand the forty-sixth hole in the first direction D1, and the portion of the sixth insulating interlayer 630 adjacent to the expanded forty-sixth hole can be additionally removed to expand the forty-sixth hole in the horizontal direction, and thus, the forty-seventh hole can be formed to at least partially expose the upper surface of the first memory channel structure 550.

[0208] The forty-seventh hole may also expose an upper surface of a portion of the fourth insulating interlayer 470 adjacent to the first memory channel structure 550 .

[0209] A second channel 690 , a second filling pattern 700 , and a second capping pattern 710 may be formed in the forty-seventh hole.

[0210] In some example embodiments, the second trench 690 may include a lower portion surrounded by the sixth insulating interlayer 630, a central portion surrounded by the etch stop layer 640, and an upper portion surrounded by the second charge storage structure 680. A lower surface and sidewalls of the second filling pattern 700 may be covered by an upper portion of the second trench 690. A second capping pattern 710 may be formed on the second trench 690 and the second filling pattern 700, and may be surrounded by the second charge storage structure 680.

[0211] The second charge storing structure 680 , the second channel 690 , the second filling pattern 700 , and the second capping pattern 710 may collectively form a second memory channel structure 720 , and the second memory channel structure 720 may contact an upper surface of the first memory channel structure 550 to be connected to the first memory channel structure 550 .

[0212] refer to Fig.41 , a seventh insulating interlayer 730 may be formed on the second gate electrode 650, the second memory channel structure 720, the first to third dividing patterns 610, 615 and 660, and the fifth insulating interlayer 560. Forty-eighth to fifty-fifth holes 741, 742, 743, 744, 745, 746, 747 and 748 may be formed through the fourth insulating interlayer 470, the fifth insulating interlayer 560 and the seventh insulating interlayer 730 to expose upper surfaces of the thirteenth to twentieth sacrificial patterns 461, 462, 463, 464, 465, 466, 467 and 468, respectively. The thirteenth to twentieth sacrificial patterns 461 , 462 , 463 , 464 , 465 , 466 , 467 , and 468 may be removed to expand the forty-eighth to fifty-fifth holes 741 , 742 , 743 , 744 , 745 , 746 , 747 , and 748 in the first direction D1 .

[0213] refer to Fig.42, an anisotropic etching process can be performed on the third spacer layer 450 to form a third spacer 455, and the portion of the second barrier pattern 590 exposed by the third spacer 455 and the portion of the third insulating interlayer 390 thereunder can be removed, so that the upper surfaces of the first gate electrode 600 and the seventh to twelfth sacrificial patterns 381, 382, ​​383, 384, 385 and 386 can be exposed.

[0214] refer to Fig.43 , the seventh to twelfth sacrificial patterns 381 , 382 , 383 , 384 , 385 , and 386 may be removed to expand the forty-eighth to fifty-fifth holes 741 , 742 , 743 , 744 , 745 , 746 , 747 , and 748 in the first direction D1 , and thus the second spacer layer 370 may be partially exposed.

[0215] An anisotropic etching process may be performed on the exposed second spacer layer 370 to form a second spacer 375, and portions of the second barrier pattern 590 exposed by the second spacer 375 and portions of the second insulating pattern 275 thereunder may be removed so that the first gate electrode 600 and upper surfaces of the fifth and sixth sacrificial patterns 311 and 312 may be exposed.

[0216] The fifth and sixth sacrificial patterns 311 and 312 may be removed to expand the forty-eighth and forty-ninth holes 741 and 742 in the first direction D1 , and thus the first spacer layer 300 may be partially exposed.

[0217] An anisotropic etching process may be performed on the exposed first spacer layer 300 to form the first spacers 305 , and portions of the second barrier pattern 590 exposed by the first spacers 305 may be removed so that an upper surface of the first gate electrode 600 may be exposed.

[0218] Reference Fig.44 , first to eighth upper contact plugs 761 , 762 , 763 , 764 , 765 , 766 , 767 , and 768 may be formed in the forty-eighth to fifty-fifth holes 741 , 742 , 743 , 744 , 745 , 746 , 747 , and 748 , respectively.

[0219] A ninth upper contact plug 769 may be formed through the seventh insulating interlayer 730 to contact an upper surface of the second gate electrode 650. In example embodiments, the ninth upper contact plug 769 may be formed on a portion of the second region II of the substrate 100 adjacent to the first region I.

[0220] In some example embodiments, each of the first to ninth upper contact plugs 761 , 762 , 763 , 764 , 765 , 766 , 767 , 768 , and 769 may include a conductive pattern and a barrier pattern covering a sidewall and a lower surface of the conductive pattern.

[0221] refer to Fig.45 , an eighth insulating interlayer 770 may be formed on the seventh insulating interlayer 730 and the first to ninth upper contact plugs 761, 762, 763, 764, 765, 766, 767, and 768. A fifty-sixth hole 780 may be formed through the fourth insulating interlayer 470, the fifth insulating interlayer 560, the seventh insulating interlayer 730, and the eighth insulating interlayer 770 and the third spacer 455 to expose the upper surface of the sixth sacrificial pillar 416. The exposed sixth sacrificial pillar 416 may be removed so that the fifty-sixth hole 780 is expanded in the first direction D1 to expose the upper surface of the third lower wiring 184.

[0222] refer to Fig.46 , a through passage 790 may be formed in the enlarged fifty-sixth hole 780 .

[0223] In some example embodiments, the through via 790 may include a conductive pattern and a barrier pattern covering a sidewall and a lower surface of the conductive pattern.

[0224] Reference again Figures 9 to 12 After the ninth insulating interlayer 800 is formed on the eighth insulating interlayer 770 and the through via 790, a first upper via 810, a second upper via 820, a third upper via 825 and a fourth upper via 830 may be formed, the first upper via 810 extending through the seventh to ninth insulating interlayers 730, 770 and 800 to contact an upper surface of the second memory channel structure 720, the second upper via 820 extending through the eighth insulating interlayer 770 and the ninth insulating interlayer 800 to contact an upper surface of each of the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768, the third upper via 825 extending through the eighth insulating interlayer 770 and the ninth insulating interlayer 800 to contact an upper surface of the ninth upper contact plug 769, and the fourth upper via 830 extending through the ninth insulating interlayer 800 to contact an upper surface of the through via 790.

[0225] A tenth insulating interlayer 840 may be formed on the ninth insulating interlayer 800 and the first to fourth upper vias 810, 820, 825, and 830, and first to fourth upper wirings 850, 860, 865, and 870 may be formed through the tenth insulating interlayer 840 to contact upper surfaces of the first to fourth upper vias 810, 820, 825, and 830, respectively, to complete the manufacture of the semiconductor device.

[0226] As shown above, the forty-eighth to fifty-fifth holes 741, 742, 743, 744, 745, 746, 747 and 748 can be obtained by using reference Figures 1 to 8 The method of forming a hole shown is formed partially through the gate electrode structure to expose the upper surface of the corresponding one of the first gate electrodes 600 , and the first to third spacers 305 , 375 , and 455 may be formed on the sidewalls thereof.

[0227] Therefore, the first to eighth upper contact plugs 761, 762, 763, 764, 765, 766, 767 and 768 in the forty-eighth to fifty-fifth holes 741, 742, 743, 744, 745, 746, 747 and 748, respectively, can be electrically connected only to the corresponding first gate electrodes 600 among the first gate electrodes 600, respectively, and can be electrically insulated from the first gate electrodes 600 above the corresponding first gate electrodes 600 among the first gate electrodes 600.

[0228] Fig.47 is a cross-sectional view showing a semiconductor device according to an example embodiment, which may correspond to Figure 3 The semiconductor device can be used with Figures 9 to 12 The semiconductor devices are substantially the same or similar, and thus repeated descriptions are omitted here.

[0229] refer to Fig.47 , the semiconductor device may not include the second spacer 375 and the third insulating interlayer 390 , and thus the second mold layer and the third mold layer may not be distinguished from each other.

[0230] Therefore, the lower portion of each of the upper contact plugs may not be divided into the first and second lower portions with reference to the third insulating interlayer 390. Therefore, the width of the lower portion of each of the upper contact plugs may decrease from the top toward the bottom thereof in the first direction D1.

[0231] The third spacer 455 may cover the sidewall of the lower portion of each of the upper contact plugs, but may not be disposed on the uppermost fourth sacrificial layer 280 among the fourth sacrificial layers 280 included in the third mold layer and the second barrier pattern 590 contacting the uppermost fourth sacrificial layer 280 among the fourth sacrificial layers 280 .

[0232] Figures 9 to 12 The first support structure 350 shown in FIG. 4 may be merged into the second support structure 430 .

[0233] An eleventh insulating interlayer 930 may be formed instead of the fourth insulating interlayer 470 .

[0234] Figures 48 to 55 is along line A-A' (see Fig.10) to illustrate the manufacturing Fig.47 A method for a semiconductor device. The method may include Figures 13 to 46 and Figures 9 to 12 The processes shown are basically the same or similar processes, so their repeated descriptions are omitted here.

[0235] refer to Fig.48 , you can execute Figures 9 to 20 The process shown is basically the same or similar process, and in performing Figure 21 to Figure 24 The process shown can be performed with regard to Fig.25 The illustrated process is substantially the same or similar to a process such that a third mold layer may be formed on the second mold layer and the first and third sacrificial capping patterns 332 and 336 .

[0236] Thirty-third to thirty-fifth holes 402 , 404 , and 406 may be formed through the third mold layer to expose upper surfaces of the first to third sacrificial capping patterns 332 , 334 , and 336 , respectively.

[0237] refer to Fig.49 , the first to third sacrificial cover patterns 332, 334 and 336 exposed by the thirty-third to thirty-fifth holes 402, 404 and 406 can be removed to expand the thirty-third to thirty-fifth holes 402, 404 and 406 in the first direction D1, and fourth to sixth sacrificial pillars 412, 414 and 416 can be formed in the expanded thirty-third and thirty-fifth holes 402, 404 and 406, respectively.

[0238] refer to Fig.50 , the fifth sacrificial pillar 414 may be removed to form a fifty-seventh hole, and a third support structure 435 may be formed in the fifty-seventh hole.

[0239] The third support structure 435 may include oxide (eg, silicon oxide).

[0240] refer to Fig.51 , you can execute Figures 1 to 8 The illustrated process is substantially the same or similar to the process, so that fifty-eighth to sixty-fifth holes 901 , 902 , 903 , 904 , 905 , 906 , 907 , and 908 may be formed to partially penetrate the second and third mold layers on the second region II of the substrate 100 .

[0241] In some example embodiments, the fifty-eighth to sixty-fifth holes 901, 902, 903, 904, 905, 906, 907, and 908 may be formed to be spaced apart from each other in the second direction D2 on the second region II of the substrate 100. The fifty-eighth hole 901 and the fifty-ninth hole 902 may expose the upper surface of the lowermost second insulating layer 270 of the second mold layer and may overlap the fifth sacrificial pattern 311 and the sixth sacrificial pattern 312 in the first direction D1, respectively.

[0242] The sixtieth to sixty-fifth holes 903, 904, 905, 906, 907, and 908 may expose upper surfaces of corresponding fourth sacrificial layers 280 in the fourth sacrificial layers 280 of the second mold layer or the third mold layer, respectively. For example, the sixtieth hole 903 may expose an upper surface of the lowermost fourth sacrificial layer 280 in the fourth sacrificial layers 280 included in the second mold layer, and the sixty-fifth hole 908 may expose an upper surface of the fourth sacrificial layer 280 at the second level from above of the fourth sacrificial layers 280 included in the third mold layer.

[0243] refer to Fig.52 , a fourth spacer layer 910 may be formed on inner walls of the fifty-eighth to sixty-fifth holes 901, 902, 903, 904, 905, 906, 907, and 908. Twenty-first to twenty-eighth sacrificial patterns 921, 922, 923, 924, 925, 926, 927, and 928 may be formed in the fifty-eighth to sixty-fifth holes 901, 902, 903, 904, 905, 906, 907, and 908, respectively.

[0244] An eleventh insulating interlayer 930 may be formed on the twenty-first to twenty-eighth sacrificial patterns 921 , 922 , 923 , 924 , 925 , 926 , 927 and 928 , the uppermost second insulating layer 270 among the second insulating layers 270 included in the third mold layer, the fourth and sixth sacrificial pillars 412 and 416 , and the third supporting structure 435 .

[0245] refer to Fig.53 , you can execute Figures 30 to 37 The processes shown are substantially the same or similar processes to form the first memory channel structure 550 , the fifth insulating interlayer 560 , the channel connection pattern 580 , the second barrier pattern 590 , the first gate electrode 600 , and the first and second dividing patterns 610 and 615 .

[0246] refer to Fig.54 , you can execute Figures 38 to 43 The processes shown are substantially the same or similar processes to form the second gate electrode 650 , the second memory channel structure 720 , the third dividing pattern 660 , the seventh insulating interlayer 730 , and the like.

[0247] In addition, forty-eighth to fifty-fifth holes 741 , 742 , 743 , 744 , 745 , 746 , 747 , and 748 as well as the first spacer 305 and the fourth spacer 915 may be formed.

[0248] Reference Fig.55 , tenth to seventeenth upper contact plugs 951 , 952 , 953 , 954 , 955 , 956 , 957 , and 958 may be formed in the forty-eighth to fifty-fifth holes 741 , 742 , 743 , 744 , 745 , 746 , 747 , and 748 , respectively.

[0249] Reference again Fig.47 , you can execute Fig.46 and Figures 9 to 12 The processes shown are basically the same or similar processes to complete the manufacture of semiconductor devices.

[0250] Although certain example embodiments have been shown and described in detail, a person skilled in the art will understand that changes in form and details may be made therein without departing from the spirit and scope of the claims.

[0251] This application claims the priority benefit of Korean Patent Application No. 10-2023-0121268 filed in the Korean Intellectual Property Office on September 12, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a gate electrode structure on a substrate, the gate electrode structure comprising gate electrodes sequentially stacked and spaced apart from each other in a first direction, the first direction being substantially perpendicular to an upper surface of the substrate, and each of the gate electrodes extending in a second direction, the second direction being substantially parallel to the upper surface of the substrate; a memory channel structure extending through the gate electrode structure; as well as A contact plug partially extends through the gate electrode structure to contact an upper surface of a first gate electrode among the gate electrodes, the contact plug extends through a second gate electrode but is electrically insulated from the second gate electrode, the second gate electrode is above the first gate electrode, and at least a portion of the contact plug has a width that decreases in a stepwise manner from a top toward a bottom thereof in the first direction.

2. The semiconductor device according to claim 1, further comprising: A spacer is provided on a sidewall of the contact plug, the spacer electrically insulating the second gate electrode from the contact plug.

3. The semiconductor device according to claim 2, wherein The contact plug includes a lower portion and an upper portion stacked in the first direction, and The spacer is on a sidewall of the lower portion of the contact plug. 4 . The semiconductor device according to claim 3 , wherein a width of an upper surface of the lower portion of the contact plug is greater than a width of a lower surface of the upper portion of the contact plug.

5. The semiconductor device according to claim 4, wherein The lower portion of the contact plug includes a first lower portion and a second lower portion stacked in the first direction, and Each of the first lower portion and the second lower portion of the contact plug has a width that decreases in a stepwise manner from a top toward a bottom thereof in the first direction.

6. The semiconductor device according to claim 1, further comprising: A barrier pattern including a metal oxide covers a lower surface and an upper surface of each of the gate electrodes, a sidewall of each of the gate electrodes faces the memory channel structure, and a sidewall of each of the gate electrodes faces the contact plug.

7. The semiconductor device according to claim 6, further comprising: spacers on sidewalls of the contact plug, wherein the spacer contacts a sidewall of the barrier pattern.

8. The semiconductor device according to claim 1, further comprising: a plurality of contact plugs, the contact plug being one of the plurality of contact plugs, wherein heights of lower surfaces of the plurality of contact plugs decrease in the second direction.

9. The semiconductor device according to claim 8, further comprising: a support structure extending through the gate electrode structure, In the top view, each of the plurality of contact plugs is located inside a region defined by the support structure. 10 . The semiconductor device according to claim 1 , wherein the gate electrodes have substantially the same length in the second direction.

11. A semiconductor device comprising: a gate electrode structure on a substrate, the gate electrode structure comprising gate electrodes sequentially stacked and spaced apart from each other in a first direction, the first direction being substantially perpendicular to an upper surface of the substrate, and each of the gate electrodes extending in a second direction, the second direction being substantially parallel to the upper surface of the substrate; a memory channel structure extending through the gate electrode structure; an insulating interlayer on the gate electrode structure and the memory channel structure; as well as a contact plug extending through the insulating interlayer and a portion of the gate electrode structure to contact an upper surface of a first one of the gate electrodes, the contact plug extending through a second one of the gate electrodes but being electrically insulated from the second one, the second gate electrode being above the first one of the gate electrodes, The contact plug comprises: a first lower portion and a second lower portion stacked in the first direction and extending through the portion of the gate electrode structure, and an upper portion on the second lower portion and extending through the insulating interlayer, and Each of the first lower portion and the second lower portion has a width that decreases in a stepwise manner from a top toward a bottom thereof in the first direction. 12 . The semiconductor device according to claim 11 , wherein a width of an upper surface of the second lower portion of the contact plug is greater than a width of a lower surface of the upper portion of the contact plug.

13. The semiconductor device according to claim 11, further comprising: A spacer is provided on sidewalls of the first lower portion and the second lower portion of the contact plug, the spacer comprising an insulating material.

14. The semiconductor device according to claim 13, wherein The spacer includes a first spacer portion and a second spacer portion on the sidewalls of the first lower portion and the second lower portion of the contact plug, respectively, and Wherein the first spacer portion and the second spacer portion are not in contact with each other.

15. The semiconductor device according to claim 11, further comprising: A barrier pattern including a metal oxide covers a lower surface and an upper surface of each of the gate electrodes, a sidewall of each of the gate electrodes faces the memory channel structure, and a sidewall of each of the gate electrodes faces the contact plug.

16. A semiconductor device comprising: A gate electrode structure, comprising: first gate electrodes on the first region and the second region of the substrate, the first gate electrodes being sequentially stacked and spaced apart from each other in a first direction, the first direction being substantially perpendicular to an upper surface of the substrate, and each of the gate electrodes extending in a second direction, the second direction being substantially parallel to the upper surface of the substrate, and a second gate electrode on the first region of the substrate and a portion of the second region adjacent to the first region and above the first gate electrode; a memory channel structure extending through the gate electrode structure on the first region of the substrate; a support structure extending through the first gate electrode on the second region of the substrate; an insulating interlayer on the substrate, the insulating interlayer covering the gate electrode structure, the memory channel structure and the support structure; and first contact plugs, each of which extends through the insulating interlayer and at least one of the first gate electrodes to contact a first one of the first gate electrodes, each of which extends through a second one of the first gate electrodes but is electrically insulated from the second one, the second one being above the first one of the first gate electrodes, Each of the first contact plugs comprises: extending through an upper portion of the insulating interlayer, and At least a portion of the lower portion, which is below the upper portion, has a width that decreases from a top toward a bottom thereof in the first direction. 17 . The semiconductor device according to claim 16 , wherein a width of an upper surface of the lower portion of each of the first contact plugs is greater than a width of a lower surface of the upper portion of each of the first contact plugs.

18. The semiconductor device according to claim 16, wherein The lower portion of each of the first contact plugs includes a first lower portion and a second lower portion stacked in the first direction, and Each of the first lower portion and the second lower portion of each of the first contact plugs has a width that decreases in a stepwise manner from a top toward a bottom thereof in the first direction.

19. The semiconductor device according to claim 16, further comprising: A second contact plug extends through the insulating interlayer to contact an upper surface of the second gate electrode.

20. The semiconductor device according to claim 16, wherein The first contact plugs are spaced apart from each other in the second direction, and A height of a lower surface of the first contact plug decreases in the second direction.

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