Memory element and forming method thereof

Abstract

The invention discloses a memory element and a forming method thereof. The memory element comprises a substrate, a lamination layer and a stacking structure from bottom to top. A plurality of vertical channel pillars pass through the stack structure and the stack-up. The plurality of first isolation structures are arranged on the sides of the plurality of vertical channel columns and pass through the lower part of the stack structure. The plurality of second isolation structures are disposed over the plurality of first isolation structures, respectively, and pass through the upper portion of the stack structure. A plurality of common source lines are disposed on the sides of the plurality of vertical channel pillars and pass through the stacked structure and a portion of the stack. From a top view, the plurality of common source lines extend in a first direction, and each of the plurality of first isolation structures and the plurality of second isolation structures has two wide end portions in the first direction, respectively adjoining two common source lines. The memory element can be applied to a process for manufacturing a 3D NAND flash memory with high capacity and high performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a method for forming the same, and in particular to a memory element and a method for forming the same. Background Art

[0002] Non-volatile memory elements (eg, flash memory) have become a widely used memory element in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.

[0003] The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. Summary of the invention

[0004] The invention provides a memory element and a forming method thereof, which can form a memory element with high reliability.

[0005] The present invention provides a memory element, which includes a substrate, a stack and a stack structure from bottom to top. A plurality of vertical channel columns pass through the stack structure and the stack. A plurality of first isolation structures are arranged on the sides of the plurality of vertical channel columns and pass through the lower part of the stack structure. A plurality of second isolation structures are respectively arranged above the plurality of first isolation structures and pass through the upper part of the stack structure. A plurality of common source lines are arranged on the sides of the plurality of vertical channel columns and pass through the stack structure and part of the stack. From a top view, the plurality of common source lines extend in a first direction, and each of the plurality of first isolation structures and the plurality of second isolation structures has two wide ends in the first direction, respectively adjacent to two common source lines.

[0006] The present invention further provides a method for forming a memory element, comprising the following steps. A stack is formed on a substrate. A stack structure is formed on the stack, wherein the stack structure comprises a plurality of insulating layers and a plurality of conductor layers stacked alternately. A plurality of vertical channel columns, a plurality of first isolation structures, and a plurality of second isolation structures are formed in the stack structure, wherein the plurality of vertical channel columns pass through the stack structure and the stack, a plurality of first isolation structures pass through the lower portion of the stack structure, and a plurality of second isolation structures are respectively arranged above the plurality of first isolation structures and pass through the upper portion of the stack structure. From a top view, each of the plurality of first isolation structures and the plurality of second isolation structures has two wide ends in the first direction.

[0007] Based on the above, in the present invention, wide ends are formed on both sides of the isolation structure to prevent seams from being formed in the isolation structure due to over-etching when forming the vertical channel, thereby preventing the conventional short circuit problem between adjacent source lines caused by filling the seams with tungsten layers in the subsequent replacement process. Therefore, the reliability of the memory element formed by the present invention can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A and Fig. 7A It is a cross-sectional schematic diagram of a method for forming a memory element according to an embodiment of the present invention.

[0009] Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B is a simplified top view of a method for forming a memory device according to an embodiment of the present invention.

[0010] Fig. 8A , Fig.9A and Fig. 10A is a cross-sectional schematic diagram of a method for forming a memory element according to another embodiment of the present invention.

[0011] Figure 8B , Fig. 9B and Fig. 10B is a simplified top view of a method for forming a memory device according to another embodiment of the present invention.

[0012] 10: Base

[0013] 20: Component layer

[0014] 30: Insulation layer

[0015] 100, 102: Memory components

[0016] 110: Conductor layer

[0017] 111: Overlay

[0018] 112: Insulation layer

[0019] 114: Insulation layer

[0020] 116: Middle layer

[0021] 117: Conductor plug

[0022] 118: First isolation structure

[0023] 118CP: Narrow middle

[0024] 118EP: Wide end

[0025] 120: Charge storage structure

[0026] 122: Channel layer

[0027] 124: Insulation column

[0028] 128: Second isolation structure

[0029] 128CP: Narrow middle

[0030] 128EP: Wide end

[0031] 130: Vertical channel

[0032] 131: Conductor layer

[0033] 132: Etch stop layer

[0034] 134: Horizontal channel

[0035] 136: Common source line

[0036] BK1, BK2: Block

[0037] D1, D2, D3: Direction

[0038] LP: Lower

[0039] SK: Stacked structure

[0040] UP: upper part

[0041] V1: Confined space

[0042] V2: Closed gap

[0043] VC: Vertical Channel Column

[0044] VCH: Vertical Channel Hole

[0045] W1: Width

[0046] W2: Width DETAILED DESCRIPTION

[0047] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same elements will be described with the same symbols in the following description.

[0048] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

[0049] Directional terms used herein, such as "above", "below", etc., are only used to refer to the directions of the drawings and are not intended to limit the present invention. Therefore, it should be understood that "above" can be used interchangeably with "below", and when an element such as a layer or film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

[0050] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A and Fig. 7A It is a cross-sectional schematic diagram of a method for forming a memory element according to an embodiment of the present invention. Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B 1 is a simplified top view of a method for forming a memory element according to an embodiment of the present invention, wherein for the sake of clarity and ease of description, only a few components are shown, and these components are not at the same level. In one embodiment, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A and Fig. 7A Along Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B The cross-sectional view is shown along the II line.

[0051] Please refer to Figure 1A, providing a substrate 10. In one embodiment, the substrate 10 includes a semiconductor substrate, such as a silicon-containing substrate. Then, a device layer 20 is formed on the substrate 10. In one embodiment, the device layer 20 may include various semiconductor devices that are generally known. In one embodiment, the device layer 20 may include a metal oxide semiconductor (MOS) transistor formed on the surface of the substrate 10 and an internal connection structure electrically connected to the metal oxide semiconductor transistor, but the present invention is not limited thereto. The internal connection structure includes a plurality of dielectric layers and a plurality of internal connections in the plurality of dielectric layers. Then, an insulating layer 30 is formed on the device layer 20. In one embodiment, the material of the insulating layer 30 includes silicon oxide.

[0052] Afterwards, a stack 111 is formed on the insulating layer 30. The stack 111 includes a plurality of insulating layers 112 and a plurality of conductive layers 110 alternately stacked in the D3 direction (e.g., the Z direction). In one embodiment, the material of the insulating layer 112 includes silicon oxide, and the material of the conductive layer 110 includes doped polysilicon. The present invention does not limit the number of the insulating layer 112 and the conductive layer 110.

[0053] Please continue to refer to Figure 1A , a stacking structure SK is formed on the stack 111. The stacking structure SK includes a lower part LP and an upper part UP. In one embodiment, each of the lower part LP and the upper part UP of the stacking structure SK includes a plurality of insulating layers 114 and a plurality of intermediate layers 116 alternately stacked in the D3 direction (such as the Z direction). The present invention does not limit the number of insulating layers 114 and intermediate layers 116. In one embodiment, the insulating layer 114 includes an oxide layer, and the intermediate layer 116 includes a nitride layer, but the present invention is not limited thereto. In other embodiments, the insulating layer 114 and the intermediate layer 116 may be other dielectric material layers, as long as there is an etching selectivity between the insulating layer 114 and the intermediate layer 116. In one embodiment, the intermediate layer 116 is used as a sacrificial layer, and a subsequent replacement process will be performed. In another embodiment, when the intermediate layer 116 is a doped polysilicon layer, a subsequent replacement process will not be performed.

[0054] In one embodiment, the lower LP of the stacked structure SK is first formed. Then, a plurality of first isolation structures 118 are formed in the lower LP of the stacked structure SK. In one embodiment, the first isolation structure 118 is also referred to as a "global select line cut (GLC) insulator". The method for forming the first isolation structure 118 includes: performing a patterning process (e.g., a photolithography process) on the lower LP of the stacked structure SK to form a plurality of first holes; filling the first holes with an isolation material (e.g., silicon oxide); and performing a chemical mechanical polishing (CMP) process to remove excess isolation material outside the first holes. The first isolation structure 118 passes through at least one insulating layer 114 and at least one intermediate layer 116 in the D3 direction (e.g., the Z direction).

[0055] In one embodiment, the first isolation structure 118 has substantially vertical sidewalls, such as Figure 1A In another embodiment, the first isolation structure 118 may have an inclined sidewall. In one embodiment, the first isolation structure 118 may have a single-layer or multi-layer structure.

[0056] In this embodiment, the lower end of each first isolation structure 118 is surrounded by the insulating layer 114, and the upper end is surrounded by the intermediate layer 116. Figure 1A However, the present invention is not limited thereto. In another embodiment, the lower end of each first isolation structure 118 is surrounded by the middle layer 116, and the upper end is surrounded by the insulating layer 114. In other embodiments, the lower end and the upper end of each first isolation structure 118 may be both surrounded by the insulating layer 114, or both surrounded by the middle layer 116.

[0057] Each first isolation structure 118 has a dumbbell-like shape in a top view. Figure 1B As shown. More specifically, from a top view, each first isolation structure 118 has a narrow middle portion 118CP and two wide end portions 118EP located on both sides of the narrow middle portion 118CP in a direction D1 (such as the X direction). The narrow middle portion 118CP has a bar-like shape, and the wide end portions 118EP have a circle-like shape. In one embodiment, the size of the wide end portions 118EP in a direction D2 (such as the Y direction) is greater than the size of the narrow middle portion 118CP in the direction D2, and the direction D2 is perpendicular to the direction D1. In one embodiment, from a top view, each narrow middle portion 118CP has a substantially fixed width, and each wide end portion 118EP has a variable width.

[0058] Still refer to Figure 1A, forming an upper portion UP of the stacked structure SK on the lower portion LP of the stacked structure SK. In one embodiment, the uppermost layer of the stacked structure SK is an insulating layer 114. This uppermost insulating layer 114 may also be referred to as a "top cap layer". The uppermost insulating layer 114 has a flat top surface. In one embodiment, the method for forming the uppermost insulating layer 114 includes forming a top cap material layer on the stacked structure and then performing a planarization process, such as a chemical mechanical polishing process.

[0059] Please refer to Figure 2A , a plurality of vertical channel pillars VC are formed in the stack 111 and the stack structure SK. The plurality of vertical channel pillars VC are located on the sides of the plurality of first isolation structures 118, such as Figure 2A and Figure 2B As shown. In one embodiment, a patterning process (e.g., a photolithography process) is performed to form a plurality of vertical channel holes VCH in the stack 111 and the stack structure SK. Then, a charge storage structure 120 is conformally formed on the sidewall and bottom surface of the vertical channel hole VCH. In one embodiment, the charge storage structure 120 may be an oxide / nitride / oxide (ONO) composite layer. Next, a channel layer 122 is formed on the charge storage structure 120 in the vertical channel hole VCH. In one embodiment, the material of the channel layer 122 includes polysilicon. Thereafter, an insulating column 124 is formed on the channel layer 122 in the vertical channel hole VCH. In one embodiment, the material of the insulating column 124 includes silicon oxide. In one embodiment, the charge storage structure 120, the channel layer 122, and the insulating column 124 may constitute a vertical channel column VC. Thereafter, a conductor plug 117 is formed on the upper portion of the vertical channel hole VCH, and the conductor plug 117 is in contact with the channel layer 122. In one embodiment, the material of the conductive plug 117 includes doped polysilicon.

[0060] Please refer to Figure 3A , a plurality of second isolation structures 128 are formed in the upper portion UP of the stack structure SK. In one embodiment, the second isolation structure 128 is also referred to as a "string select line cut (GSC) insulator". The method for forming the second isolation structure 128 includes: performing a patterning process (e.g., a photolithography process) on the upper portion UP of the stack structure SK to form a plurality of second holes; filling the second holes with an isolation material (e.g., silicon oxide); and performing a chemical mechanical polishing process to remove excess isolation material outside the second holes. The second isolation structure 128 passes through at least one insulating layer 114 and at least one intermediate layer 116 in the D3 direction (e.g., the Z direction).

[0061] In one embodiment, the second isolation structure 128 has substantially vertical sidewalls, such as Figure 3AIn another embodiment, the second isolation structure 128 may have an inclined sidewall. In one embodiment, the second isolation structure 128 may have a single-layer or multi-layer structure.

[0062] In this embodiment, the lower end of each second isolation structure 128 is surrounded by the insulating layer 114, and the upper end is flush with the uppermost intermediate layer 116. Figure 3A However, the present invention is not limited thereto. In another embodiment, the lower end of each second isolation structure 128 is surrounded by the middle layer 116, and the upper end is surrounded by the insulating layer 114. In other embodiments, the lower end and the upper end of each second isolation structure 128 may be both surrounded by the insulating layer 114, or both surrounded by the middle layer 116.

[0063] The top view of each second isolation structure 128 has a dumbbell-like shape, as shown in FIG. Figure 3B As shown. More specifically, from a top view, each second isolation structure 128 has a narrow middle portion 128CP and two wide end portions 128EP located on both sides of the narrow middle portion 128CP in a direction D1 (such as the X direction). The narrow middle portion 128CP has a bar-like shape, and the wide end portions 128EP have a circle-like shape. In one embodiment, the size of the wide end portions 128EP in a direction D2 (such as the Y direction) is greater than the size of the narrow middle portion 128CP in the direction D2, and the direction D2 is perpendicular to the direction D1. In one embodiment, from a top view, each narrow middle portion 128CP has a substantially fixed width, and each wide end portion 128EP has a variable width.

[0064] In one embodiment, if Figure 3A As shown, the first isolation structure 118 and the second isolation structure 128 are separated by at least one insulating layer 114 and at least one intermediate layer 116 in the D3 direction (such as the Z direction). The first isolation structure 118 and the second isolation structure 128 are substantially aligned in the D3 direction (such as the Z direction). In one embodiment, the first isolation structure 118 has a width W1, and the second isolation structure 128 has a width W2, and the width W2 is greater than the width W1.

[0065] from Figure 3BFrom the top view of the structure 118, the plurality of second isolation structures 128 overlap with the plurality of first isolation structures 118, and the plurality of second isolation structures 128 are respectively located within the boundaries of the plurality of first isolation structures 118. More specifically, the size of the narrow middle portion 118CP of the first isolation structure 118 in the direction D2 (such as the Y direction) is larger than the size of the narrow middle portion 128CP of the second isolation structure in the direction D2, and the size of the wide end portion 118EP of the first isolation structure 118 in the direction D2 (such as the Y direction) is larger than the size of the wide end portion 128EP of the second isolation structure in the direction D2.

[0066] Please refer to Figure 4A , a plurality of vertical channels 130 are formed in the partial stack 111 and the stack structure SK. The method for forming the vertical channels 130 includes performing a photolithography process. In one embodiment, the vertical channels 130 may be referred to as "slits". In one embodiment, the vertical channels 130 expose the insulating layer 112 of the stack 111. In one embodiment, the vertical channels 130 have substantially vertical sidewalls, such as Figure 4A In another embodiment, the vertical channel 130 may have an inclined sidewall.

[0067] from Figure 4B From the top view of FIG. 1 , the plurality of vertical channels 130 extend in the direction D1 (e.g., the X direction). In one embodiment, each first isolation structure 118 has two wide ends 118EP in the direction D1, respectively adjacent to the two vertical channels 130. In one embodiment, each of the second isolation structures 128 has two wide ends 128EP in the direction D1, respectively adjacent to the two vertical channels 130.

[0068] In one embodiment, during the step of forming the plurality of vertical channels 130, the wide end portion 118EP of the first isolation structure 118 and the wide end portion 128EP of the second isolation structure 128 are also partially removed. Figure 4B From a top view, each vertical channel 130 exposes a wide end portion 118EP of a corresponding first isolation structure 118 and a wide end portion 128EP of a corresponding second isolation structure 128 .

[0069] Next, the plurality of intermediate layers 116 in the stacked structure SK are replaced with a plurality of conductive layers 131. More specifically, after the replacement process, the stacked structure SK includes a plurality of insulating layers 114 and a plurality of conductive layers 131 alternately stacked on the substrate 10. In one embodiment, when the intermediate layer 116 is a doped polysilicon layer, the replacement step may be omitted as appropriate.

[0070] In one embodiment, a selective etching process is performed so that the etchant contacts the middle layer 116 of the stacked structure SK exposed by the vertical channel 130. Thus, the middle layer 116 of the stacked structure SK is etched and removed to form a plurality of horizontal openings. The selective etching process may be an isotropic etching process, such as a wet etching process. The etchant used in the wet etching process may be, for example, hot phosphoric acid. Then, a conductor material layer is formed on the surface of the stacked structure SK, in the vertical channel 130, and in the horizontal openings. In one embodiment, the conductor material layer includes a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The material of the metal layer includes tungsten (W). Then, a back etching process is performed to remove the surface of the stacked structure SK and the conductor material layer in the vertical channel 130. The remaining conductor material layer forms a conductor layer 131 in the horizontal opening.

[0071] Please refer to Figure 5A An etch stop layer 132 is conformally formed on the upper surface of the stacked structure SK and the sidewalls and bottom surface of the vertical trench 130. In one embodiment, the etch stop layer 132 includes an insulating layer, such as a nitride / oxide / nitride (NON) composite layer. Figure 5B From a top view of FIG. 1 , the etch stop layer 132 physically contacts the wide end portion 118EP of the first isolation structure 118 and the wide end portion 128EP of the second isolation structure 128 .

[0072] Please refer to Fig. 6A as well as Figure 6B , deepen the depth of the vertical channel 130, and remove part of the etching stop layer 132, so that the remaining etching stop layer 132 remains on the sidewall of the vertical channel 130 in the form of a spacer. Then, the conductor layer 110 in the middle of the stack 111 and the underlying insulating layer 112 and the overlying insulating layer 112 are removed to form a horizontal channel 134 in the stack 111. The above removal step will also remove part of the charge storage layer 120 of each vertical channel column VC at the same time. In one embodiment, the horizontal channel 134 exposes part of the channel layer 122 of each vertical channel column VC. More specifically, the channel layer 122 of each vertical channel column VC is discontinuous in the stack 111. In one embodiment, the above removal step will also thin the etching stop layer 132. For example, the original nitride / oxide / nitride (NON) etching stop layer 132 is thinned into a nitride layer.

[0073] Please refer to Fig. 7A, a conductive layer 110′, such as a doped polysilicon layer, is backfilled in the horizontal channel 134. In one embodiment, a doped polysilicon layer is formed on the surface of the stacked structure SK, in the vertical channel 130, and in the horizontal channel 134. Then, an etch-back process is performed to remove the surface of the stacked structure SK and the doped polysilicon layer in the vertical channel 130. The conductive layer 110′ in the horizontal channel 134, the underlying conductive layer 110, and the overlying conductive layer 110 form a common source line or a ground line.

[0074] Please continue to refer to Fig. 7A , a plurality of common source lines 136 are respectively formed in the plurality of vertical channels 130. The common source lines 136 are formed in the form of a conductor wall. The plurality of common source lines 136 extend in a direction D1 (such as the X direction). In one embodiment, a conductive material (such as tungsten) is filled on the surface of the stacked structure SK and in the vertical channel 130, and then a planarization process is performed to remove the conductive material outside the vertical channel 130. In one embodiment, each common source line 136 is electrically isolated from the adjacent conductor layer 131 by an etching stop layer 132. In another embodiment, the etching stop layer 132 may be removed first, an isolation column may be formed in the vertical channel 130, and then a common source line 136 passing through the isolation column may be formed. Next, a bit line (BL) may be formed on the stacked structure SK, which is electrically connected to the conductor plug 117 of the vertical channel column VC below through a plurality of conductor contact windows. At this point, the memory element 100 of the present invention is completed.

[0075] In the memory element 100 of the invention, the stack structure SK may include a lower section, a middle section, and an upper section. The conductor layer 131 of the lower section of the stack structure SK serves as a plurality of global select lines (GSL). The conductor layer 131 of the middle section of the stack structure SK serves as a word line (WL). The conductor layer 131 of the upper section of the stack structure SK serves as a string select line (SSL). A plurality of global select line cut (GLC) insulators (such as the first isolation structure 118) are configured in the global select line GSL, and a plurality of string select line cut (GSC) insulators (such as the second isolation structure 128) are configured in the string select line SSL. In this configuration, different blocks BK1, BK2 (such as Figure 7B The operations of the memory devices will not interfere with each other, thus improving the performance of the memory devices.

[0076] During the vertical channel formation process, the seams formed by over-etching will "open" the traditional single-size GLC / GSC insulator, and the tungsten layer of the subsequent replacement process will fill the seams and cause the traditional short circuit problem between adjacent common source lines. In the present invention, since the first isolation structure 118 and / or the second isolation structure 128 are designed to have wide ends, the traditional short circuit problem will not occur.

[0077] In the above-mentioned embodiment, the first isolation structure 118 and / or the second isolation structure 128 are non-porous isolation structures. However, the present invention is not limited thereto. In another embodiment, under the process margin / , the first isolation structure 118 and / or the second isolation structure 128 may have a closed gap, and the closed gap will not cause the traditional short circuit problem.

[0078] Fig. 8A , Fig.9A and Fig. 10A is a cross-sectional schematic diagram of a method for forming a memory element according to another embodiment of the present invention. Figure 8B , Fig. 9B and Fig. 10B FIG. 1 is a simplified top view of a method for forming a memory element according to another embodiment of the present invention, wherein only a few components are shown for the sake of clarity and ease of description, and these components are not at the same level. In one embodiment, Fig. 8A , Fig.9A and Fig. 10A is along Figure 8B , Fig. 9B and Fig. 10B The cross-sectional view is shown along the II line. FIG. 8A to FIG. 10B Methods and Figures 1A to 7B The method is similar to that of , and the differences are described below, while the similarities are not repeated here.

[0079] First, conduct Figure 1A , Figure 1B The steps to form Fig. 8A , Figure 8B The intermediate structure. Figure 8B It can be seen from the top view that a closed gap V1 is formed in the wide end portion 118EP of the first isolation structure 118 .

[0080] Next, proceed FIG. 2A to FIG. 3B The steps to form Fig.9A , Fig. 9B The intermediate structure. Fig. 9B It can be seen from the top view that a closed gap V2 is formed in the wide end portion 128EP of the second isolation structure 128 .

[0081] Then, proceed FIG. 4A to FIG. 7B The steps to form Fig. 10A , Fig. 10B The memory element 102 is provided.

[0082] Below, we will refer to Fig. 7A , Figure 7B , Fig. 10A and Fig. 10B The structure of the memory element of the present invention is described. In one embodiment, the memory element 100 / 102 includes a substrate 10, a stack 111 and a stack structure SK from bottom to top. A plurality of vertical channel pillars VC pass through the stack structure SK and the stack 111. A plurality of first isolation structures 118 are arranged on the sides of the plurality of vertical channel pillars VC and pass through the lower part LP of the stack structure SK. A plurality of second isolation structures 128 are respectively arranged above the plurality of first isolation structures 118 and pass through the upper part UP of the stack structure. A plurality of common source lines 136 are arranged on the sides of the plurality of vertical channel pillars VC and pass through the stack structure SK and a portion of the stack 111. From a top view, the plurality of common source lines 136 extend in a first direction D1, and each of the plurality of first isolation structures 118 and the plurality of second isolation structures 128 has two wide end portions 118EP / 128EP in the first direction D1, respectively adjacent to two common source lines 136.

[0083] In one embodiment, from a top view, the plurality of second isolation structures 128 overlap with the plurality of first isolation structures 118 , respectively, and the plurality of second isolation structures 128 are located within boundaries of the plurality of first isolation structures 118 , respectively.

[0084] In one embodiment, from a top view, each of the plurality of first isolation structures 118 and the second isolation structure 128 further has a narrow middle portion 118CP / 128CP between the two wide end portions 118EP / 128EP in the first direction D1, and the size of the wide end portion 118EP / 128EP in the second direction D2 is greater than the size of the narrow middle portion 118CP / 128CP in the second direction D2, and the second direction D2 is perpendicular to the first direction D1.

[0085] In one embodiment, a size of the wide end portion 118EP of the first isolation structure 118 in the second direction D2 is greater than a size of the wide end portion 128EP of the second isolation structure 128 in the second direction D2.

[0086] In one embodiment, a size of the narrow middle portion 118CP of the first isolation structure 118 in the second direction D2 is greater than a size of the narrow middle portion 128CP of the second isolation structure 128 in the second direction D2.

[0087] In one embodiment, each narrow middle portion 118CP / 128CP has a substantially constant width, and each wide end portion 118EP / 128EP has a varying width, as viewed from a top view.

[0088] In one embodiment, the stacked structure SK includes a plurality of alternately stacked insulating layers 114 and a plurality of conductive layers 131. In one embodiment, the plurality of first isolation structures 118 and the plurality of second isolation structures 128 are respectively aligned in a third direction D3 and are separated by at least one conductive layer 131, and the third direction D3 is perpendicular to the first direction D1.

[0089] In one embodiment, the wide ends 118EP / 128EP of the plurality of first isolation structures 118 and the plurality of second isolation structures 128 have closed gaps V1 / V2 therein.

[0090] In summary, in the present invention, wide ends are formed on both sides of the source line isolation structure to prevent seams from being formed in the isolation structure due to over-etching when forming a vertical channel, thereby preventing the conventional short circuit problem between adjacent source lines caused by filling the seams with a tungsten layer in the subsequent replacement process. Therefore, the reliability of the memory element formed by the present invention can be greatly improved.

[0091] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.

Claims

1. A memory element, characterized in that: include: A laminate, configured on a substrate; A stacking structure, arranged on the stack; a plurality of vertical channel columns passing through the stacked structure and the laminate; A plurality of first isolation structures are arranged on the sides of the plurality of vertical channel columns and pass through the lower portion of the stacked structure; A plurality of second isolation structures, respectively disposed above the plurality of first isolation structures and passing through an upper portion of the stacked structure; as well as A plurality of common source lines are arranged on the sides of the plurality of vertical channel pillars and pass through the stack structure and a portion of the stack. From a top view, the plurality of common source lines extend in a first direction, and each of the plurality of first isolation structures and the plurality of second isolation structures has two wide ends in the first direction, respectively adjacent to two common source lines.

2. The memory device according to claim 1, characterized in that From a top view, the plurality of second isolation structures overlap with the plurality of first isolation structures respectively, and the plurality of second isolation structures are respectively located within boundaries of the plurality of first isolation structures.

3. The memory device according to claim 1, wherein: From a top view, each of the multiple first isolation structures and the second isolation structures also has a narrow middle portion between the two wide ends in the first direction, wherein the size of the wide end in the second direction is larger than the size of the narrow middle portion in the second direction, and the second direction is perpendicular to the first direction.

4. The memory element according to claim 3, characterized in that A dimension of the wide end portion of the first isolation structure in the second direction is greater than a dimension of the wide end portion of the second isolation structure in the second direction.

5. The memory device according to claim 3, characterized in that A dimension of the narrow middle portion of the first isolation structure in the second direction is greater than a dimension of the narrow middle portion of the second isolation structure in the second direction.

6. The memory device according to claim 3, characterized in that From a top view, each narrow middle portion has a substantially constant width, and each wide end portion has a varying width.

7. The memory device according to claim 1, wherein: The stacking structure includes a plurality of insulating layers and a plurality of conductive layers stacked alternately.

8. The memory device according to claim 7, characterized in that The plurality of first isolation structures and the plurality of second isolation structures are respectively aligned in a third direction and are separated by at least one conductor layer, and the third direction is perpendicular to the first direction.

9. The memory device according to claim 1, wherein: The first and second isolation structures have closed gaps therein at the wide ends.

10. A method for forming a memory element, characterized in that: include: forming a laminate on a substrate; forming a stacking structure on the stack, the stacking structure comprising a plurality of insulating layers and a plurality of conductor layers stacked alternately; as well as A plurality of vertical channel columns, a plurality of first isolation structures and a plurality of second isolation structures are formed in the stacked structure, wherein the plurality of vertical channel columns pass through the stacked structure and the laminate, a plurality of first isolation structures pass through the lower portion of the stacked structure, and a plurality of second isolation structures are respectively arranged above the plurality of first isolation structures and pass through the upper portion of the stacked structure, From a top view, each of the plurality of first isolation structures and the plurality of second isolation structures has two wide ends in the first direction.

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