Method of manufacturing super-junction device

Abstract

The application discloses a manufacturing method of a super-junction device, comprising: growing a first epitaxial layer; injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, the first selected region at least including a partial region of a terminal region close to a transition region; forming a trench gate; forming a well region and annealing; forming a second trench; growing a P-type doped second epitaxial layer in the second trench, removing the second epitaxial layer outside the second trench and flattening the surface of the second epitaxial layer in the second trench; completing a subsequent front process, including forming a protective ring oxide film covering an inner region of the transition region and a cutoff region of the terminal region, and setting a thermal process according to a requirement of controlling mutual diffusion of PN impurities of a super-junction structure; and completing a back process. The application can effectively control the mutual diffusion of the PN impurities of the super-junction structure, improve the reliability of products, improve the PN balance of the terminal region, improve the BVdss of the device, improve the consistency of the BVdss and improve the EAS capability.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a manufacturing method of a super junction (SJ) device. BACKGROUND

[0002] Compared with the existing conventional VDMOS, the existing super junction MOSFET has been widely used in various electronic power fields due to its excellent device characteristics. Due to the special N-pillar (N-type pillar) and P-pillar (P-type pillar) in the super junction MOSFET structure, which are mutually compensated, the high breakdown voltage can be achieved at a relatively high N-type epitaxial layer (NEPI) epitaxial concentration. Therefore, it has a low on-resistance and high breakdown voltage beyond the Si limit.

[0003] There are two main manufacturing processes for the existing super junction MOSFET device. One is to form mutually spaced P-type regions (P-type pillars) and N-type regions (N-type pillars) by multiple epitaxial deposition and lithography. One is to form P-type pillars by deep trench and trench filling on a thick N-epitaxial layer, thereby forming mutually spaced P-type regions and N-type regions. In the existing deep trench technology, in order to enable the planarization process of the deep trench P-type pillar to be well implemented, the P-type pillar forming process is usually placed before the polysilicon forming process of the gate structure, and sometimes the P-type well process is placed after the P-type pillar formation. In this way, the P-type pillar and the N-type pillar are formed after the trench P-type pillar, and then the gate oxide process and other high-temperature processes are performed, causing the mutual diffusion of the P-type pillar impurities and the N-type pillar impurities, which increases the source-drain on-resistance (Rdson) of the device and affects the chip performance.

[0004] After such setting, the vertical Vds is consumed by the PN pillar (P-type pillar and N-type pillar), and the surface electric field formed after the chip terminal region is consumed by the PN pillar. In the chip design and manufacturing process, it is generally difficult to adjust the relationship curve between the source-drain breakdown voltage (BVdss) of the horizontal terminal region and the P-N dose difference (the actual controllable is the concentration of P-type impurities) and the BVdss of the body in the active area (vertical electric field) to be consistent. Therefore, the loss of the key process window of the device affects the consistency of the chip BVdss. SUMMARY

[0005] The technical problem solved by the present application is to provide a super junction device manufacturing method, which can independently set the thermal processes of trench gate, well region and super junction structure, so that the quality of trench gate and well region is guaranteed, the PN impurity diffusion of super junction structure is effectively controlled, the smaller step super junction structure is realized, the on-resistance of super junction device is reduced, the process complexity and cost are not increased, the product reliability is improved, the PN balance of terminal region is increased, the source-drain breakdown voltage (BVdss) of terminal region is improved, the BVdss of the whole device is improved, the process window of P-type doping concentration of P-type column is expanded, and the BVdss consistency and single pulse avalanche energy (EAS) capability of the device are improved.

[0006] To solve the above technical problem, the super junction device manufacturing method provided by the present application comprises the following steps:

[0007] Growing a first epitaxial layer doped with N-type on the surface of a semiconductor substrate.

[0008] Using photolithography and ion implantation to implant first P-type impurities into the surface region of the first epitaxial layer in a first selected region, the super junction device comprising an active region, a transition region and a terminal region, the terminal region surrounding the active region, the transition region being between the active region and the terminal region, and the first selected region comprising at least a part of the terminal region close to the transition region.

[0009] Forming a plurality of trench gates in the first epitaxial layer of the active region, the trench gate comprising a gate oxide layer formed on the inner side surface of a gate trench and a gate conductive material layer filled in the gate trench, each trench gate being located in a corresponding N-type column, the gate conductive material layer outside the gate trench being removed, and the top surface of the gate conductive material layer in the gate trench being flat to ensure the formation process of a subsequent second trench, and the quality of the trench gate being adjusted by adjusting the thermal process in the formation process of the trench gate.

[0010] Forming a P-type doped well region in the active region and the transition region by photolithography and ion implantation and annealing the well region, each trench gate passing through the well region, and the well region being set to a desired position and repairing ion implantation damage by adjusting the thermal process of annealing the well region.

[0011] Performing photolithography and etching to form a plurality of second trenches in the first epitaxial layer, the first epitaxial layer between each second trench serving as an N-type column, and the second trenches being located in the active region, the transition region and a part of the terminal region close to the transition region.

[0012] Growth of a P-type doped second epitaxial layer in the second trench, removal of the second epitaxial layer outside the second trench and planarization of the surface of the second epitaxial layer in the second trench, the second epitaxial layer in the second trench forms a P-type pillar, the super-junction structure is formed by the alternating arrangement of the N-type pillars and the P-type pillars; outside the well region, the first P-type impurity is used to compensate the P-type impurity which is reduced due to thermal segregation in the surface region of the P-type pillar.

[0013] Subsequent front surface process after the super-junction structure is completed, in the subsequent front surface process, a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super-junction structure, so that the on-resistance of the super-junction device meets the requirement.

[0014] The subsequent front surface process includes: forming a first oxide film and performing patterned etching on the first oxide film to remove the first oxide film at the outermost periphery of the termination region, the remaining first oxide film covers the inner region of the transition region and the termination region and forms a guard ring oxide film.

[0015] Back surface process of the super-junction device is completed.

[0016] Further improvement is that the formation of the trench gate includes the following steps:

[0017] A first dielectric layer is formed on the top surface of the first epitaxial layer.

[0018] Photolithography defines the formation area of the gate trench.

[0019] The first dielectric layer and the first epitaxial layer in the formation area of the gate trench are etched in sequence to form the gate trench.

[0020] The gate oxide layer is formed by thermal oxidation process.

[0021] The gate conductive material layer is formed.

[0022] The first chemical mechanical polishing process is performed to planarize the gate conductive material layer, so as to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer in the gate trench.

[0023] Further improvement is that, before or after the first chemical mechanical polishing process, it further includes:

[0024] A rapid thermal oxidation or a rapid thermal annealing is performed.

[0025] Further improvement is that the maximum temperature of the annealing of the well region is above 1100℃, and the time is above 30 minutes.

[0026] Further improvement is that before the photoetching process of the second trench, it further includes forming a hard mask layer.

[0027] In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

[0028] Further improvement is that the hard mask layer includes a bottom silicon dioxide layer, an intermediate silicon nitride layer and a top silicon dioxide layer which are stacked in sequence.

[0029] After the etching of the second trench is completed, the top silicon dioxide layer and the intermediate silicon nitride layer outside the second trench are removed, and then the growth of the second epitaxial layer is performed.

[0030] Then, the second epitaxial layer is planarized by a second chemical mechanical polishing process to remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

[0031] Further improvement is that the subsequent front process includes:

[0032] Photoetching and ion implantation are performed to form an N-type heavily doped source region, and the source region is self-aligned with the side surface of the corresponding gate trench.

[0033] Annealing is performed to activate the source region, and the annealing of the source region is furnace tube annealing with a temperature below 950℃ or rapid thermal annealing; at the same time of forming the source region, an N-type heavily doped cutoff region is formed in the surface region of the first epitaxial layer outside the edge of the termination region.

[0034] An interlayer film is formed, and the interlayer film is stacked by an undoped silicon dioxide layer and a BPSG layer.

[0035] A contact hole opening is formed through the interlayer film.

[0036] A P-type heavily doped contact region is formed at the bottom of the contact hole opening.

[0037] A metal layer is filled in the contact hole opening to form a contact hole.

[0038] A front metal layer is formed, and the front metal layer is patterned and etched to form a source electrode and a gate electrode, and the source region and the well region are connected to the source electrode through the corresponding contact hole at the top, and the gate electrode is connected to the contact hole at the top of the gate conductive material layer of the trench gate lead-out end.

[0039] Further improvement is, the front side passivation protection process further includes:

[0040] A dielectric protection layer is formed, which is one or a combination of SiON layer, SiO2 layer, SiN layer and silicon oxide layer rich in Si.

[0041] A photolithography and dry etching are performed to pattern the dielectric protection layer to open the lead-out area of the source electrode and the lead-out area of the gate electrode.

[0042] Further improvement is, the front side passivation protection process further includes:

[0043] A polyimide layer is formed.

[0044] A photolithography and development are performed to pattern the polyimide layer to open the lead-out area of the source electrode and the lead-out area of the gate electrode.

[0045] The polyimide layer is baked.

[0046] Further improvement is, the metal layer forming the contact hole includes:

[0047] A barrier layer is formed on the inner side surface of the contact hole opening.

[0048] A tungsten layer is formed to fill in the contact hole opening.

[0049] The barrier layer and the tungsten layer also extend to the ILD surface outside the contact hole opening.

[0050] The front side metal layer is formed on the surface of the tungsten layer, when the front side metal layer is patterned, the tungsten layer and the barrier layer in the front side metal layer removal area are also removed, and the tungsten layer and the barrier layer in the front side metal layer retention area are also retained.

[0051] Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before the front side metal layer is formed, and then a second barrier layer and the front side metal layer are formed or the front side metal layer is directly formed.

[0052] Further improvement is, the setting of the thermal process corresponding to the subsequent front side process includes: when the time of the thermal process is more than 10 minutes, the corresponding temperature is limited to no more than 950℃.

[0053] Further improvement is, the second trench has a vertical side surface structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant.

[0054] Alternatively, the second trench has a top wide and bottom narrow side slope structure, the doping concentration of the second epitaxial layer is constant, and the doping concentration of the first epitaxial layer is set according to the side slope angle and depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance of adjacent N-type columns and corresponding P-type columns at each longitudinal position meets the requirements.

[0055] Alternatively, the second trench has a top wide and bottom narrow side slope structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side slope angle and depth of the second trench, and the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases from the bottom to the top of the second trench.

[0056] Further improvement is that after the first chemical mechanical polishing process, the top surface of the gate conductive material layer in the gate trench is located below the top surface of the first epitaxial layer outside the gate trench to facilitate the subsequent formation of the second trench.

[0057] Further improvement is that the inner side edge of the first selected region is located between the inner side edge and the outer side edge of the transition region.

[0058] The outer side edge of the first selected region is located inside the outer side edge of the outermost P-type column.

[0059] Alternatively, the outer side edge of the first selected region and the outer side edge of the outermost P-type column are flush.

[0060] Alternatively, the outer side edge of the first selected region is located outside the outer side edge of the outermost P-type column, and there is a first distance between the outer side edge of the first selected region and the outer side edge of the terminal region, and the first distance is greater than the maximum distance of punch-through between the outer side edge of the first selected region and the outer side edge of the terminal region.

[0061] Further improvement is that the first selected region is an opening region of a photoresist pattern formed by photolithography of the first P-type impurity.

[0062] Between the inner side edge and the outer side edge of the first selected region, the first selected region is fully opened.

[0063] Alternatively, between the inner side edge and the outer side edge of the first selected region, the subsequent formation region of the P-type column is covered, and the outer region of the P-type column is opened.

[0064] Further improvement is that the ion implantation of the first P-type impurity includes boron, and the implantation energy is 50keV-2MeV.

[0065] The implantation dose of the ion implantation of the first P-type impurity ensures that after the backside process is completed, the impurity concentration of the first P-type impurity is not higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

[0066] Further improvement is that after the ion implantation of the first P-type impurity is completed, it further includes:

[0067] The first P-type impurity is activated by annealing, and the maximum temperature of the annealing of the first P-type impurity is above 1100℃, and the minimum time is 60-180 minutes.

[0068] Further improvement is that the first oxide film is composed of a thermal oxide film formed by a thermal oxidation process.

[0069] Alternatively, the first oxide film is composed of an ALD oxide film formed by an ALD process and a thermal oxide film formed by a thermal oxidation process.

[0070] Alternatively, the first oxide film is composed of a thermal oxide film formed by a thermal oxidation process and a CVD oxide film formed by a CVD process.

[0071] Further improvement is that the temperature of the thermal oxidation process of the thermal oxide film constituting the first oxide film is 900-950℃.

[0072] Further improvement is that the step of the super-junction structure in the active region is a first step, the step in the transition region is a second step, and the step in the terminal region is a third step.

[0073] The first step, the second step and the third step are equal.

[0074] Alternatively, the second step is smaller than the first step, and the third step is smaller than the first step.

[0075] The present application specially sets the process flow of the super junction device, mainly places the formation process of the trench gate and the well region which requires higher heat process before the formation process of the super junction structure, sets the flatness of the gate conductive material layer in the gate trench including that the gate conductive material layer outside the gate trench is removed and the top surface of the gate conductive material layer in the gate trench is flat, which can ensure that the etching and filling process of the second trench of the super junction structure is well realized; since the formation process of the trench gate and the well region is placed before the formation process of the super junction structure, the formation process of the trench gate and the well region which requires higher heat process can avoid adverse effects on the super junction structure, so that the trench gate and the well region can adopt higher heat process according to their own needs, so that the quality of the trench gate and the well region is well guaranteed; meanwhile, the present application also controls the heat process after the super junction structure, which can ensure that the PN impurity diffusion of the super junction structure meets the requirements, so that the on-resistance of the super junction device meets the requirements. Since the PN impurity diffusion of the super junction structure can be well controlled, the step of the super junction structure can be further reduced, so that the on-resistance of the super junction device is further reduced and the performance of the super junction device is improved.

[0076] Although the present application places the formation process of the trench gate and the well region before the formation process of the super junction structure, the present application controls the flatness of the gate conductive material layer in the gate trench, which can ensure that the super junction structure can be formed under the condition of forming the trench gate and the well region, so the present application also has the advantages of not increasing the process complexity and cost.

[0077] Therefore, the present application can independently set the heat process of the trench gate, the heat process of the well region and the heat process of the super junction structure, so that the quality of the trench gate and the well region is guaranteed, the PN impurity diffusion of the super junction structure is effectively controlled, which is beneficial to realize the super junction structure with smaller step and reduce the on-resistance of the super junction device, and meanwhile, the process complexity and cost are not increased.

[0078] The present application also forms a protective ring oxide film in the transition region and the terminal region after the formation of the super junction structure, which can improve the reliability of the product.

[0079] The present invention also adds a first P-type impurity in the terminal region. Outside the well region, the first P-type impurity can compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation. This can increase the PN balance of the terminal region, that is, the charge matching between the P-type column and the N-type column, thereby improving the source-drain breakdown voltage (BVdss) of the terminal region and further improving the BVdss of the entire device. It can also expand the process window of the P-type doping concentration of the P-type column, improve the BVdss consistency of the device and enhance the EAS capability of the device. For example, by setting the first P-type impurity, the BVdss of the terminal region can be made greater than the BVdss of the active region, so The BVdss of the entire device is determined by the BVdss of the active area. The P-type doping concentration of the P-type column does not need to be used to adjust the difference in PN matching between the terminal area and the active area. The P-type doping concentration of the P-type column only needs to meet the BVdss requirements of the active area. Therefore, the process window of the P-type doping concentration of the P-type column is expanded, and the BVdss consistency of the device is increased. After the process window of the P-type doping concentration of the P-type column is expanded, the adjustment range of the P-type doping concentration of the P-type column will be increased, which is more conducive to improving the performance of the super junction device. For example, by increasing the P-type doping concentration of the P-type column, the EAS performance of the device can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0081] Figure 1 is a flow chart of a method for manufacturing a super junction device according to a first embodiment of the present invention;

[0082] Figures 2A-2M 1 is a schematic diagram of the device structure in each step of the method for manufacturing a super junction device according to the first embodiment of the present invention;

[0083] Figure 3 1 is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the second embodiment of the present invention;

[0084] Figure 4 1 is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the third embodiment of the present invention;

[0085] Figure 5 FIG4 is a schematic diagram of the device structure of a super junction device formed by the manufacturing method of a super junction device according to the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0086] like Figure 1 FIG. 1 is a flow chart of a method for manufacturing a super junction device according to a first embodiment of the present invention; FIG. Figures 2A to 2M , which is a schematic diagram of the device structure in each step of the method for manufacturing a super junction device according to the first embodiment of the present invention; the method for manufacturing a super junction device according to the first embodiment of the present invention includes the following steps:

[0087] Step S101: Figure 2A As shown, an N-type doped first epitaxial layer 102 is grown on the surface of a semiconductor substrate 101 .

[0088] In the first embodiment of the present invention, the material of the semiconductor substrate 101 includes silicon, the material of the first epitaxial layer 102 includes silicon, and the material of the subsequently formed second epitaxial layer 108 also includes silicon.

[0089] Step S102: Figure 2A As shown, the first P-type impurity 204 is implanted into the surface area of ​​the first epitaxial layer 102 of the first selected area 303 by photolithography and ion implantation. The super junction device includes an active area 201, a transition area 202 and a terminal area 203. The terminal area 203 surrounds the active area 201. The transition area 202 is located between the active area 201 and the terminal area 203. The first selected area 303 includes at least a portion of the terminal area 203 close to the transition area 202.

[0090] Figure 2A In the embodiment, the area of ​​the semiconductor substrate 101 is large. Figure 2A On the cross section, curve AA indicates that the active area 201, the transition area 202 and the terminal area 203 are continuously distributed. The structure of the area omitted by curve AA can be referred to Figure 2A The structure shown in FIG. Ion implantation is indicated by the arrow line marked 302 .

[0091] In the first embodiment of the present invention, the first selected region 303 is an open region of the photoresist pattern formed by photolithography of the first P-type impurity 204. Prior to photolithography, an implantation protection film 301 composed of a dielectric layer is formed. After photolithography, the implantation protection film 301 is etched using the photoresist pattern as a mask, thereby transferring the first selected region 303 to the open region of the implantation protection film 301.

[0092] Afterwards, ion implantation is performed using the implantation protection film 301 as a mask to implant the first P-type impurities 204 into the surface region of the first epitaxial layer 101 corresponding to the first selected region 303 . Figure 2A In the figure, the injected first P-type impurity 204 is represented by a hollow dot, indicating that the first P-type impurity 204 is injected into the surface area of ​​the corresponding first epitaxial layer 101. However, the net doping concentration of the surface area of ​​the first epitaxial layer 101 injected with the first P-type impurity 204 is still N-type doping.

[0093] In the first embodiment of the present invention, the first selected region 303 is completely open between the inner and outer edges of the first selected region 303. In other embodiments, the region between the inner and outer edges of the first selected region 303 may be covered with the area where the subsequent P-type pillars are to be formed, while the outer regions of the P-type pillars are open. In other words, the first P-type impurities 204 are implanted only into the surface regions of the N-type pillars or into the surface regions of the first epitaxial layer 101 extending outside the superjunction structure in the termination region.

[0094] In the first embodiment of the present invention, the outer edge of the first selected region 303 is flush with the outer edge of the outermost P-type pillar.

[0095] The inner edge of the first selected region 303 is located at the inner edge of the transition region 202 , that is, the entire transition region 202 is implanted with the first P-type impurities 204 .

[0096] In some embodiments, the implanted impurities of the ion implantation of the first P-type impurity 204 include boron, and the implantation energy is 50 keV to 2 MeV.

[0097] The ion implantation dose of the first P-type impurity 204 ensures that after the subsequent back-side process is completed, that is, after the first P-type impurity 204 has undergone all thermal processes, the impurity concentration of the first P-type impurity 204 is not higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

[0098] In some embodiments, after the ion implantation of the first P-type impurity 204 is completed, the method further includes:

[0099] The first P-type impurity 204 is annealed and activated. The maximum annealing temperature of the first P-type impurity 204 is above 1100° C., and the minimum annealing time is 60 minutes to 180 minutes. In some preferred examples, the annealing process parameters of the first P-type impurity 204 are: a temperature of 1100° C. and a time of 60 minutes to 180 minutes, or a temperature of 1175° C. and a time of 60 minutes to 180 minutes.

[0100] Step S103: Figure 2D As shown, a plurality of trench gates are formed in the first epitaxial layer 102 of the active region 201, and the trench gates include a gate oxide layer 104 formed on the inner surface of the gate trench 103 and a gate conductive material layer 105 filled in the gate trench 103; each trench gate is located in a subsequent corresponding N-type column; the gate conductive material layer 105 outside the gate trench 103 is removed, and the top surface of the gate conductive material layer 105 inside the gate trench 103 is flat to ensure the implementation of the subsequent second trench 107 formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process.

[0101] In the first embodiment of the present application, the steps of forming the trench gate include:

[0102] As shown in FIG. 3, a first dielectric layer 304 is formed on the top surface of the first epitaxial layer 102. The material of the first dielectric layer 304 is generally silicon oxide. Figure 2B

[0103] As shown in FIG. 4, photolithography defines the formation area of the gate trench 103. In this process, the photoresist pattern 305 is formed, and the opening area of the photoresist pattern 305 is the formation area of the gate trench 103. Figure 2B

[0104] As shown in FIG. 5, the first dielectric layer 304 and the first epitaxial layer 102 in the formation area of the gate trench 103 are etched in sequence to form the gate trench 103. The photoresist pattern 305 is removed before or after the etching of the first epitaxial layer 102 or is consumed during the etching process. Figure 2C

[0105] As shown in FIG. 6, a thermal oxidation process is used to form the gate oxide layer 104. The thermal oxidation process has a high-temperature thermal process. Since the thermal process corresponding to the thermal oxidation process is not affected by the subsequent formation of the super-junction structure, the parameters of the thermal oxidation process can be set according to the need to form a high-quality gate oxide layer 104, and finally the quality of the trench gate is guaranteed. Figure 2D

[0106] As shown in FIG. 7, the gate conductive material layer 105 is formed. Figure 2D

[0107] In the first embodiment of the present application, the material of the gate conductive material layer 105 includes polysilicon.

[0108] As shown in FIG. 8, a first chemical mechanical polishing process is performed to planarize the gate conductive material layer 105, so as to remove the gate conductive material layer 105 above the top surface of the first epitaxial layer 102 outside the gate trench 103 and to flatten the top surface of the gate conductive material layer 105 inside the gate trench 103. Figure 2D In the first embodiment of the present application, after the first chemical mechanical polishing process, the top surface of the gate conductive material layer 105 inside the gate trench 103 is located below the top surface of the first epitaxial layer 102 outside the gate trench 103, so as to facilitate the subsequent formation of the second trench 107 and the process of the subsequent second trench 107 to achieve its goal.

[0109]

[0110] In some embodiments, before or after the first chemical mechanical polishing process, a rapid thermal oxidation or a rapid thermal annealing is performed. ​​​​​​​

[0111] As shown in Figure 2D After the trench gate is formed, a surface of the first epitaxial layer 102 is formed with a protective film 205, which is formed by thinning the first dielectric layer 304 or by oxidizing after the first dielectric layer 304 is removed. The protective film 205 can be used as a protective layer for subsequent ion implantation.

[0112] Step S104, as shown in Figure 2E A P-type doped well region 106 is formed in the active region 201 and the transition region 202 by photolithography and ion implantation, and the well region 106 is annealed. Each trench gate passes through the well region 106. The annealing heat process of the well region 106 is adjusted to set the position of the well region 106 and repair ion implantation damage. The well region in the transition region 202 is separately indicated by a mark 106a.

[0113] In the first embodiment of the present application, the maximum temperature of the annealing of the well region 106 is above 1100℃, and the time is above 30 minutes.

[0114] Step S105, as shown in Figure 2F Photolithography and etching are performed to form a plurality of second trenches 107 in the first epitaxial layer 102. The first epitaxial layer 102 between each second trench 107 is used as an N-type column. The second trenches 107 are located in the active region 201, the transition region 202, and a part of the termination region 203 close to the transition region 202.

[0115] In the first embodiment of the present application, before the photolithography process of the second trench 107 is performed, a hard mask layer is further formed. The hard mask layer includes a bottom silicon dioxide layer, an intermediate silicon nitride layer, and a top silicon dioxide layer which are sequentially stacked.

[0116] In the etching process of the second trench 107, the hard mask layer is etched first, and then the first epitaxial layer 102 is etched.

[0117] After the etching of the second trench 107 is completed, the top silicon dioxide layer and the intermediate silicon nitride layer outside the second trench 107 are removed, and then the subsequent growth of the second epitaxial layer 108 is performed.

[0118] Step S106, as shown in Figure 2F A P-type doped second epitaxial layer 108 is grown in the second trench 107. The second epitaxial layer 108 outside the second trench 107 is removed entirely, and the surface of the second epitaxial layer 108 in the second trench 107 is made flat. The P-type column is composed of the second epitaxial layer 108 filled in the second trench 107. The super junction structure is formed by the N-type column and the P-type column arranged alternately. On the outside of the well region 106, the first P-type impurity 204 is used to compensate for the P-type impurity of the surface region of the P-type column which is reduced due to thermal segregation.

[0119] Then, the second epitaxial layer 108 is planarized by a second chemical mechanical polishing process to remove the second epitaxial layer 108 outside the second trench 107 and to make the surface of the second epitaxial layer 108 in the second trench 107 flat.

[0120] After the second chemical mechanical polishing process, the bottom silicon dioxide layer 206 with a partial thickness is retained on the surface of the first epitaxial layer 102.

[0121] In the first embodiment of the present application, the step of the super-junction structure in the active region 201 is the first step, the step in the transition region 202 is the second step, and the step in the terminal region 203 is the third step; the first step, the second step and the third step are equal.

[0122] In other embodiments, the second step can be smaller than the first step, the third step can be smaller than the first step, and the third step can be equal to the second step.

[0123] The N-type column and the P-type column of the super-junction structure achieve charge matching at each longitudinal position.

[0124] In some embodiments, the second trench 107 has a vertical side surface structure, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is constant.

[0125] In some embodiments, the second trench 107 has a top-wide and bottom-narrow side surface inclined structure, the doping concentration of the second epitaxial layer 108 is constant, and the doping concentration of the first epitaxial layer 102 is set according to the side surface inclination and depth of the second trench 107; from the bottom to the top of the second trench 107, the doping concentration of the first epitaxial layer 102 at the corresponding depth gradually increases, so that the charge balance of each adjacent N-type column and corresponding P-type column at each longitudinal position meets the requirements.

[0126] In some embodiments, the second trench 107 has a top-wide and bottom-narrow side surface inclined structure, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is set according to the side surface inclination and depth of the second trench 107; from the bottom to the top of the second trench 107, the doping concentration of the second epitaxial layer 108 at the corresponding depth gradually decreases.

[0127] In step S107, a subsequent front process after the super-junction structure is completed; in the subsequent front process, a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super-junction structure, so that the on-resistance of the super-junction device meets the requirements.

[0128] In the first embodiment of the present application, the setting of the thermal process corresponding to the subsequent front process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950℃.

[0129] The subsequent front side process includes:

[0130] As shown in FIG. 1 1, a first oxide film 110a is formed and the first oxide film 110a is patterned and etched to remove the first oxide film 110a at the outermost periphery of the termination region 203 and the active region 201, and the remaining first oxide film 110a covers the inner region of the termination region 203 and the transition region 202 and forms a guard ring oxide film. Figure 2G

[0131] In some embodiments, the first oxide film 110a is composed of a thermal oxide film formed by a thermal oxidation process, and the thickness of the thermal oxide film is 100-200 nm. The temperature of the thermal oxidation process for the thermal oxide film constituting the first oxide film 110a is 900-950 °C.

[0132] In some embodiments, the first oxide film 110a is composed of an ALD oxide film formed by an ALD process and a thermal oxide film formed by a thermal oxidation process, and the thickness of the ALD oxide film is 50-100 nm. The thickness of the thermal oxide film is 100-200 nm. The temperature of the thermal oxidation process for the thermal oxide film constituting the first oxide film 110a is 900-950 °C. The ALD oxide film can obtain a better interface between the first epitaxial layer 102 and the first oxide film 110a, and can improve the high temperature reverse bias stress (HTRB) reliability of the device.

[0133] In some embodiments, the first oxide film 110a is composed of a thermal oxide film formed by a thermal oxidation process and a CVD oxide film formed by a CVD process, and the thickness of the thermal oxide film is 100-200 nm. The thickness of the CVD oxide film is 50-100 nm. The temperature of the thermal oxidation process for the thermal oxide film constituting the first oxide film 110a is 900-950 °C.

[0134] In the first embodiment of the present application, the subsequent front side process includes:

[0135] As shown in FIG. 1 1, a first oxide film 110a is formed and the first oxide film 110a is patterned and etched to remove the first oxide film 110a at the outermost periphery of the termination region 203 and the active region 201, and the remaining first oxide film 110a covers the inner region of the termination region 203 and the transition region 202 and forms a guard ring oxide film. Figure 2H

[0136] In the first embodiment of the present application, the formation of the source region 109 also includes forming an N-type heavily doped cutoff region 109a in the surface region of the first epitaxial layer 102 at the outer edge of the termination region 203 at the same time.

[0137] The source region 109 is annealed and activated, and the annealing of the source region 109 is a furnace tube with a temperature of 950 °C or less or a rapid thermal annealing.​​

[0138] like Figure 2I As shown, an interlayer film 110 is formed, and the interlayer film 110 is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0139] like Figure 2I As shown, a contact hole opening 111 is formed through the interlayer film 110 . The contact hole opening 111 also penetrates into the first epitaxial layer 102 and passes through the surface source region 109 and contacts the well region 106 .

[0140] A contact hole opening 111 is also formed on the top of the stop region 109 a , and the bottom of the contact hole opening 111 also passes through the stop layer 109 a and contacts the first epitaxial layer 102 at the bottom.

[0141] like Figure 2J As shown, a P-type heavily doped contact region 111 a , namely, a contact hole implantation (CT IMP) is formed at the bottom of the contact hole opening 111 .

[0142] A metal layer is filled in the contact hole opening 111 to form a contact hole.

[0143] The metal layers that form the contact holes include:

[0144] like Figure 2J As shown, a barrier layer 112 is formed on the inner surface of the contact hole opening 111 .

[0145] In some embodiments, the material of the barrier layer 112 includes a Ti layer and a TiN layer stacked sequentially.

[0146] like Figure 2K As shown, a tungsten layer 113 is formed and filled in the contact hole opening 111 .

[0147] The barrier layer 112 and the tungsten layer 113 also extend onto the surface of the interlayer film 110 outside the contact hole opening 111 .

[0148] like Figure 2K As shown, a front metal layer 114 is formed. The front metal layer 114 is patterned and etched to form a source and a gate. The source region 109 and the well region 106 are connected to the source through corresponding contact holes at the top. The gate is connected to a contact hole at the top of the gate conductive material layer 105 at the trench gate lead. In some embodiments, the material of the front metal layer 114 includes AlCu.

[0149] In the first embodiment of the present invention, the front metal layer 114 is formed on the surface of the tungsten layer 113. When the front metal layer 114 is patterned, the tungsten layer 113 and the barrier layer 112 in the removal area of ​​the front metal layer 114 are also removed, and the tungsten layer 113 and the barrier layer 112 are also retained in the retention area of ​​the front metal layer 114.

[0150] In other embodiments, the barrier layer 112 and tungsten layer 113 outside the contact hole opening 111 can be removed before forming the front metal layer 114, and then a second barrier layer and the front metal layer 114 can be formed. In some embodiments, the second barrier layer comprises a Ti layer and a TiN layer stacked in sequence. Alternatively, the front metal layer 114 can be formed directly without forming the second barrier layer. Alternatively, after removing the tungsten layer 113 outside the contact hole opening 111, the barrier layer 112 is not removed, and the front metal layer 114 can be formed directly.

[0151] Figure 2K In the figure, the patterned front metal layer 114 includes: a source electrode corresponding to label 114a, a gate bus corresponding to label 114b, a transition region field plate corresponding to label 114c, multiple terminal region field plates corresponding to labels 114d1, 114d2 to 114dx, and a metal connected to the drain electrode corresponding to label 114e. The bottom of metal 114e is connected to the cut-off region 109a. The source electrode 114a and the gate bus 114b need to be separated, and the gate bus 114b and the transition region field plate 114c can be an integrated structure or separated structures. The terminal region field plates 114d1, 114d2 to 114dx are separated structures. The number of terminal region field plates 114d1, 114d2 to 114dx can be adjusted as needed, and the terminal region field plates 114d1, 114d2 to 114dx can also be omitted.

[0152] In the first embodiment of the present invention, a front passivation protection process is further performed, and the front passivation protection process further comprises:

[0153] like Figure 2L As shown, a dielectric protection layer 115 is formed; the dielectric protection layer 115 is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0154] Photolithography and dry etching are performed to pattern the dielectric protection layer 115 to open the lead-out region of the source and the lead-out region of the gate.

[0155] like Figure 2M As shown, the front passivation protection process also includes:

[0156] A polyimide layer 116 is formed.

[0157] The polyimide layer 116 is patterned by photoetching and developing to open the source and gate lead-out areas.

[0158] The polyimide layer 116 is baked.

[0159] In the first embodiment of the present application, the dielectric protective layer 115 and the polyimide layer 116 are simultaneously formed.

[0160] In some embodiments, only the dielectric protective layer 115 is formed, and the polyimide layer 116 is omitted.

[0161] In some embodiments, the dielectric protective layer 115 is omitted, and only the polyimide layer 116 is formed.

[0162] Step S108, as shown in Figure 2M the back surface process of the super-junction device is completed.

[0163] In the first embodiment of the present application, the back surface process includes:

[0164] The semiconductor substrate 101 is back thinned.

[0165] The N-type heavily doped drain region is formed. In the first embodiment of the present application, the semiconductor substrate 101 is N-type heavily doped, and the drain region is directly composed of the thinned semiconductor substrate 101, and thus the drain region does not need to be further activated. In other embodiments, the drain region is composed of a back surface injection region formed by back surface P-type heavy doping of the semiconductor substrate 101, and the drain region needs to be activated subsequently.

[0166] The back surface metal layer 117 is formed and composed of the drain electrode. In some embodiments, the back surface metal layer 117 includes TiNiAg.

[0167] The first embodiment of the present application specially sets the process flow of the super-junction device, mainly places the formation process of the trench gate and the well region 106 which requires higher thermal process before the formation process of the super-junction structure, sets the flatness of the gate conductive material layer 105 in the gate trench 103 to include that the gate conductive material layer 105 outside the gate trench 103 is removed and the top surface of the gate conductive material layer 105 in the gate trench 103 is flat, which can ensure that the etching and filling process of the second trench 107 of the super-junction structure is well implemented; since the formation process of the trench gate and the well region 106 is placed before the formation process of the super-junction structure, the formation process of the trench gate and the well region 106 which requires higher thermal process can avoid adversely affecting the super-junction structure, so that the trench gate and the well region 106 can use higher thermal process according to their own needs, so that the quality of the trench gate and the well region 106 is well guaranteed; at the same time, the first embodiment of the present application also controls the thermal process after the super-junction structure, which can ensure that the mutual diffusion of PN impurities of the super-junction structure meets the requirements, so that the on-resistance of the super-junction device meets the requirements. Since the mutual diffusion of PN impurities of the super-junction structure can be well controlled, the step of the super-junction structure can be further reduced, so that the on-resistance of the super-junction device can be further reduced and the performance of the super-junction device can be improved.

[0168] Although the first embodiment of the present application places the formation process of the trench gate and the well region 106 before the formation process of the super-junction structure, the first embodiment of the present application controls the flatness of the gate conductive material layer 105 in the gate trench 103, which can still facilitate the formation of the super-junction structure under the condition of forming the trench gate and the well region 106, so the first embodiment of the present application also has the advantages of not increasing the process complexity and cost.

[0169] Therefore, the first embodiment of the present application can independently set the thermal process of the trench gate, the thermal process of the well region 106 and the thermal process of the super-junction structure, so that the quality of the trench gate and the well region 106 is guaranteed, the mutual diffusion of PN impurities of the super-junction structure is effectively controlled, which is conducive to realizing a smaller step of the super-junction structure and reducing the on-resistance of the super-junction device, and the process complexity and cost are not increased.

[0170] The first embodiment of the present application also forms a protective ring oxide film in the transition region 202 and the terminal region 203 after the formation of the super-junction structure, which can improve the reliability of the product.

[0171] The first embodiment of the present invention further adds a first P-type impurity 204 to the terminal region 203. Outside the well region 106, the first P-type impurity 204 can compensate for the P-type impurity whose surface area of ​​the P-type column is reduced due to thermal segregation. This can increase the PN balance of the terminal region 203, that is, the charge matching between the P-type column and the N-type column, thereby increasing the source-drain breakdown voltage (BVdss) of the terminal region 203 and further increasing the BVdss of the entire device. It can also expand the process window of the P-type doping concentration of the P-type column, improve the BVdss consistency of the device and enhance the EAS capability of the device. For example, by setting the first P-type impurity 204, the BVdss of the terminal region 203 can be made greater than that of the active region 2 01, so the BVdss of the entire device is determined by the BVdss of the active area 201, and the P-type doping concentration of the P-type column does not need to be used to adjust the difference in PN matching between the terminal area 203 and the active area 201. The P-type doping concentration of the P-type column only needs to meet the BVdss requirement of the active area 201, so the process window of the P-type doping concentration of the P-type column is expanded, and the BVdss consistency of the device is increased; after the process window of the P-type doping concentration of the P-type column is expanded, the adjustment range of the P-type doping concentration of the P-type column will be increased, which is more conducive to improving the performance of the super junction device. For example, by increasing the P-type doping concentration of the P-type column, the EAS performance of the device can be further improved.

[0172] like Figure 3 FIG. 1 is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the second embodiment of the present invention. The difference from the method for manufacturing a super junction device according to the first embodiment of the present invention is that in the method for manufacturing a super junction device according to the second embodiment of the present invention:

[0173] The outer edge of the first selected region 303 is located outside the outer edge of the outermost P-type pillar, and a first distance exists between the outer edge of the first selected region 303 and the outer edge of the termination region 203. The first distance is greater than the maximum distance between the outer edge of the first selected region 303 and the outer edge of the termination region 203 at which punch-through occurs. In this application, the outer edge of the termination region 203 refers to the inner edge of the cut-off region 109a; the maximum distance between the outer edge of the first selected region 303 and the outer edge of the termination region 203 at which punch-through occurs refers to the maximum distance less than or equal to which the first P-type impurity 204 will punch-through into the N+-doped cut-off region 109a or the P+-doped contact region 207 corresponding to the bottom of the cut-off region 109a. In some embodiments, the first distance is greater than 10 microns.

[0174] like Figure 4 FIG. 1 is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the third embodiment of the present invention. The difference from the method for manufacturing a super junction device according to the first embodiment of the present invention is that in the method for manufacturing a super junction device according to the third embodiment of the present invention:

[0175] The outer edge of the first selected region 303 is located inside the outer edge of the outermost P-type pillar.

[0176] like Figure 5 , which is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the fourth embodiment of the present invention; the difference from the method for manufacturing a super junction device according to the second embodiment of the present invention is that in the method for manufacturing a super junction device according to the fourth embodiment of the present invention:

[0177] The inner edge of the first selected region 303 is located at the outer edge of the transition region 202 , that is, the first P-type impurity 204 is not implanted into the entire transition region 202 .

[0178] In other embodiments, the inner edge of the first selected region 303 is located in other regions between the inner edge and the outer edge of the transition region 202 , that is, the first P-type impurities 204 are formed only in a portion of the transition region 202 .

[0179] In the first embodiment of the present invention, taking the N-type MOSFET as an example, the thermal process after the formation of the P-type column can be greatly reduced, thereby further reducing the on-resistance of the device. At the same time, after the P-type column is formed, by adding a thermal oxidation film or a combination of a thermal oxidation film and an ALD film, or a combination of these films and a CVD film in the transition region and the region that bears the lateral voltage, i.e., the terminal region, the reliability of the product is improved. The first embodiment of the present invention also adds a P-type ion implantation region in the terminal region to expand the process window of BVdss and P-type impurity concentration. By setting the terminal injection, i.e., the injection of the first P-type impurity 204, the absolute value of the terminal BVdss can also be adjusted. For example, when the BVdss of the terminal is higher than the BVdss of the active region, the BVdss of the device can be improved, the consistency of the device can be improved, and the EAS capability can be enhanced.

[0180] The following takes a 600V trench gate super junction N-type MOSFET as an example to further illustrate the first embodiment of the present invention in combination with corresponding parameters:

[0181] In step S101 , the semiconductor substrate 101 is a low-resistivity N-type substrate. For example, the resistivity of the semiconductor substrate 101 is less than 0.003 ohm.cm.

[0182] The thickness of the first epitaxial layer 102 is between 45 and 50 microns. The resistivity design of the first epitaxial layer 102 is related to the stepping of the subsequent P-type and N-type pillars, and can be simulated and designed using computer-aided software. For example, the stepping of the PN pillar is set to 5 microns, and the resistivity is set to 0.5 ohm.cm.

[0183] In step S102, the ion implantation of the protective film 301 is performed

[0184] The ion implantation of the first P-type impurity 204 is performed with B as the implanted impurity, an implantation energy of 50 keV to 2 MeV, and a dose designed according to the impurity concentration of the first epitaxial layer 102 of the device, generally designed so that the highest impurity concentration of B after all the subsequent processes does not exceed 20% of the N-type impurity concentration. In some examples, the process parameters of the ion implantation of the first P-type impurity 204 are B 600 keV 8E11 atoms / cm -2 , B 60 keV 8E11 atoms / cm -2 , B 60 keV 8E11 atoms / cm -2 . Subsequently, a high-temperature annealing process is performed, for example, 1100°C for 60-180 min or 1175°C for 60-180 min. 1100°C for 60-180 min means that the annealing temperature is 1100°C and the time is 60 min to 180 min.

[0185] In step S103, the thickness of the first dielectric layer 201 is 0.5-2 microns.

[0186] The width and depth of the gate trench 103 can be designed according to the performance of the device, for example, the width of the gate trench 103 is designed to be 0.8-1.5 microns and the depth is designed to be 2.5-4 microns. No gate trench 103 is formed in the transition region 202 and the termination region 203. Subsequently, the first dielectric layer 304 as a hard mask is completely removed, generally by wet etching.

[0187] The thickness of the gate oxide layer 104 is designed to be 500 angstroms to 1500 angstroms;

[0188] The resistivity of the polysilicon of the gate conductive material layer 105 is generally designed to be about 10 ohm.cm to 30 ohm.cm. Before or after the planarization of the polysilicon of the gate conductive material layer 105, a high-temperature RTO or a high-temperature RTA can be performed, which can improve the leakage between the gate and the drain of the product.

[0189] In step S104, the ion implantation of the well region 106 is not performed in the active region 201, the transition region 202, and the termination region 203. The ion implantation of the well region 106 is generally performed with B as the implanted impurity, an implantation energy of 100 keV, and an implantation dose designed according to the threshold voltage of the device, for example, an implantation dose of 1E13 atoms / cm 2The ion implantation of the well region 106 can also be performed by using two different energy B implantations, so that different P-type wells, i.e. the well region 106, can be formed to adjust the performance parameters of the device, including threshold voltage and EAS, etc. After the ion implantation of the well region 106, a high temperature annealing can be performed, for example, 1100C for 30 minutes or higher temperature and longer time, so that the P-type well can be pushed to the set position and some damages caused by the ion implantation can be repaired.

[0190] Before the B implantation of the well region 106, the surface of the silicon, i.e. the semiconductor substrate 101 and the first epitaxial layer 102, is thinned to about 200 angstroms to serve as the protective film 205 during the ion implantation. The oxide film, i.e. the protective film 205, can be the film left after the previous polysilicon CMP, i.e. the first chemical mechanical polishing, and can be obtained by dry or wet etching. It can also be a thermal oxide film or a CVD film generated after the film after the polysilicon CMP is removed, and the latter can increase the consistency of the ion implantation protective film and improve the consistency of the device parameters, especially the threshold voltage.

[0191] In step S105, the thickness of the bottom silicon dioxide layer is 200 angstroms. The thickness of the middle silicon nitride layer is 200 angstroms. The thickness of the top silicon dioxide layer is 2-5 microns.

[0192] The width of the deep trench, i.e. the second trench 107, is 2.5 microns, the size of the N region between adjacent trenches, i.e. the distance between the second trenches 107, is 2.5 microns, and the depth of the second trench 107 is 40-42 microns, which can be set according to the requirements of the BVdss of the device.

[0193] After the etching of the second trench 107, the hard mask top SIO2 and SIN, i.e. the top silicon dioxide layer and the middle silicon nitride layer, are removed, and the bottom SIO2, i.e. the bottom silicon dioxide layer, is kept as a protective layer for the Si surface. Then, the second trench 107 is completely filled by P-type epitaxial deposition, and then the surface Si is completely removed by chemical mechanical polishing.

[0194] In this configuration, adjacent P-type and N-type pillars can be configured with the same stepping, P-type pillar width, and N-type pillar width in the active region 201, transition region 202, and terminal region 203. For example, the stepping can be set to 5μm, with a P-type pillar top width of 2.5μm and an N-type pillar top width of 2.5μm. Alternatively, the stepping in the transition region 202 and terminal region 203 can be different from that in the active region. Typically, the stepping in the transition region 202 and terminal region 203 is smaller than that in the active region. For example, the stepping in the transition region 202 and terminal region 203 can be set to 4.8μm, with a P-type pillar top width of 2.5μm and an N-type pillar top width of 2.3μm. The outermost P-type pillars in the terminal region 203 are located a certain distance from the outermost periphery of the chip, for example, 15-30 microns.

[0195] In step S107, when forming the first oxide film 110a, a thermal oxidation is performed on the silicon wafer, i.e., the semiconductor substrate 101 on which the first epitaxial layer 102 is formed, to form a thermal oxide film of 2000-8000 angstroms. The thermal oxidation temperature can be set at 900-950°C. In order to obtain a better SI-SIO2 interface and improve the high temperature reverse bias stress (HTRB) reliability of the device, a very thin oxide film of, for example, 30-100 angstroms can be deposited on the silicon wafer using an atomic layer deposition (ALD) device, and then a 2000-8000 angstrom oxide film is formed by thermal oxidation. If the thermal oxide film is set at 2000 angstroms, a CVD oxide film (undoped) with a thickness of 2000-6000 angstroms can be deposited. The first oxide film 110a in the active area 201 is then removed by photolithography and wet etching, and the first oxide film 110a in the outermost part (cut-off area) of the terminal area 203 is also removed. In the other parts of the transition area 202 and the terminal area 203, the first oxide film 110a is retained, and the total thickness of the retained first oxide film 110a is 4000-8000 angstroms.

[0196] In step S107, Figure 2H As shown, a 100-300 angstrom oxide film is deposited on the surface of the active area 201 and the outermost portion of the chip as a protective film for subsequent N+ implantation. Then, photolithography and ion implantation are performed to form the N+ source region 109. Here, N+ can be implanted with phosphorus or arsenic (As), for example, using As 60keV1~5E15 atoms / cm 2 , As 60Kev 1~5E15 atoms / cm 2 Indicates that the implanted impurity is As, the implantation energy is 60keV, and the implantation dose is 1 atom / cm 2 ~5E15 atoms / cm 2 After the ion implantation of the source region 109 , an activation process may be performed at a temperature below 950° C., for example, 900° C. for 30 min. RTA activation may also be used.

[0197] In the step of forming the interlayer film 110, a 2000 angstrom undoped silicon dioxide layer is first deposited, and then a 8000-10000 angstrom BPSG layer is deposited.

[0198] In the step of forming the contact hole, the contact hole opening 111 can be deep into the Si, i.e. the Si of the first epitaxial layer 102 to

[0199] The bottom of the contact hole opening 111 can form a P-type region, i.e. the contact region 207, by B or BF2 implantation. For example, when the contact region 207 is formed by B implantation, the implantation energy can be 30-60 Kev, and the implantation dose can be 5E14-1E15 / cm 2 , which better guarantees the ohmic contact between the metal in the subsequent contact hole opening 111 and the Si at the bottom of the contact hole opening 111, and reduces the contact resistance.

[0200] In the step of forming the barrier layer 112, the thickness of the Ti layer is The thickness of the TiN layer is

[0201] In the step of forming the tungsten layer 113, the process of filling the contact hole opening 111 with metal tungsten is to grow along the sidewall of the contact hole opening 111 and contact the center region of the contact hole opening 111. The contacted part can have some gaps or no gaps. The tungsten can completely fill the contact hole opening 111, or can not completely fill the contact hole opening 111, as long as the subsequent metal can well cover the hole.

[0202] In the step of forming the front metal layer 114, the deposition temperature of AlCu can be set to 250-450C, and the thickness can be set to 2-6 microns. Then, the metal Al-Cu, i.e. AlCu, the W, i.e. the tungsten layer 113, and the barrier layer 112 film below are all removed by metal lithography and dry etching.

[0203] In addition, as an alternative embodiment, the following can be used as an alternative:

[0204] Before forming the front metal layer 114, the W on the surface of the silicon is completely removed by dry etching, and then the barrier layer 112 film below the W is also completely etched, and then Ti / TiN / ALcu, i.e. the second barrier layer 112a and the front metal layer 114, are deposited. The thickness of the film can be set as follows, 5 microns, or other settings, wherein 5 microns represents the thickness of the Ti layer The thickness of the TiN layer is The thickness of the AlCu is 5 microns. Alternatively, after the W on the surface is completely etched, only the AlCu is deposited, for example, 5 microns thick AlCu is deposited. After the AlCu deposition is completed, the photolithography and dry etching of the metal are performed.

[0205] The front side passivation protection process further includes:

[0206] A dielectric protection layer of 1-2 microns can be deposited, which can be SiON, SiO2, SiN, silicon oxide film rich in Si, or a combination thereof. Then, the electrode lead-out area of the gate is opened, the electrode lead-out area of the source is opened, and other areas including the terminal area subjected to lateral voltage are protected by photolithography and dry etching, so as to improve the reliability of the product.

[0207] The front side passivation protection process further includes:

[0208] A polyimide film can be deposited on the surface of the silicon wafer, which can be formed on the surface of the dielectric protection layer or the dielectric protection layer is omitted. Then, the electrode lead-out area of the gate is opened, the electrode lead-out area of the source is opened, and other areas including the terminal area subjected to lateral voltage are protected by photolithography and development, so as to improve the reliability of the product. After the photolithography and development are completed, baking at 300-400°C (30-90 min) can be performed, and the thickness of the polyimide after baking is 4-15 microns.

[0209] In step S108, the entire thickness of the silicon wafer, i.e., the entire thickness of the semiconductor substrate 101 and the first epitaxial layer 102, is thinned to 60-200 microns.

[0210] The thickness of the TiNiAg of the back side metal layer 115 can be The Ti layer The Ni layer The Ag layer

[0211] The above process can realize the manufacture of a super-junction MOSFET and form the division of the active region, the transition region, and the terminal region subjected to lateral voltage. The electrode of the source region is led out through the front side metal layer 114 in Figure 2M The gate is led out by connecting the contact hole at the end of the trench gate in Figure 2M The drain is the back side metal layer 115.

[0212] In the first embodiment of the present application, the following further optimization can be performed:

[0213] In step S101, the first epitaxial layer 102 can be set according to the angle and depth of the trench, i.e. the second trench 107, in step S104. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e. consistent from top to bottom. If the trench is an inclined trench with a large top and a small bottom, the N-epitaxy, i.e. the first epitaxial layer 102, can be set to have a high concentration at the top and a low concentration at the bottom, with a linear change in the middle, so that at each position perpendicular to the trench, the PN balance can be achieved when the impurity concentration of the P-type column is a single concentration, thus better balancing the source-drain breakdown voltage (BVdss) and Rdson of the device.

[0214] In step S106, the trench can be filled with the second epitaxial layer 108. The setting of the first epitaxial layer 102 and the angle of the trench can be combined. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e. consistent from top to bottom, and the impurity concentration of the P-type column can also be constant. If the resistivity of the first epitaxial layer 102 is set to be constant and the trench is an inclined trench with a large top and a small bottom, the P-type epitaxial deposition process can be set to have a high P-type impurity concentration first, and then gradually reduce the deposition concentration. The specific process conditions can be determined by evaluating the BVdss of the device and the window relationship of the P-type impurity setting, with the goal of expanding the process window of the P-type epitaxial process.

[0215] In the first embodiment of the present application, in order to reduce the mutual diffusion of PN impurities after the formation of the P-type column, the temperature during the heat process after the formation of the P-type column is limited to not exceed 950C for more than 10 minutes.

[0216] Compared with the prior art, the first embodiment of the present application adopts a new process flow without increasing the process complexity and cost. Before the trench of the P-type column, i.e. the second trench 107, is formed, the high-heat process of the gate oxide process, i.e. the formation process of the gate oxide layer 104, and the P-type well formation push well process are all placed before the P-type column trench. After the P-type column is formed, the heat process is set to be below 950C, or only the RTA and other special short-time activation processes are used. At the same time, by adding a thermal oxide film or a combination of a thermal oxide film and an ALD film, or a combination of these films and a cvd film after the P-type column is formed in the transition area and the area bearing the lateral voltage, the reliability of the product is improved. The first embodiment of the present application also adds a P-type ion implantation area in the terminal area, which is used to expand the process window of BVdss and the P-type impurity concentration. By setting the terminal implantation, the absolute value of the terminal BVdss can also be adjusted. For example, when the BVdss of the terminal is higher than that of the active area, the BVdss of the device can be improved, the consistency of the device can be improved, and the EAS capability can be improved.

[0217] The above has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as the protection scope of the present application.

Claims

1. A method for manufacturing a super junction device, characterized in that: The steps include: Growing an N-type doped first epitaxial layer on the surface of the semiconductor substrate; Implanting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region using photolithography and ion implantation, wherein the superjunction device includes an active region, a transition region, and a termination region, wherein the termination region surrounds the active region, the transition region is located between the active region and the termination region, and the first selected region includes at least a portion of the termination region adjacent to the transition region; forming a plurality of trench gates in the first epitaxial layer of the active region, wherein the trench gates include a gate oxide layer formed on an inner surface of a gate trench and a gate conductive material layer filled in the gate trench; Each of the trench gates is located in a subsequent corresponding N-type column; The gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer inside the gate trench is flat, so as to ensure the implementation of the subsequent second trench formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process; forming a P-type doped well region in the active region and the transition region by photolithography and ion implantation, and annealing the well region, wherein each trench gate passes through the well region, and adjusting the thermal process of the annealing of the well region so as to push the well region to a set position and repair ion implantation damage; Performing photolithography and etching to form a plurality of second trenches in the first epitaxial layer, wherein the first epitaxial layer between the second trenches serves as an N-type pillar; The second trench is located in a portion of the active region, the transition region, and the terminal region close to the transition region; A P-type doped second epitaxial layer is grown in the second trench, the second epitaxial layer outside the second trench is completely removed, and the surface of the second epitaxial layer in the second trench is flattened, the second epitaxial layer filled in the second trench forms a P-type pillar, and the N-type pillars and the P-type pillars are alternately arranged to form a superjunction structure; outside the well region, the first P-type impurity is used to compensate for the P-type impurity whose surface area of ​​the P-type pillars is reduced due to thermal segregation; After completing the super junction structure, a subsequent front-side process is performed, wherein a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities in the super junction structure so that the on-resistance of the super junction device meets the requirement; The subsequent front surface process includes: forming a first oxide film and patterning and etching the first oxide film to remove the first oxide film in the active area and the outermost cut-off area of ​​the terminal area, and the remaining first oxide film covers the inner area of ​​the transition area and the cut-off area of ​​the terminal area to form a protective epoxy film; the formation process of the first oxide film includes a thermal oxidation process; Complete the backside process of super junction devices.

2. The method for manufacturing a super junction device according to claim 1, wherein: The steps of forming the trench gate include: forming a first dielectric layer on a top surface of the first epitaxial layer; Photolithography defines a formation area of ​​the gate trench; Sequentially etching the first dielectric layer and the first epitaxial layer in the gate trench formation region to form the gate trench; forming the gate oxide layer by a thermal oxidation process; forming the gate conductive material layer; A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

3. The method for manufacturing a super junction device according to claim 2, wherein: Before or after the first chemical mechanical polishing process, the method further includes: Perform a rapid thermal oxidation or a rapid thermal annealing.

4. The method for manufacturing a super junction device according to claim 1, wherein: The maximum annealing temperature of the well region is above 1100° C., and the annealing time is above 30 minutes.

5. The method for manufacturing a super junction device according to claim 1, wherein: Before performing the photolithography process of the second trench, the method further includes: forming a hard mask layer; In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

6. The method for manufacturing a super junction device according to claim 5, wherein: The hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence; After the etching of the second trench is completed, removing the top silicon dioxide layer and the middle silicon nitride layer outside the second trench, and then growing the second epitaxial layer; Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

7. The method for manufacturing a super junction device according to claim 1, wherein: The subsequent front surface process includes: Performing photolithography and ion implantation to form an N-type heavily doped source region, wherein the source region and the corresponding side of the gate trench are self-aligned; Annealing the source region for activation, wherein the annealing of the source region is performed in a furnace at a temperature below 950° C. or by rapid thermal annealing; while forming the source region, an N-type heavily doped cutoff region is formed in the surface region of the first epitaxial layer at the outer edge of the terminal region; forming an interlayer film, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer; forming a contact hole opening through the interlayer film; forming a P-type heavily doped contact region at the bottom of the contact hole opening; Filling a metal layer in the contact hole opening to form a contact hole; A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

8. The method for manufacturing a super junction device according to claim 7, wherein: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a dielectric protection layer; the dielectric protection layer is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer, and a Si-rich silicon oxide layer; Photolithography and dry etching are performed to pattern the dielectric protection layer to open the lead-out region of the source and the lead-out region of the gate.

9. The method for manufacturing a super junction device according to claim 7 or 8, wherein: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a polyimide layer; Performing photolithography and development to pattern the polyimide layer to open the lead-out region of the source electrode and the lead-out region of the gate electrode; The polyimide layer is baked.

10. The method for manufacturing a super junction device according to claim 7, wherein: The metal layer forming the contact hole includes: forming a barrier layer, wherein the barrier layer is formed on the inner surface of the contact hole opening; forming a tungsten layer, wherein the tungsten layer is filled in the contact hole opening; The barrier layer and the tungsten layer further extend onto the surface of the interlayer film outside the contact hole opening; The front metal layer is formed on the surface of the tungsten layer. When the front metal layer is patterned, the tungsten layer and the barrier layer are also removed in the front metal layer removal area, and the tungsten layer and the barrier layer are also retained in the front metal layer retention area. Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before forming the front metal layer, and then a second barrier layer and the front metal layer are formed, or the front metal layer is directly formed.

11. The method for manufacturing a super junction device according to claim 1, wherein: The setting of the thermal process corresponding to the subsequent front surface process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

12. The method for manufacturing a super junction device according to claim 1, wherein: The second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer is constant, and the doping concentration of the first epitaxial layer is set according to the side inclination angle and the depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance between each adjacent N-type pillar and the corresponding P-type pillar at each longitudinal position meets the requirement; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench. From the bottom to the top of the second trench, the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases.

13. The method for manufacturing a super junction device according to claim 2, wherein: After the first chemical mechanical polishing process, the top surface of the gate conductive material layer in the gate trench is located 500Å to 1000Å below the top surface of the first epitaxial layer outside the gate trench to facilitate the subsequent formation of the second trench.

14. The method for manufacturing a super junction device according to claim 1, wherein: The inner edge of the first selected area is located between the inner edge and the outer edge of the transition zone; The outer edge of the first selected area is located inside the outer edge of the outermost P-type column; Alternatively, the outer edge of the first selected area is flush with the outer edge of the outermost P-type column; Alternatively, the outer edge of the first selected area is located outside the outer edge of the outermost P-type column, and there is a first distance between the outer edge of the first selected area and the outer edge of the terminal area, and the first distance is greater than the maximum distance at which penetration occurs between the outer edge of the first selected area and the outer edge of the terminal area.

15. The method for manufacturing a super junction device according to claim 14, wherein: The first selected area is an open area of ​​the photoresist pattern formed by photolithography of the first P-type impurity; Between the inner edge and the outer edge of the first selected area, the first selected area is completely open; Alternatively, between the inner edge and the outer edge of the first selected region, the subsequent formation region of the P-type column is covered, and the outer region of the P-type column is open.

16. The method for manufacturing a super junction device according to claim 1, wherein: The implanted impurities of the first P-type impurity ion implantation include boron, and the implantation energy is 50keV to 2MeV; The implantation dose of the first P-type impurity ion implantation ensures that after the back-side process is completed, the impurity concentration of the first P-type impurity is no higher than 20% of the N-type impurity concentration of the N-type region outside the P-type column, and the net doping of the N-type region outside the P-type column remains N-type doping.

17. The method for manufacturing a super junction device according to claim 16, wherein: After the ion implantation of the first P-type impurity is completed, the method further includes: The first P-type impurity is annealed and activated, wherein the maximum annealing temperature of the first P-type impurity is greater than 1100° C., and the minimum annealing time is 60 minutes to 180 minutes.

18. The method for manufacturing a super junction device according to claim 1 or 11, wherein: The first oxide film is composed of a thermal oxide film formed by a thermal oxidation process; Alternatively, the first oxide film is formed by stacking an ALD oxide film formed by an ALD process and a thermal oxide film formed by a thermal oxidation process; Alternatively, the first oxide film is formed by stacking a thermal oxide film formed by a thermal oxidation process and a CVD oxide film formed by a CVD process.

19. The method for manufacturing a super junction device according to claim 18, wherein: The temperature of the thermal oxidation process of the thermal oxidation film constituting the first oxide film is 900° C. to 950° C.

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