Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device, including: providing a substrate; forming a well region of a first type in the substrate, the well region including source regions and drain regions that are spaced apart; forming a trench in the well region based on a target mask, the trench being located between the source regions and the drain regions; injecting ions of a second type into a target sidewall and a part of the bottom of the trench to form a target doping region of the second type having an "L"-shaped cross section; the target sidewall being adjacent to the drain region; after forming a dielectric layer in the trench, forming a drift region of the second type in the well region; forming a gate structure on the substrate between the target doping region and the source region, forming a source doping region in the source region, and forming a drain doping region in the drain region. It can at least improve the reliability problem of HCI of high-voltage devices and the performance of SOA of high-voltage devices.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit manufacturing technologies, and particularly to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technologies, high-voltage devices are increasingly used, such as radio frequency power amplifiers in wireless communication systems, power management, and industrial microwave applications, etc. High-voltage devices, such as LDMOS (Laterally Diffused Metal-Oxide Semiconductor), IGBT (Insulated Gate Bipolar Transistor), high-voltage thyristor (SCR), etc., are widely used in wireless communication base stations, industrial heating, or radar and other fields due to their characteristics such as high power handling capacity, high-frequency performance, low on-state loss, and good linearity.

[0003] In related technologies, since the hot carrier effect of high-voltage devices is closely related to the doping concentration of the drift region. When the doping concentration increases, the impact ionization under the gate enhances; while when the doping concentration is relatively small, the impact ionization near the trench edge under the drain enhances.

[0004] However, in current high-voltage devices, when the doping concentration of the drift region is relatively high, there will be hot carrier injection (HCI) reliability problems; while when the doping of the drift region is relatively low, there will be problems with insufficient safe operating area (SOA), and it is difficult to balance the HCI and SOA of high-voltage devices. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method for manufacturing a semiconductor device and a semiconductor device, which can at least balance the improvement of the HCI reliability of high-voltage devices and the SOA performance of high-voltage devices.

[0006] To achieve the above object and other objects, in a first aspect, the present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate; forming a well region of a first type in the substrate, the well region including a source region and a drain region distributed at intervals; forming a trench in the well region based on a target mask, the trench being located between the source region and the drain region; injecting ions of a second type into a target sidewall and a part of the bottom of the trench to form a target doped region of the second type with an "L"-shaped cross-section; the target sidewall being adjacent to the drain region; after forming a dielectric layer in the trench, forming a drift region of the second type in the well region; forming a gate structure on the substrate between the target doped region and the source region, forming a source doped region in the source region, and forming a drain doped region in the drain region.

[0007] In the method for manufacturing a semiconductor device in the above embodiments, a second-type target doping region having an ion concentration different from that of the drift region and an "L"-shaped longitudinal cross-section is formed in the second-type drift region. The doping concentration of the drift region below the gate structure is relatively low, reducing the hot carrier impact ionization rate below the gate structure. The doping concentration of the target doping region near the sidewall and bottom surface of the trench below the drain doping region is relatively high, reducing the hot carrier impact ionization rate of the drain doping region in the target doping region. Therefore, the embodiments of the present disclosure can at least balance the improvement of the HCI reliability of high-voltage devices and the SOA performance of high-voltage devices.

[0008] In one embodiment, the doping concentration of the target doping region is: to 。

[0009] In one embodiment, the doping concentration of the drift region is: to 。

[0010] In the method for manufacturing a semiconductor device in the above embodiments, by restricting the doping concentration of the target doping region and the doping concentration of the drift region, the hot carrier injection (HCI) reliability of high-voltage devices and the SOA performance of high-voltage devices are further improved.

[0011] In one embodiment, the top surface of the target doping region is not lower than the bottom surface of the drain doping region; the bottom surface of the target doping region is higher than the bottom surface of the drift region.

[0012] In the method for manufacturing a semiconductor device in the above embodiments, by restricting the positions of the target doping region and the drain doping region, the target doping region is formed below the drain doping region, ensuring that the ion concentration below the drain doping region is higher than that of the drift region, reducing the hot carrier impact ionization rate of the drain doping region in the target doping region, and thus improving the SOA performance.

[0013] In one embodiment, a partial dielectric layer is included between the gate structure and the drain doping region.

[0014] In the method for manufacturing a semiconductor device in the above embodiments, by forming a partial dielectric layer between the gate structure and the drain doping region, the channel layer below the gate structure is connected to the drain doping region via the drift region and the target doping region below the dielectric layer, improving the SOA performance while avoiding the generation of current leakage channels.

[0015] In one embodiment, the doping concentration of the well region is: to 。

[0016] In one embodiment, the doping concentration of the drain doping region is: to 。

[0017] In the method for manufacturing a semiconductor device in the above embodiments, by restricting the concentrations of the well region and the drain doping region, the hot carrier injection (HCI) reliability of the high-voltage device is further ensured, and the performance of the safe operating area (SOA) is improved.

[0018] In one embodiment, the longitudinal cross-section of the trench is an "inverted trapezoid", which can reduce the difficulty of trench etching and the process cost.

[0019] In one embodiment, the inner angle of the "L"-shaped target doping region is an obtuse angle, which is beneficial to form a rounded target doping region, avoiding the formation of a sharp acute angle at the corner of the target doping region, and thus preventing the occurrence of tip discharge or leakage current.

[0020] In one embodiment, after forming the gate structure, a source doping region is formed in the source region, and a drain doping region is formed in the drain region.

[0021] In the method for manufacturing a semiconductor device in the above embodiments, by forming the drain doping region and the source doping region in the drain region and the source region, the basic structure of the high-voltage device is formed, and by forming the drain doping region in the drain region that contacts the target doping region, the performance of the safe operating area (SOA) is improved.

[0022] In one embodiment, the dielectric layer fills the trench and covers the top surface of the substrate; forming the drift region includes: forming a patterned photoresist layer on the top surface of the dielectric layer based on a target mask; performing a second-type ion implantation into the well region based on the patterned photoresist layer to form the drift region; removing the patterned photoresist layer and the dielectric layer on the top surface of the substrate, so that the top surface of the dielectric layer remaining in the trench is flush with the top surface of the substrate.

[0023] In the method for manufacturing a semiconductor device in the above embodiments, when forming the target doping region and the drift region, the same target mask is used, reducing the cost of manufacturing the high-voltage semiconductor device.

[0024] In one embodiment, before forming the drain doping region, the top surface of the target doping region is located inside the top surface of the substrate.

[0025] In the method for manufacturing a semiconductor device in the above embodiments, by restricting the top surface of the target doping region to be inside the top surface of the substrate before forming the drain doping region, the contact between the drain doping region and the target doping region is ensured, and thus the improvement of the performance of the safe operating area (SOA) is ensured.

[0026] In a second aspect, embodiments of the present disclosure further provide a semiconductor device, including: a semiconductor device prepared by using the preparation method of any one of the above semiconductor devices.

[0027] The unexpected technical effects that can be produced by the embodiments of the present disclosure include: by forming a second-type target doping region in the second-type drift region, which has a different ion concentration from the drift region and an "L"-shaped longitudinal section, the doping concentration in the drift region under the gate structure is relatively low, reducing the hot carrier impact ionization rate under the gate structure, and the doping concentration of the target doping region near the sidewall and bottom surface of the trench under the drain doping region is relatively high, reducing the hot carrier impact ionization rate of the drain doping region in the target doping region. Therefore, the embodiments of the present disclosure can at least improve the hot carrier injection (HCI) reliability of high-voltage devices and the performance of the safe operating area of high-voltage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 It is a schematic flowchart of a preparation method of a semiconductor device provided in an embodiment;

[0030] Figure 2 It is a schematic longitudinal sectional structure diagram of the structure obtained in step S2000 in the preparation method of a semiconductor device provided in an embodiment Figure 1 ;

[0031] Figure 3 It is a schematic longitudinal sectional structure diagram of the structure obtained in step S2000 in the preparation method of a semiconductor device provided in an embodiment Figure 2 ;

[0032] Figure 4 It is a schematic longitudinal sectional structure diagram of the structure obtained in step S3000 in the preparation method of a semiconductor device provided in an embodiment;

[0033] Figure 5 It is a schematic longitudinal sectional structure diagram of the structure obtained in step S4000 in the preparation method of a semiconductor device provided in an embodiment Figure 1 ;

[0034] Figure 6 It is a schematic longitudinal sectional structure diagram of the structure obtained in step S4000 in the preparation method of a semiconductor device provided in an embodiment Figure 2;

[0035] Figure 7 Schematic longitudinal cross - sectional structure of the structure obtained in step S5000 in the manufacturing method of the semiconductor device provided in an embodiment Figure 1 ;

[0036] Figure 8 Schematic longitudinal cross - sectional structure of the structure obtained in step S5000 in the manufacturing method of the semiconductor device provided in an embodiment Figure 2 ;

[0037] Figure 9 Schematic longitudinal cross - sectional structure of the structure obtained in step S5000 in the manufacturing method of the semiconductor device provided in an embodiment Figure 3 ;

[0038] Figure 10 Schematic longitudinal cross - sectional structure of the structure obtained in step S6000 in the manufacturing method of the semiconductor device provided in an embodiment Figure 1 ;

[0039] Figure 11 Schematic longitudinal cross - sectional structure of the structure obtained in step S6000 in the manufacturing method of the semiconductor device provided in an embodiment Figure 2 。

[0040] Description of reference numerals:

[0041] 201, substrate; 202, well region; 401, sacrificial layer; 403, trench; 501, target doping region; 601, patterned photoresist layer; 602, high - voltage device region; 603, other regions; 701, dielectric layer; 801, drift region; 1001, gate sidewall; 1002, gate oxide layer; 1003, gate; 1101, source doping region; 1102, drain doping region. Detailed implementation manners

[0042] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0045] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0046] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, and variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0048] Please refer to Figures 1 - 11 , embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including the following steps:

[0049] Step S1000: Provide a substrate 201.

[0050] Wherein, the substrate 201 may be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 201 may be a single-layer structure or a multi-layer structure. For example, the substrate 201 may be a silicon substrate 201, a silicon germanium substrate 201, a silicon germanium carbon substrate 201, a silicon carbide substrate 201, a gallium arsenide substrate 201, an indium arsenide substrate 201, an indium phosphide substrate 201, or other III / V semiconductor substrates 201 or II / VI semiconductor substrates 201. Alternatively, for another example, the substrate 201 may be a layered substrate 201 including, for example, silicon / silicon carbide, silicon on insulator, or silicon germanium on insulator. Therefore, the type of the substrate 201 should not limit the protection scope of the present disclosure.

[0051] Step S2000: Form a well region 202 of a first type in the substrate 201.

[0052] Wherein, the well region 202 includes source regions and drain regions that are spaced apart, and the source regions are used to form source doping regions, and the drain regions are used to form drain doping regions.

[0053] Step S3000: Form a trench 403 in the well region 202 based on a target mask (not shown).

[0054] Wherein, the trench 403 is located between the source regions and the drain regions. The longitudinal cross-section of the trench 403 may be an inverted trapezoid. The bottom surface of the trench 403 is higher than the bottom surface of the well region 202.

[0055] Step S4000: Inject ions of a second type into the target sidewalls and a part of the bottom of the trench 403 to form a target doping region 501 of the second type with a longitudinal cross-section of "L" shape.

[0056] Among them, the target sidewall is adjacent to the drain region.

[0057] Step S5000: After forming the dielectric layer 701 in the trench 403, a second-type drift region 801 is formed in the well region 202.

[0058] Step S6000: A gate 1003 structure is formed on the substrate 201 between the target doping region 501 and the source region, a source doping region 1101 is formed in the source region, and a drain doping region 1102 is formed in the drain region.

[0059] In the above embodiment, by forming a second-type target doping region 501 with an ion concentration different from that of the drift region 801 and having an "L"-shaped cross section in the second-type drift region 801, the doping concentration of the drift region 801 under the gate 1003 structure is relatively low, reducing the hot carrier impact ionization rate under the gate 1003 structure. The doping concentration of the target doping region 501 near the sidewall and bottom surface of the trench 403 under the drain doping region 1102 is relatively high, reducing the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501. Therefore, the embodiments of the present disclosure can at least improve the hot carrier injection (HCI) reliability of high-voltage devices and the safe operating area performance of high-voltage devices.

[0060] Here, it should be noted that HCI (Hot Carrier Injection) refers to the phenomenon in semiconductor devices where carriers (electrons or holes) are accelerated due to an excessively high electric field intensity and injected into the gate 1003 oxide layer of the transistor. This can cause physical or chemical changes in the gate oxide layer, thereby affecting device performance. Hot carrier injection can lead to the degradation of the electrical characteristics of the device, manifested as threshold voltage drift, increased gate 1003 leakage current, reduced drive current, etc. This phenomenon intensifies with the reduction of device size and the increase of voltage, and is one of the important factors affecting the reliability of high-voltage devices. The safe operating area (SOA) refers to the range within which a semiconductor device can operate safely without damage under specific voltage, current, and power conditions. It defines the maximum voltage, current, or power consumption that the device can withstand under different operating conditions. Exceeding the SOA may lead to thermal runaway, breakdown, or permanent damage of the device. Therefore, the improvement of hot carrier injection (HCI) reliability and the SOA of high-voltage devices is particularly important for high-voltage devices.

[0061] In step S2000, please refer to Figures 2 - 3 , among which, Figure 2 is to form a well region 202 in the substrate 201.

[0062] Specifically, the following steps can be used to form a well region 202 of the first type in the substrate 201: injecting ions of the first type into the substrate 201; and pushing the ions of the first type into a position close to the bottom of the substrate 201 based on a thermal annealing process.

[0063] Here, in the thermal annealing process, the doped ions can be rearranged in the lattice by heating and enter the active sites, thereby effectively "activating" the doped ions. The thermal annealing process restores the normal structure of the bonds between the implanted ions and the crystalline silicon by heating, and can also reduce the lattice damage generated during the implantation process.

[0064] Specifically, the annealing temperature and time can be controlled to push the ions of the first type into a position close to the bottom of the substrate 201. A higher temperature can accelerate the atomic migration speed, accelerate the lattice repair and the activation of the dopant; and the control of time determines the diffusion depth and the degree of stress release during the annealing process.

[0065] Among them, the doping concentration of the well region 202 is: To .

[0066] As an example, the doping concentration of the well region 202 can be , , , and so on.

[0067] As an example, taking an N-type LDMOS high-voltage device as an example, the semiconductor structure formed after injecting ions of the first type into the substrate 201 is as shown in Figure 2 . In the semiconductor structure shown in Figure 2 , it includes the substrate 201 and the well region 202 without performing the thermal annealing process. After pushing the ions of the first type into a position close to the bottom of the substrate 201 based on the thermal annealing process, the formed semiconductor structure is as shown in Figure 3 . In the semiconductor structure shown in Figure 3 , the ions of the first type are pushed into a position close to the bottom of the substrate 201 based on the thermal annealing process, forming a well region 202 of the first type.

[0068] Among them, taking an N-type LDMOS high-voltage device as an example, the ions of the first type in the well region 202 can be P-type ions.

[0069] In step S3000, please refer to Figure 4 , and form a trench 403 in the well region 202 based on the target mask, where the trench 403 is located between the source region and the drain region.

[0070] As an example, please continue to refer to Figure 4, a sacrificial layer 401 can be formed between the target photomask and the well region 202 to avoid damaging the well region 202 during the etching of the trench 403 device.

[0071] In step S4000, please refer to Figure 5 、 Figure 6 , ions of the second type are implanted into the target sidewall and part of the bottom of the trench 403 to form a second-type target doping region 501 with an "L"-shaped longitudinal section; the target sidewall is adjacent to the drain region.

[0072] Among them, the doping concentration of the target doping region 501 is: To .

[0073] As an example, the doping concentration of the target doping region 501 can be: 、 、 and so on.

[0074] Here, by restricting the concentration of the target doping region 501, the safe operating area performance of the high-voltage device is further improved.

[0075] Exemplarily, the longitudinal section of the trench 403 is "inverted trapezoid", which can reduce the difficulty of trench etching and the process cost.

[0076] Exemplarily, the inner angle of the "L"-shaped target doping region 501 is an obtuse angle, which is beneficial to form a rounded target doping region 501, avoiding the formation of sharp acute angles at the corners of the target doping region 501, and generating tip discharge phenomena or leakage current.

[0077] By forming the target doping region 501 on the sidewall and bottom surface of the trench 403 close to the drain doping region 1102, the high ion concentration below the drain doping region 1102 is ensured, and the hot carrier impact ionization rate between the drain doping region 1102 and the target doping region 501 is reduced, thereby improving the safe operating area (SOA) performance.

[0078] Specifically, in step S4000, first, a patterned mask layer (not shown) is formed based on the target photomask, and based on the patterned mask layer, ions of the second type are implanted into the target sidewall and part of the bottom of the trench 403 to form a second-type target doping region 501 with an "L"-shaped longitudinal section.

[0079] As an example, please refer to Figure 5 , Figure 5 shows the second-type target doping region 501 with an "L" shape formed on the target sidewall and part of the bottom of the trench 403.

[0080] As an example, taking an N-type LDMOS high-voltage device as an example, ions of the second type, which are N-type ions, are implanted into the target sidewall and part of the bottom of the trench 403.

[0081] As an example, please refer to Figure 6 , Figure 6 shows the patterned photoresist layer 601 formed on the target mask. The patterned photoresist layer 601 covers the areas where ion implantation is not required. The areas where ion implantation is not required include part of the high-voltage device area 602 and other areas 603 in the semiconductor device. Based on the protection of the patterned photoresist layer 601, the ions implanted during the ion implantation process are prevented from diffusing into part of the high-voltage device area 602 and other areas 603 in the semiconductor device where ion implantation is not required.

[0082] In one embodiment, during the process of implanting ions of the second type to form the target doped region 501, by blocking through the patterned mask layer and controlling the ion implantation angle, an "L"-shaped target doped region 501 of the second type is formed on the target sidewall and part of the bottom of the trench 403. Specifically, please continue to refer to Figure 6 , Figure 6 The arrow in shows the ion implantation angle during the formation of the target doped region 501.

[0083] Here, the present disclosure does not limit the ion implantation angle. During the actual operation process, the staff can control the ion implantation angle according to the actual situation and the opening position and shape of the patterned photoresist layer 601, so as to form an "L"-shaped target doped region 501 of the second type on the target sidewall and part of the bottom of the trench 403.

[0084] Among them, the dielectric layer 701 fills the trench 403 and covers the top surface of the substrate 201; a patterned photoresist layer 601 is formed on the top surface of the dielectric layer 701 based on the target mask; second-type ion implantation is performed into the well region 202 based on the patterned photoresist layer 601 to form the drift region 801; the patterned photoresist layer 601 and the dielectric layer 701 on the top surface of the substrate 201 are removed, so that the top surface of the dielectric layer 701 remaining in the trench 403 is flush with the top surface of the substrate 201.

[0085] In this way, when forming the target doped region 501 and the drift region 801, the same target mask is used, reducing the complexity and cost of fabricating the high-voltage semiconductor device.

[0086] Among them, the top surface of the target doped region 501 is not lower than the bottom surface of the drain doped region 1102; the bottom surface of the target doped region 501 is higher than the bottom surface of the drift region 801. By restricting the positions of the target doped region 501 and the drain doped region 1102, the target doped region 501 is formed below the drain doped region 1102, the top surface of the target doped region 501 is flush with the bottom surface of the drain doped region 1102, and the bottom surface of the drain doped region 1102 partially covers the top surface of the target doped region 501, ensuring that the ion concentration below the drain doped region 1102 is higher than that of the drift region 801, thereby ensuring the improvement of the Safe Operating Area (SOA) performance of the high-voltage device.

[0087] In step S5000, please refer to Figures 7 - 9 , Figure 7 shows the structure of the semiconductor device after forming the dielectric layer 701 in the trench 403. Specifically, the steps of forming the dielectric layer 701 in the trench 403 include: forming the dielectric layer 701 in the trench 403 and planarizing the dielectric layer 701. Among them, the dielectric layer 701 can be formed in the trench 403 by means of Chemical Vapor Deposition (CVD), Thermal Oxidation, High Density Plasma (HDP) deposition, etc. After filling the trench 403, a planarization process such as Chemical Mechanical Polishing (CMP) can be used to polish off the excess dielectric layer 701 material to form a flat surface and ensure uniform and defect-free filling in the trench 403.

[0088] Among them, the doping concentration of the drift region 801 is: to .

[0089] As an example, the doping concentration of the drift region 801 can be: , , , and so on.

[0090] Here, by restricting the concentration of the drift region 801, the reliability of Hot Carrier Injection (HCI) of the high-voltage device is further improved.

[0091] Please continue to refer to Figure 8 , Figure 9 , Figure 8Shows a semiconductor structure after forming a drift region 801 of the second type within the well region 202. Specifically, the steps of forming a drift region 801 of the second type within the well region 202 include: performing a second-type ion implantation into the well region 202 based on the patterned photoresist layer 601, and pushing the second-type ions to a region near the bottom of the well region 202 based on an annealing process to form a drift region 801 of the second type. Please continue to refer to Figure 8 , after forming the drift region 801 of the second type, there are two regions with different doping concentrations in the drift region 801. By forming a second-type target doping region 501 with an "L"-shaped longitudinal section having a different ion concentration from that of the drift region 801 in the drift region 801 of the second type, the doping concentration below the gate 1003 structure in the drift region 801 is relatively low, reducing the hot carrier impact ionization rate below the gate 1003 structure, and the doping concentration of the target doping region 501 near the sidewall and bottom surface of the trench 403 below the drain doping region 1102 is relatively high, reducing the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501.

[0092] Specifically, please continue to refer to Figure 9 , Figure 9 Shows the overall structure of the semiconductor device, as Figure 9 shown, in the present disclosure, the same patterned photoresist layer 601 is used as the mask plate for both second-type ion implantations. When performing ion implantation for the drift region 801, the direction of ion implantation can be Figure 9 the direction perpendicular to the bottom surface of the substrate 201 as indicated by the arrow in

[0093] In step S6000, please refer to Figures 10 - 11 , a gate 1003 structure is formed on the substrate 201 between the target doping region 501 and the source region, a source doping region 1101 is formed within the source region, and a drain doping region 1102 is formed within the drain region.

[0094] Among them, a partial dielectric layer 701 is included between the gate 1003 structure and the drain doping region 1102. By forming a partial dielectric layer 701 between the gate 1003 structure and the drain doping region 1102, the channel layer below the gate 1003 structure is connected to the drain doping region 1102 via the drift region 801 and the target doping region 501 below the dielectric layer 701, while avoiding the generation of current leakage channels and improving the SOA performance.

[0095] Specifically, the step of forming the source doping region 1101 within the source region is to implant source ions into the source region; the step of forming the drain doping region 1102 within the drain region is to implant drain ions into the drain region.

[0096] Specifically, after the gate 1003 structure is formed, a source doping region 1101 is formed in the source region, and a drain doping region 1102 is formed in the drain region. By forming the drain doping region 1102 and the source doping region 1101 in the drain region and the source region, the basic structure of the high-voltage device is formed, and by forming the drain doping region 1102 in the drain region that contacts the target doping region 501, the Safe Operating Area (SOA) performance is improved.

[0097] Please continue to refer to Figure 10 , Figure 10 which shows the semiconductor structure after the gate 1003 structure is formed on the substrate 201 between the target doping region 501 and the source region. As Figure 10 shown, the gate 1003 structure includes a gate 1003, a gate sidewall 1001, and a gate oxide layer 1002.

[0098] Among them, the gate sidewall 1001 can be composed of silicon dioxide or other dielectric materials, which can optimize the electric field distribution, improve the breakdown voltage performance, reduce the leakage current, and enhance the device reliability, ensuring that the high-voltage device can operate stably in a high-voltage and high-power environment for a long time.

[0099] Among them, the gate oxide layer 1002 can be composed of silicon dioxide ( ) or other high-k materials. In the high-voltage device, the gate oxide layer 1002 can form electrical isolation and affect the on-state performance, breakdown voltage ability, leakage current control, etc. of the high-voltage device.

[0100] Among them, the material of the gate 1003 can be polysilicon material, or transition metals such as titanium (Ti), tantalum (Ta), tungsten (W) with high conductivity and high stability, or nitrides such as titanium nitride ( ), tantalum nitride ( ), etc., which are commonly used to enhance the heat resistance and chemical stability. In some low-cost or low-power devices, aluminum can be used as the material of the gate 1003 due to its low cost and relatively high conductivity.

[0101] Please continue to refer to Figure 11 , Figure 11A semiconductor structure is shown after forming a source doping region 1101 in a source region and a drain doping region 1102 in a drain region. Among them, the source doping region 1101 is formed in the well region 202, the drain doping region 1102 is formed in the drift region 801 and is in contact with the target doping region 501. The doping concentration of the target doping region 501 is relatively high near the sidewall and bottom surface of the trench 403 below the drain doping region 1102, reducing the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501. Therefore, the embodiments of the present disclosure can at least improve the hot carrier injection (HCI) reliability of high-voltage devices and the SOA performance of high-voltage devices.

[0102] Among them, the doping concentration of the drain doping region 1102 is: to .

[0103] Among them, the doping concentration of the source doping region 1101 is: to .

[0104] As an example, the doping concentration of the drain doping region 1102 can be: , , , and so on.

[0105] As an example, the doping concentration of the source doping region 1101 can be: , , , and so on. It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps in

[0106] In some embodiments, the present disclosure provides a semiconductor device, including: a semiconductor device prepared by using the preparation method of any of the above semiconductor devices.

[0107] Please refer to Figure 11, the unexpected technical effects that can be produced by the embodiments of the present disclosure include: by forming a second-type target doping region 501 with an ion concentration different from that of the drift region 801 and an "L"-shaped longitudinal section in the second-type drift region 801, the doping concentration of the drift region 801 under the gate 1003 structure is relatively low, reducing the hot carrier impact ionization rate under the gate 1003 structure, and the doping concentration of the target doping region 501 near the sidewall and bottom surface of the trench 403 under the drain doping region 1102 is relatively high, reducing the hot carrier impact ionization rate of the drain doping region 1102 in the target doping region 501. Therefore, the embodiments of the present disclosure can at least improve the hot carrier injection (HCI) reliability of high-voltage devices and the SOA performance of high-voltage devices.

[0108] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0109] The above embodiments only represent several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; Forming a first type of well region in the substrate, wherein the well region includes a source region and a drain region that are spaced apart; forming a trench in the well region, wherein the trench is located between the source region and the drain region; Implanting second-type ions into the target sidewalls and part of the bottom of the trench based on the patterned photoresist layer formed by the target photomask to form a second-type target doping region with an "L"-shaped longitudinal section; the target sidewall is adjacent to the drain region; removing the patterned photoresist layer; After forming a dielectric layer in the groove, a patterned photoresist layer formed on the top surface of the dielectric layer based on the target photomask forms a second type drift region in the well region whose bottom surface is lower than the bottom surface of the target doping region; the doping concentration of the target doping region is higher than the doping concentration of the drift region; After forming a gate structure on the substrate between the target doping region and the source region, a source doping region is formed in the source region, and a drain doping region is formed in the drain region; the bottom surface of the drain doping region contacts the top surface of the target doping region and is higher than the bottom surface of the dielectric layer.

2. The preparation method according to claim 1, characterized in that: The doping concentration of the target doping region is: to ; and / or; The doping concentration of the drift region is: to .

3. The preparation method according to claim 1, characterized in that: The top surface of the target doping region is not lower than the bottom surface of the drain doping region.

4. The preparation method according to claim 1, characterized in that: A portion of the dielectric layer is included between the gate structure and the drain doped region.

5. The preparation method according to any one of claims 1 to 4, characterized in that: The doping concentration of the well region is: to ; and / or; The doping concentration of the drain doping region is: to .

6. The preparation method according to any one of claims 1 to 4, characterized in that: The longitudinal section of the groove is an "inverted trapezoid".

7. The preparation method according to any one of claims 1 to 4, characterized in that: The inner angle of the "L"-shaped target doping region is an obtuse angle.

8. The preparation method according to any one of claims 1 to 4, characterized in that: The dielectric layer fills the trench and covers the top surface of the substrate; forming the drift region comprises: forming a patterned photoresist layer on the top surface of the dielectric layer based on the target mask; Performing second-type ion implantation into the well region based on the patterned photoresist layer to form the drift region; The patterned photoresist layer and the dielectric layer on the top surface of the substrate are removed, so that the top surface of the dielectric layer remaining in the groove is flush with the top surface of the substrate.

9. The preparation method according to any one of claims 1 to 4, characterized in that: Before forming the drain doping region, the top surface of the target doping region is located at the bottom surface of the drain region.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

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