Lateral enhancement-mode gallium oxide field effect transistor with niO extension gate field plate

Abstract

The application belongs to the technical field of power semiconductors, and relates to a lateral enhancement mode gallium oxide field effect transistor with a NiO extended gate field plate. When the device of the application is in a forward conduction state, an electron accumulation layer is formed in a drift region below the extended gate field plate, thereby reducing the on-resistance of the device and making up for the deficiency of the larger on-resistance of the enhancement mode MOSFET; in a blocking state, the extended gate structure and the N-type gallium oxide drift region form a super-junction-like structure, modulate the electric field distribution, assist in depleting the drift region, improve the breakdown voltage of the device, further improve the doping concentration of the epitaxial layer of the device, and reduce the on-resistance. The device of the application is an enhancement mode device, has the dual advantages of low on-resistance and high breakdown voltage, in addition, the nickel oxide deposition process used in the application is simple, does not introduce additional etching process, avoids the etching damage in the drift region of the device and the premature breakdown caused by the gallium oxide-nickel oxide interface problem.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and relates to a lateral enhancement gallium oxide field effect transistor with a NiO extended gate field plate. BACKGROUND

[0002] Gallium oxide (Ga2O3) based power devices gradually become a new favorite in the field of power devices due to their super-wide band gap (4.9eV), super-high critical breakdown field strength (8MV / cm) and the advantages of low cost, mass production and high-quality single crystal substrate growth. Among many Ga2O3 crystal phases, only the beta-Ga2O3 crystal structure can be grown by the melt method. Compared with traditional silicon-based and third-generation semiconductor materials such as gallium nitride and silicon carbide, the beta-Ga2O3 based power device has the advantages of high breakdown voltage, low on-resistance and low cost, and has great application prospects in the fields of high voltage, high power and high energy efficiency. However, since beta-Ga2O3 has not formed effective P-type doping, most of the current beta-Ga2O3 power MOSFETs are depletion mode devices, which will increase the off-state power consumption of the device. The enhancement mode beta-Ga2O3 power MOSFET prepared by the trench gate, P-NiO gate and other methods will weaken the current capacity of the device, increase the specific on-resistance of the device, and the existing trench gate gallium oxide MOSFET and super junction gallium oxide MOSFET inevitably etch and groove in the device drift region, which not only occupies the drift region space and increases the on-resistance, but also causes complex interface problems. SUMMARY

[0003] In view of the above problems, the application provides a lateral enhancement gallium oxide field effect transistor with a NiO extended gate field plate.

[0004] The technical scheme of the application is as follows:

[0005] The lateral enhancement gallium oxide field effect transistor with the NiO extended gate field plate is provided with, from bottom to top along the vertical direction of the device, a gallium oxide substrate 1, a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3.

[0006] Characterized in that, the gallium oxide epitaxial layer 3 has a drain heavily doped region 4 and a source heavily doped region 5 on both sides respectively; the lower surface of the drain heavily doped region 4 is in contact with the upper surface of the gallium oxide buffer layer 2, and the upper surface of the drain heavily doped region 4 has a drain metal 6 away from one end of the source heavily doped region 5; the lower surface of the source heavily doped region 5 is in contact with the upper surface of the gallium oxide buffer layer 2, and the upper surface of the source heavily doped region 5 has a source metal 7 away from one end of the drain heavily doped region 4; the upper surface of the drain heavily doped region 4, the upper surface of the gallium oxide epitaxial layer 3 and the upper surface of the source heavily doped region 5 between the drain metal 6 and the source metal 7 have a gate oxide layer 8; the gate structure is formed on the upper surface of the gate oxide layer 8 close to the source metal 7 side, which is composed of a nickel oxide strip and a gate metal 10, the nickel oxide strip is in contact with the gate oxide layer 8 and the gate metal 10 respectively, and the nickel oxide strip extends along the upper surface of the gate oxide layer 8 to the side close to the drain metal 6, forming an extended gate field plate.

[0007] Further, the gate structure is a planar gate structure, the nickel oxide strip includes a first P-type nickel oxide strip 91 and a second P-type nickel oxide strip 92, the first P-type nickel oxide strip 91 is located on the upper surface of the gate oxide layer 8, the second P-type nickel oxide strip 92 is located on the upper surface of the first P-type nickel oxide strip 91, and one end of the second P-type nickel oxide strip 92 close to the source metal 7 is flush with one end of the first P-type nickel oxide strip 91 close to the source metal 7 in the vertical direction; the gate metal 10 is located on the upper surface of the second P-type nickel oxide strip 92; wherein the lateral width of the second P-type nickel oxide strip 92 is equal to the lateral width of the gate metal 10, and the two ends of the second P-type nickel oxide strip 92 are completely aligned with the two ends of the gate metal 10 in the vertical direction; the lateral width of the first P-type nickel oxide strip 91 is less than the lateral width of the gallium oxide epitaxial layer 3, and there is a spacing between the two ends of the first P-type nickel oxide strip 91 and the two ends of the gallium oxide epitaxial layer 3.

[0008] Further, the gate structure is a slot gate structure, a groove is formed on the gallium oxide epitaxial layer 3, the gate oxide layer 8 is filled in the bottom and inner wall of the groove, the gate metal 10 is filled in the groove and extends out of the groove, and the nickel oxide strip is the first P-type nickel oxide strip 91, one end of the first P-type nickel oxide strip 91 is in contact with the side wall of the gate metal 10.

[0009] Further, the gate structure is a slot gate structure, a groove is formed on the gallium oxide epitaxial layer 3, the gate oxide layer 8 is filled in the groove bottom and inner wall, the nickel oxide strip includes a first P-type nickel oxide strip 91 and a second P-type nickel oxide strip 92, the second P-type nickel oxide strip 92 is filled in the groove and the upper surface of the second P-type nickel oxide strip 92 is flush with the upper surface of the gate oxide layer 8; the first P-type nickel oxide strip 91 covers the second P-type nickel oxide strip 92, and one end of the first P-type nickel oxide strip 91 close to the drain metal 6 is flush with the end surface of the second P-type nickel oxide strip 92 in the vertical direction; the gate metal 10 is located on the upper surface of the second P-type nickel oxide strip 92 and directly above the second P-type nickel oxide strip 92, and the lateral width of the gate metal 10 is the same as the lateral width of the second P-type nickel oxide strip 92.

[0010] The manufacturing method of the device includes the following steps:

[0011] Step 1: Forming a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3 on the upper surface of the gallium oxide substrate 1 in sequence by epitaxy;

[0012] Step 2: Forming a source heavily doped region 5 and a drain heavily doped region 4 at both ends of the gallium oxide epitaxial layer 3 by high-energy ion implantation;

[0013] Step 3: Depositing a drain metal 6 and a source metal 7 on the drain heavily doped region 4 and the source heavily doped region 5 respectively by a lift-off technique;

[0014] Step 4: Forming a gate oxide layer 8 by an atomic layer deposition process;

[0015] Step 5: Generating a gate structure on the gate oxide layer 8.

[0016] When the gate structure is a planar gate structure, the manufacturing method is as follows:

[0017] A sputtering process is used to form a first P-type nickel oxide strip 91 on the upper surface of the gate oxide layer 8, and then a second P-type nickel oxide strip 92 is formed above the first P-type nickel oxide strip 91 by a sputtering process, wherein the oxygen flux during the formation of the second P-type nickel oxide strip 92 is greater than the oxygen flux during the formation of the first P-type nickel oxide strip 91, so as to ensure that the first P-type nickel oxide strip 91 has a low hole concentration and the second P-type nickel oxide strip 92 has a high hole concentration;

[0018] A gate metal 10 is deposited on the upper surface of the second P-type nickel oxide strip 92.

[0019] When the gate structure is a slot gate structure, the manufacturing method corresponds to the following two methods:

[0020] 1) A groove is formed by ICP etching, and then the etching interface damage is repaired by a wet method, and then a gate oxide layer 8 is formed by an atomic layer deposition process;

[0021] Forming the first P-type nickel oxide strip 91 above the gate oxide layer by a sputtering process;

[0022] Depositing the gate metal 10 on the upper surface of the gate oxide layer 8 above the groove and in contact with the first P-type nickel oxide strip 91.

[0023] 2) Forming the groove by ICP etching, repairing the etching interface damage by wet method, and then forming the gate oxide layer 8 by atomic layer deposition (ALD) process;

[0024] Depositing the second P-type nickel oxide 92 in the groove of the gate oxide layer 8 to be flush with the etching mesa, and then forming the first P-type nickel oxide strip 91 on the upper surface of the gate oxide layer 8 and the second P-type nickel oxide 92 by a sputtering process;

[0025] Depositing the gate metal 10 on the upper surface of the first P-type nickel oxide strip 91 and aligning with the edge of the groove gate.

[0026] The device of the present application is an enhanced device. When the device is turned on in the forward direction, an electron accumulation layer is formed under the extended gate, reducing the on-resistance of the device. When the device is blocked, the extended gate structure forms a super-junction-like structure with the N-type gallium oxide drift region, modulates the electric field distribution, assists in depleting the drift region, and improves the breakdown voltage of the device. Further, the drift region doping concentration is further improved, and the on-resistance is reduced. The nickel oxide deposition process used in the present application is simple, does not introduce additional etching process, and avoids the etching damage in the device drift region and the premature breakdown caused by the gallium oxide-nickel oxide interface problem. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a structural schematic diagram of the device described in Embodiment 1 of the present application;

[0028] Figure 2 is a structural schematic diagram of the device described in Embodiment 2 of the present application;

[0029] Figure 3 is a structural schematic diagram of the device described in Embodiment 3 of the present application;

[0030] Figure 4 is a process flow schematic diagram of the device described in Embodiment 1 of the present application; DETAILED DESCRIPTION

[0031] The technical solutions of the present application will be described in detail below in combination with the drawings and embodiments:

[0032] Embodiment 1:

[0033] As shown in Figure 1 , a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate comprises:

[0034] From bottom to top along the vertical direction of the device, it comprises a gallium oxide substrate 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3;

[0035] The device is characterized in that a right heavy doped drain region 4 is formed in the gallium oxide epitaxial layer 3, and a left heavy doped source region 5 is formed in the gallium oxide epitaxial layer 3; a drain metal 6 is deposited on the surface of the heavy doped drain region 4, and a source metal 7 is deposited on the surface of the heavy doped source region 5; a gate structure is formed above the gallium oxide epitaxial layer 3 and between the drain metal 6 and the source metal 7, and the gate structure comprises a gate oxide layer 8, a first P-type nickel oxide strip 91, a second P-type nickel oxide strip 92, and a gate metal 10; the gate oxide layer 8 covers the upper surface of the gallium oxide epitaxial layer 3; the first P-type nickel oxide strip 91 covers the upper surface of the gate oxide layer 8, and the first P-type nickel oxide strip 91 extends from the side far away from the drain to the side close to the drain without contacting the drain metal 6, thereby forming an extended gate field plate; the second P-type nickel oxide strip 92 covers the upper surface of the first P-type nickel oxide strip 91 far away from the drain, and the left end of the second P-type nickel oxide strip 92 is aligned with the first P-type nickel oxide strip 91, and the right side of the second P-type nickel oxide strip 92 does not extend to the side close to the drain; the gate metal 10 covers the second P-type nickel oxide strip 92.

[0036] The working principle of the present example is as follows:

[0037] The lateral enhancement type gallium oxide field effect transistor with the NiO extended gate field plate provided by the present application utilizes the high-concentration second P-type nickel oxide strip 92 to deplete the carrier concentration below the gate of the device, thereby forming an enhancement type device; in the forward conduction state, the gate metal 10 and the drain metal 6 are positively biased, and the voltage applied by the gate metal 10 is greater than the voltage applied by the drain metal 6, and the source metal 7 is grounded; an electron accumulation layer is formed in the drift region below the extended gate field plate, thereby reducing the on-resistance of the device and making up for the deficiency of the enhancement type MOSFET in that the on-resistance is large; in the blocking state, the gate metal 10 and the source metal 7 are grounded, and a high voltage is applied to the drain metal 6; the extended gate structure and the N-type gallium oxide drift region form a super-junction-like structure, thereby modulating the electric field distribution, assisting in depleting the drift region, improving the breakdown voltage of the device, further improving the doping concentration of the epitaxial layer of the device, and reducing the on-resistance.

[0038] As Figure 4 Figures (a)-(f) show the process flow diagram of the embodiment 1 of the present application, and specifically comprising the following steps:

[0039] Step 1: sequentially epitaxially forming a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3 on a gallium oxide substrate 1;

[0040] Step 2: forming a heavy doped source region 5 and a heavy doped drain region 4 by high-energy ion implantation;

[0041] Step 3: depositing a drain metal 6 and a source metal 7 on the heavy doped drain region 4 and the heavy doped source region 5, respectively, by a lift-off technique;

[0042] Step 4: Forming gate oxide layer 8 by atomic layer deposition (ALD) process;

[0043] Step 5: Forming first P-type nickel oxide strip 91 above the gate oxide layer by sputtering process, then forming second P-type nickel oxide strip 92 above the first P-type nickel oxide strip 91 by sputtering process, wherein the oxygen flux during the formation of the second P-type nickel oxide strip 92 should be greater than that of the first P-type nickel oxide strip 91, so as to ensure the formation of the first P-type nickel oxide strip 91 with low hole concentration and the second P-type nickel oxide strip 92 with high hole concentration;

[0044] Step 6: Depositing gate metal 10 on the upper surface of the second P-type nickel oxide strip 92.

[0045] Example 2:

[0046] As shown in FIG. 2, it is a structure schematic diagram of the lateral enhancement gallium oxide field effect transistor with recessed gate and NiO extended gate field plate of Example 2, which is different from the structure of Example 1 in that the device enhancement is realized by the recessed gate structure instead of the high-concentration second P-type nickel oxide strip 92, and the working principle is basically the same as that of Example 1. Figure 2

[0047] The difference between the process steps of this example and Example 1 is that in Step 4, the recessed gate structure is first formed by ICP etching, and the etching interface damage is repaired by wet method, and then the gate oxide layer 8 is formed by atomic layer deposition (ALD) process; in Step 5, the second P-type nickel oxide 92 is first deposited to be flush with the etching mesa in the recess of the gate oxide layer 8, and then the first P-type nickel oxide strip 91 is formed on the upper surface of the gate oxide layer 8 and the second P-type nickel oxide 92 by sputtering process; in Step 6, the gate metal 10 is deposited on the upper surface of the first P-type nickel oxide strip 91 and aligned with the edge of the recessed gate.

[0048] Example 3:

[0049] As shown in FIG. 3, it is a structure schematic diagram of the lateral enhancement gallium oxide field effect transistor with recessed gate and NiO extended gate field plate of Example 3, which is different from the structure of Example 1 in that this example has a recessed gate structure, and the recessed gate is filled with a high-concentration second P-type nickel oxide strip 92, which together further improves the threshold of the device, and the working principle is basically the same as that of Example 1. Figure 3

[0050] ​​The difference between the present example and the process steps of Embodiment 1 is that in Step 4, the recessed gate structure is first formed by ICP etching, and the etching interface damage is repaired by wet etching, and then the gate oxide layer 8 is formed by atomic layer deposition (ALD) process; in Step 5, the second P-type nickel oxide 92 is first deposited to fill the recessed gate of the gate oxide layer 8 to be flush with the etching mesa, and then the first P-type nickel oxide strip 91 is formed on the surface of the gate oxide layer 8 and the second P-type nickel oxide 92 by sputtering process; in Step 6, the gate metal 10 is deposited on the surface of the first P-type nickel oxide strip 91 and is aligned with the edge of the recessed gate.

[0051] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A lateral enhancement mode gallium oxide field effect transistor with NiO extended gate field plate, from bottom to top, a gallium oxide substrate (1), a gallium oxide buffer layer (2), and a gallium oxide epitaxial layer (3) are sequentially stacked in the vertical direction of the device. characterized in that There are a drain heavily doped region (4) and a source heavily doped region (5) on both sides of the gallium oxide epitaxial layer (3); the lower surface of the drain heavily doped region (4) is in contact with the upper surface of the gallium oxide buffer layer (2), and the upper surface of the drain heavily doped region (4) away from the source heavily doped region (5) has a drain metal (6); the lower surface of the source heavily doped region (5) is in contact with the upper surface of the gallium oxide buffer layer (2), and the upper surface of the source heavily doped region (5) away from the drain heavily doped region (4) has a source metal (7); the upper surface of the drain heavily doped region (4), the upper surface of the gallium oxide epitaxial layer (3), and the upper surface of the source heavily doped region (5) between the drain metal (6) and the source metal (7) have a gate oxide layer (8); there is a gate structure on the upper surface of the gate oxide layer (8) near the source metal (7), which is composed of a nickel oxide strip and a gate metal (10), the nickel oxide strip is in contact with the gate oxide layer (8) and the gate metal (10), respectively, and the nickel oxide strip extends along the upper surface of the gate oxide layer (8) towards the side near the drain metal (6) to form an extended gate field plate. The gate structure is a planar gate structure, the nickel oxide strip includes a first P-type nickel oxide strip (91) with low hole concentration and a second P-type nickel oxide strip (92) with high hole concentration, the first P-type nickel oxide strip (91) is located on the upper surface of the gate oxide layer (8), the second P-type nickel oxide strip (92) is located on the upper surface of the first P-type nickel oxide strip (91), and the end of the second P-type nickel oxide strip (92) near the source metal (7) is flush with the end of the first P-type nickel oxide strip (91) near the source metal (7) in the vertical direction; the gate metal (10) is located on the upper surface of the second P-type nickel oxide strip (92); wherein the lateral width of the second P-type nickel oxide strip (92) is equal to the lateral width of the gate metal (10), and the two ends of the second P-type nickel oxide strip (92) are completely aligned with the two ends of the gate metal (10) in the vertical direction; the lateral width of the first P-type nickel oxide strip (91) is less than the lateral width of the gallium oxide epitaxial layer (3), and there is a spacing between the two ends of the first P-type nickel oxide strip (91) and the two ends of the gallium oxide epitaxial layer (3).

2. A lateral enhancement mode gallium oxide field effect transistor with NiO extended gate field plate, from bottom to top, a gallium oxide substrate (1), a gallium oxide buffer layer (2), and a gallium oxide epitaxial layer (3) are sequentially stacked in the vertical direction of the device. characterized in that The gallium oxide epitaxial layer (3) has a drain heavily doped region (4) and a source heavily doped region (5) on both sides; the lower surface of the drain heavily doped region (4) is in contact with the upper surface of the gallium oxide buffer layer (2), and the upper surface of the drain heavily doped region (4) has a drain metal (6) away from one end of the source heavily doped region (5); the lower surface of the source heavily doped region (5) is in contact with the upper surface of the gallium oxide buffer layer (2), and the upper surface of the source heavily doped region (5) has a source metal (7) away from one end of the drain heavily doped region (4); the upper surface of the drain heavily doped region (4), the upper surface of the gallium oxide epitaxial layer (3) and the upper surface of the source heavily doped region (5) between the drain metal (6) and the source metal (7) have a gate oxide layer (8); the gate structure is formed on the upper surface of the gate oxide layer (8) near the source metal (7) side, and the gate structure is composed of a nickel oxide strip and a gate metal (10), the nickel oxide strip is in contact with the gate oxide layer (8) and the gate metal (10) respectively, and the nickel oxide strip extends along the upper surface of the gate oxide layer (8) to the side near the drain metal (6) to form an extended gate field plate; The gate structure is a slot gate structure, a groove is formed on the upper layer of the gallium oxide epitaxial layer (3), the gate oxide layer (8) is filled in the bottom and inner wall of the groove, the nickel oxide strip includes a first P-type nickel oxide strip (91) with low hole concentration and a second P-type nickel oxide strip (92) with high hole concentration, the second P-type nickel oxide strip (92) is filled in the groove and the upper surface of the second P-type nickel oxide strip (92) is flush with the upper surface of the gate oxide layer (8); the first P-type nickel oxide strip (91) covers the second P-type nickel oxide strip (92), and one end of the first P-type nickel oxide strip (91) near the drain metal (6) is flush with the end surface of the second P-type nickel oxide strip (92) in the vertical direction; the gate metal (10) is located on the upper surface of the second P-type nickel oxide strip (92) and directly above the second P-type nickel oxide strip (92), and the lateral width of the gate metal (10) is the same as the lateral width of the second P-type nickel oxide strip (92).

3. A method for fabricating a lateral enhancement mode gallium oxide field effect transistor having a NiO extension gate field plate as claimed in claim 1, characterized by, The method comprises the following steps: Step 1: sequentially epitaxially forming a gallium oxide buffer layer (2) and a gallium oxide epitaxial layer (3) on the upper surface of a gallium oxide substrate (1); Step 2: forming a source heavily doped region (5) and a drain heavily doped region (4) at both ends of the gallium oxide epitaxial layer (3) by high-energy ion implantation; Step 3: depositing a drain metal (6) and a source metal (7) on the drain heavily doped region (4) and the source heavily doped region (5) respectively by exfoliation technology; Step 4: forming a gate oxide layer (8) by atomic layer deposition process; Step 5: generating a gate structure on the gate oxide layer (8); the gate structure is a planar gate structure, and the manufacturing method is as follows: Sputtering process on the surface of the gate oxide layer (8) form a first P-type nickel oxide strip (91), followed by the first P-type nickel oxide strip (91) above by sputtering process to form a second P-type nickel oxide strip (92), wherein the oxygen flux when forming sputtering second P-type nickel oxide strip (92) is greater than the oxygen flux of the first P-type nickel oxide strip (91) to ensure the formation of a low hole concentration of the first P-type nickel oxide strip (91) and a high hole concentration of the second P-type nickel oxide strip (92); Depositing a gate metal (10) on the surface of the second P-type nickel oxide strip (92).

4. The method for fabricating a lateral enhancement-mode gallium oxide field effect transistor with NiO extension gate field plate as claimed in claim 2, wherein Comprising the following steps: Step 1: Forming a gallium oxide buffer layer (2) and a gallium oxide epitaxial layer (3) on the surface of the gallium oxide substrate (1) in turn; Step 2: Forming a source heavily doped region (5) and a drain heavily doped region (4) at both ends of the gallium oxide epitaxial layer (3) by high-energy ion implantation; Step 3: Depositing a drain metal (6) and a source metal (7) on the drain heavily doped region (4) and the source heavily doped region (5) respectively by exfoliation technology; Step 4: Forming a gate oxide layer (8) by atomic layer deposition process; Step 5: Forming a gate structure on the gate oxide layer (8); the gate structure is a slot gate structure, and the manufacturing method is: Forming a groove by ICP etching, repairing etching interface damage by wet method, and then forming a gate oxide layer (8) by atomic layer deposition (ALD) process; Depositing a high-concentration second P-type nickel oxide strip (92) in the groove of the gate oxide layer (8) to be flush with the etching mesa, and then forming a low-concentration first P-type nickel oxide strip (91) on the surface of the gate oxide layer (8) and the second P-type nickel oxide strip (92) by sputtering process; Depositing a gate metal (10) on the surface of the first P-type nickel oxide strip (91) and aligning with the edge of the groove gate.

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