Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A semiconductor device includes a first electrode, first, second, fourth, and sixth semiconductor regions of a first conductivity type, third, fifth semiconductor regions of a second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is on the first electrode. The second semiconductor region is on the first semiconductor region and includes a first portion and a second portion on a portion of the first portion. The third semiconductor region is located on the other portion of the first portion, and the pitch in the terminal region is increased as the distance from the element region is increased. The fourth semiconductor region is separated from the third semiconductor region with the second portion therebetween, and is arranged alternately with the third semiconductor region. The fifth semiconductor region is on the third semiconductor region in the element region. The sixth semiconductor region is on the fifth semiconductor region. The gate electrode faces a portion of the fifth semiconductor region with a gate insulating layer interposed therebetween. The second electrode is electrically connected to the fifth and sixth semiconductor regions.

Description

[0001] Related Application

[0002] This application claims the priority of Japanese Patent Application No. 2023-147097 (filing date: September 11, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] There is a semiconductor device having a superjunction structure (SJ structure) in which n-type semiconductor regions and p-type semiconductor regions are alternately arranged. By providing the SJ structure, the withstand voltage of the semiconductor device can be improved. The SJ structure is sometimes provided in a device region where semiconductor elements such as transistors are provided and in an end region surrounding the device region. Sometimes, for example, the withstand voltage is degraded in the end region. Summary of the invention

[0005] The semiconductor device according to the embodiment includes a device region and an end region surrounding the device region. The semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a first conductivity type, a plurality of third semiconductor regions of a second conductivity type, a plurality of fourth semiconductor regions of a first conductivity type, a fifth semiconductor region of a second conductivity type, a sixth semiconductor region of a first conductivity type, a gate electrode, and a second electrode. The first electrode is provided in the device region and the end region. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The second semiconductor region has an impurity concentration of the first conductivity type lower than the impurity concentration of the first conductivity type of the first semiconductor region. The second semiconductor region includes a first portion and a plurality of second portions provided on a portion of the first portion. The plurality of third semiconductor regions are provided on another portion of the first portion. The plurality of third semiconductor regions are arranged in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region. The further away from the element region in the second direction, the longer the spacing between the plurality of the third semiconductor regions in the end region. The plurality of the fourth semiconductor regions are separated from the third semiconductor region in the second direction via the second portion. The plurality of the fourth semiconductor regions are arranged alternately with the plurality of the third semiconductor regions in the second direction. The plurality of the fourth semiconductor regions have a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region. The fifth semiconductor region is disposed on the third semiconductor region in the element region. The sixth semiconductor region is disposed on the fifth semiconductor region and is separated from the second portion via a portion of the fifth semiconductor region. The gate electrode is opposed to the portion of the fifth semiconductor region via a gate insulating layer. The second electrode is disposed on the fifth semiconductor region and the sixth semiconductor region and is electrically connected to the fifth semiconductor region and the sixth semiconductor region.

[0006] According to the present embodiment, it is possible to provide a semiconductor device capable of suppressing degradation of breakdown voltage and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic plan view illustrating a semiconductor device according to an embodiment.

[0008] Figure 2 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0009] Figure 3 (a) and Figure 3 (b) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0010] Figure 4 (a) and Figure 4 (b) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0011] Figure 5 (a) and Figure 5 (b) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0012] Figure 6 (a) and Figure 6 (b) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 7 (a)~ Figure 7 (d) is a schematic cross-sectional view illustrating a simulation of characteristics of a semiconductor device. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0015] The drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the sizes and ratios of each other may be shown differently depending on the drawings.

[0016] In this specification and each drawing, the same reference numerals are given to the same elements as those already described, and detailed description thereof will be appropriately omitted.

[0017] In the following description and drawings, n + 、n － 、n －－ 、p + ,p,p － The marks indicate the relative level of each impurity concentration. That is, a mark with "+" indicates that the impurity concentration is relatively high compared to any mark without "+" and "-", and a mark with "-" indicates that the impurity concentration is relatively low compared to any mark without "+" and "-". A mark with two "-"s ("--") indicates that the impurity concentration is relatively low compared to a mark with only one "-". In the case where each region contains both p-type impurities and n-type impurities, these marks indicate the relative level of the net impurity concentration after these impurities compensate for each other. With respect to each embodiment described below, each embodiment can be implemented by reversing the p-type (second conductivity type) and n-type (first conductivity type) of each semiconductor region.

[0018] (First embodiment)

[0019] Figure 1 It is a schematic plan view illustrating a semiconductor device according to an embodiment.

[0020] Figure 2 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0021] Figure 2 exemplify Figure 1 The cross section at line A1-A2 is shown. Figure 1 In order to explain the positional relationship between the third semiconductor region 23 and the fourth semiconductor region 24, a part of the structure of the semiconductor device 100 is omitted.

[0022] The semiconductor device involved in the embodiment is, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Figure 2 As shown, the semiconductor device 100 includes a drain electrode (first electrode 11), n + type drain region (first semiconductor region 21), n －－ type semiconductor region (second semiconductor region 22), a plurality of p － The column region (third semiconductor region 23), a plurality of n － a p-type column region (fourth semiconductor region 24), a plurality of p-type base regions (fifth semiconductor region 25), a plurality of n + type source region (sixth semiconductor region 26), a plurality of p + type contact region (seventh semiconductor region 27 ), a source electrode (second electrode 12 ), a plurality of gate electrodes 13 and a plurality of insulating portions 30 .

[0023] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the first electrode 11 toward the first semiconductor region 21 is set as the Z direction (first direction). Two directions perpendicular to the Z direction and orthogonal to each other are set as the X direction (second direction) and the Y direction (third direction). In addition, for the sake of description, the direction from the first electrode 11 toward the first semiconductor region 21 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the first electrode 11 and the first semiconductor region 21, and have nothing to do with the direction of gravity.

[0024] The semiconductor device 100 includes an element region R1 and an end region R2. The element region R1 is a region including the fifth semiconductor region 25 and the sixth semiconductor region 26 and forming semiconductor elements such as transistors. The end region R2 is a region located outside the semiconductor substrate S where the semiconductor regions are formed relative to the element region R1. Figure 1As shown, the end region R2 surrounds the device region R1 in the XY plane.

[0025] like Figure 2 As shown, the first electrode 11 is provided in the element region R1 and the terminal region R2. The first semiconductor region 21 is provided on the first electrode 11 in the element region R1 and the terminal region R2. The first semiconductor region 21 is in contact with the upper surface of the first electrode 11 and is electrically connected to the first electrode 11. The first semiconductor region 21 is n-type.

[0026] The second semiconductor region 22 is provided on the first semiconductor region 21 in the element region R1 and the terminal region R2. The second semiconductor region 22 is in contact with the upper surface of the first semiconductor region 21 and is electrically connected to the first semiconductor region 21. For example, the second semiconductor region 22 is a semiconductor layer formed by epitaxial growth on the first semiconductor region 21. The second semiconductor region 22 is n-type. The n-type impurity concentration (atoms / cm 3 ) is greater than the n-type impurity concentration (atoms / cm 3 )Low.

[0027] The second semiconductor region 22 includes a first portion 22a and a plurality of second portions 22b. The first portion 22a and the second portion 22b are respectively arranged in the element region R1 and the terminal region R2. For example, the first portion 22a is a portion of the second semiconductor region 22 located below the third semiconductor region 23. The second portion 22b is a portion provided on a portion (portion a1) of the first portion 22a.

[0028] The n-type impurity concentration in the second portion 22b (atoms / cm 3 ) and the n-type impurity concentration (atoms / cm 3 As an example, the n-type impurity concentration in the second semiconductor region 22 is 1×10 13 (atoms / cm 3 ) or more and 1×10 15 (atoms / cm 3 ) or less, preferably 8×10 14 (atoms / cm 3 )the following.

[0029] A plurality of third semiconductor regions 23 are arranged in the element region R1 and the terminal region R2. A plurality of third semiconductor regions 23 are arranged in the X direction, and each third semiconductor region 23 extends in the Y direction. The third semiconductor region 23 is provided on another portion (portion a2) of the first portion 22a. The third semiconductor region 23 is arranged with the second portion 22b in the X direction. The third semiconductor region 23 is in contact with the upper surface of a portion (portion a2) of the first portion 22a, and is in contact with the side surface of the second portion 22b. Figure 2 The distance L23 shown (the distance along the Z direction between the lower end of the third semiconductor region 23 and the first semiconductor region 21 ) is shorter than the distance D23 (the distance along the Z direction between the lower end of the third semiconductor region 23 and the upper surface Sf of the semiconductor substrate S).

[0030] The third semiconductor region 23 is of p-type. For example, the p-type impurity concentration (atoms / cm 3 ) is greater than the n-type impurity concentration (atoms / cm 3 As an example, the p-type impurity concentration in the third semiconductor region 23 can be set to 1×10 15 (atoms / cm 3 ) and above 5×10 16 (atoms / cm 3 )the following.

[0031] For example, in the element region R1 and the terminal region R2, the p-type impurity concentration (e.g., peak concentration) in the plurality of third semiconductor regions 23 is the same. For example, in the element region R1 and the terminal region R2, the widths W1 in the X direction of the plurality of third semiconductor regions 23 are the same. For example, in the element region R1 and the terminal region R2, the positions in the Z direction of the lower ends of the plurality of third semiconductor regions 23 are the same.

[0032] For example, in the device region R1, the pitch P23 of the plurality of third semiconductor regions 23 is a constant pitch P230. In other words, in the device region R1, the plurality of third semiconductor regions 23 are arranged at equal intervals in the X direction.

[0033] In addition, in the present application, the pitch refers to the distance between the centers of two adjacent elements in the X direction. For example, the pitch of the third semiconductor regions 23 is the distance between the center of one third semiconductor region 23 in the X direction and the center of the third semiconductor region 23 adjacent to the third semiconductor region 23 in the X direction.

[0034] The pitch P23 of the third semiconductor region 23 in the terminal region R2 increases as the distance from the element region R1 increases in the X direction. Figure 2 In the example shown, the pitch P232 between the region 232 and the region 233 is longer than the pitch P231 between the region 231 and the region 232. In addition, the pitch P233 between the region 234 and the region 233 is longer than the pitch P232. In addition, each of the regions 231 to 234 is one of the third semiconductor regions 23. The region 233 is located between the element region R1 and the region 234. The region 232 is located between the element region R1 and the region 233. The region 231 is located between the element region R1 and the region 232.

[0035] A plurality of fourth semiconductor regions 24 are arranged in the element region R1 and the terminal region R2. The plurality of fourth semiconductor regions 24 are arranged in the X direction, and each of the fourth semiconductor regions 24 extends in the Y direction. At least a portion of the fourth semiconductor region 24 is arranged with the third semiconductor region 23 in the X direction. The plurality of fourth semiconductor regions 24 and the plurality of third semiconductor regions 23 are arranged alternately in the X direction. The second portion 22b of the second semiconductor region 22 is located between the third semiconductor region 23 and the fourth semiconductor region 24. Therefore, the fourth semiconductor region 24 is separated from the third semiconductor region 23 in the X direction via the second portion 22b, and does not contact the third semiconductor region 23. For example, each of the fourth semiconductor regions 24 is arranged at the center of the third semiconductor region 23 in the X direction.

[0036] The fourth semiconductor region 24 is provided on a portion (portion a3) of the second semiconductor region 22. The fourth semiconductor region 24 is in contact with the upper surface of the portion a3 and in contact with the side surface of the second portion 22b. Figure 2 The distance L24 shown (the distance between the lower end of the fourth semiconductor region 24 and the first semiconductor region 21 along the Z direction) is shorter than the distance D24 (the distance between the lower end of the fourth semiconductor region 24 and the upper surface Sf of the semiconductor substrate S along the Z direction).

[0037] The fourth semiconductor region 24 is of n-type. The n-type impurity concentration (atoms / cm 3 ) is higher than the n-type impurity concentration of the second semiconductor region 22 (the first portion 22a and the second portion 22b). The n-type impurity concentration of the fourth semiconductor region 24 is lower than the n-type impurity concentration of the first semiconductor region 21. As an example, the n-type impurity concentration of the fourth semiconductor region 24 can be set to 1×10 15 (atoms / cm 3 ) and above 5×10 16 (atoms / cm 3 )the following.

[0038] For example, in the element region R1 and the terminal region R2, the n-type impurity concentrations (e.g., peak concentrations) in the plurality of fourth semiconductor regions 24 are the same. For example, in the element region R1 and the terminal region R2, the widths W2 in the X direction of the plurality of fourth semiconductor regions 24 are the same. For example, in the element region R1 and the terminal region R2, the positions in the Z direction of the lower ends of the plurality of fourth semiconductor regions 24 are the same. The width W2 of the fourth semiconductor region 24 may be the same as the width W1 of the third semiconductor region. Alternatively, the width W2 of the fourth semiconductor region 24 may be shorter than the width W1 of the third semiconductor region, or longer than the width W1 of the third semiconductor region.

[0039] As described above, a structure in which one second portion 22b, the third semiconductor region 23, another second portion 22b, and the fourth semiconductor region 24 are arranged in sequence along the X direction is repeatedly provided. In other words, two second portions 22b are provided between two adjacent third semiconductor regions 23, and one fourth semiconductor region 24 is provided between the two second portions 22b. A superjunction structure (SJ structure) in which pn junctions are repeatedly provided in the X direction is formed by the p-type third semiconductor region 23 and the n-type second semiconductor region 22 and the fourth semiconductor region 24.

[0040] In addition, if Figure 2 As shown, the width W1 of the third semiconductor region 23 in the element region R1 in the X direction may be shorter than the distance L2 between the third semiconductor regions 23 adjacent to each other in the element region R1. This is not limited to this, and for example, the width W1 may be the same as the distance L2. In the element region R1, for example, adjustment is made so that the total amount of n-type impurities and the total amount of p-type impurities contained in the n-type region (one fourth semiconductor region 24 and two second portions 22b) between two third semiconductor regions 23 and one third semiconductor region 23 adjacent to the n-type region become approximately the same. The peak concentration (atoms / cm 3 ) can be the peak concentration (atoms / cm 3 Alternatively, the peak concentration of p-type impurities in the third semiconductor region 23 (atoms / cm 3 ) can be the peak concentration (atoms / cm 3 )the following.

[0041] The fifth semiconductor region 25 is provided on one third semiconductor region 23 in the element region R1 and is electrically connected to the third semiconductor region 23. A plurality of fifth semiconductor regions 25 are arranged in the X direction, and each fifth semiconductor region 25 extends in the Y direction. The fifth semiconductor region 25 is p-type, and the p-type impurity concentration of the fifth semiconductor region 25 is higher than the p-type impurity concentration of the third semiconductor region 23. A portion of the fourth semiconductor region 24 (or the second semiconductor region 22) is arranged between two adjacent fifth semiconductor regions 25.

[0042] The sixth semiconductor region 26 is provided on a portion of the fifth semiconductor region 25 in the element region R1. A plurality of sixth semiconductor regions 26 are arranged in the X direction, and each sixth semiconductor region 26 extends in the Y direction. The sixth semiconductor region is n-type, and the n-type impurity concentration of the sixth semiconductor region 26 is higher than the n-type impurity concentration of the fourth semiconductor region 24. The sixth semiconductor region 26 is separated from the second portion 22b via a portion of the fifth semiconductor region 25. A portion of the fifth semiconductor region 25 (a portion including the region 25a where the channel is formed) is located between the sixth semiconductor region 26 and the n-type region (the fourth semiconductor region 24 or the second semiconductor region 22).

[0043] In this example, two sixth semiconductor regions 26 are provided on one fifth semiconductor region 25. The seventh semiconductor region 27 is provided on the fifth semiconductor region 25 between the two sixth semiconductor regions 26. The seventh semiconductor region 27 is p-type, and the p-type impurity concentration of the seventh semiconductor region 27 is higher than the p-type impurity concentration of the fifth semiconductor region 25.

[0044] A plurality of gate electrodes 13 and a gate insulating layer 31 are provided in the element region R1. The plurality of gate electrodes 13 are arranged in the X direction, and each gate electrode 13 extends in the Y direction. The gate electrode 13 is opposite to the fifth semiconductor region 25 via the gate insulating layer 31. More specifically, the gate electrode 13 is located on the region 25a, a portion of the sixth semiconductor region 26 adjacent to the region 25a, and a portion of the n-type region adjacent to the region 25a. The gate insulating layer 31 is located between the gate electrode 13 and the region 25a (and the portion of the sixth semiconductor region 26, and the portion of the n-type region).

[0045] The second electrode 12 is provided in the element region R1. The second electrode 12 is provided on the fifth semiconductor region 25 (on the seventh semiconductor region 27) and on the sixth semiconductor region 26. The second electrode 12 is in contact with the sixth semiconductor region 26 and is electrically connected to the sixth semiconductor region 26. The second electrode 12 is in contact with the seventh semiconductor region 27 and is electrically connected to the fifth semiconductor region 25 via the seventh semiconductor region 27.

[0046] In addition, if Figure 2 As shown, in the terminal region R2, an insulating layer 33, an insulating layer 34 and a plurality of conductive portions 16 are provided on the semiconductor substrate S. The insulating layer 33 is provided on the plurality of third semiconductor regions 23 and the second semiconductor region 22 (and the fourth semiconductor region 24) arranged in the terminal region R2. The plurality of conductive portions 16 are arranged in the X direction on the insulating layer 33, and each conductive portion 16 extends in the Y direction. Each conductive portion 16 is located above the bonding interface between the third semiconductor region 23 and the second semiconductor region 22 via the insulating layer 33. The conductive portion 16 is, for example, a field plate electrode. The potential of the conductive portion 16 is, for example, floating. By providing the field plate electrode, for example, the electric field strength at the bonding interface between the third semiconductor region 23 and the second semiconductor region 22 is suppressed. In addition, for example, the depletion layer of the terminal region R2 is suppressed from reaching the periphery of the terminal region R2. The insulating layer 34 is provided on the insulating layer 33 and the conductive portion 16 to cover the insulating layer 33 and the conductive portion 16.

[0047] An example of the material of each component is described.

[0048] The first semiconductor region 21, the second semiconductor region 22, the third semiconductor region 23, the fourth semiconductor region 24, the fifth semiconductor region 25, the sixth semiconductor region 26, and the seventh semiconductor region 27 include silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity.

[0049] The gate electrode 13 and the conductive portion 16 include conductive materials such as polysilicon. Impurities may be added to the conductive material. The gate insulating layer 31, the insulating portion 30, the insulating layer 33 and the insulating layer 34 include insulating materials such as silicon oxide and silicon nitride. The first electrode 11 and the second electrode 12 include metals such as aluminum and titanium.

[0050] The operation of the semiconductor device 100 will be described.

[0051] For example, a positive voltage with respect to the second electrode 12 is applied to the first electrode 11. In this state, if a voltage greater than a threshold value is applied to the gate electrode 13, an n-type inversion layer is formed in the fifth semiconductor region 25 (region 25a). As a result, an on-state is obtained in which electrons flow from the second electrode 12 to the first electrode 11 via the sixth semiconductor region 26, the fifth semiconductor region 25 (region 25a), the second semiconductor region 22, and the first semiconductor region 21. If the voltage applied to the gate electrode 13 becomes less than the threshold value, an n-type inversion layer is not formed in the fifth semiconductor region 25 (region 25a), and an off-state is obtained in which electrons do not substantially flow from the second electrode 12 to the first electrode 11. When the MOSFET is in the off state and a positive voltage with respect to the second electrode 12 is applied to the first electrode 11, a depletion layer expands from the pn junction surface between the second semiconductor region 22 (second portion 22b) and the third semiconductor region 23 to the second semiconductor region 22 and the third semiconductor region 23. This suppresses electric field concentration and achieves a high withstand voltage.

[0052] Next, an example of a method for manufacturing the semiconductor device according to the embodiment will be described. Figure 3 (a) Figure 3 (b) Figure 4 (a) Figure 4 (b) Figure 5 (a) Figure 5 (b) Figure 6 (a) and Figure 6 (b) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0053] First, an n-type semiconductor substrate is prepared to be the first semiconductor region 21. The second semiconductor region 22 is epitaxially grown on the n-type semiconductor substrate (first semiconductor region 21). Figure 3 As shown in (a), a first trench T1 is formed on the upper surface 22t of the second semiconductor region 22. For example, by reactive ion etching (RIE), a portion of the second semiconductor region 22 is removed from the upper surface 22t side. A plurality of first trenches T1 are arranged in the X direction, and each first trench T1 extends in the Y direction. A portion of the second semiconductor region 22 located below the lower end of the first trench T1 corresponds to the first portion 22a.

[0054] Then, if Figure 3 As shown in (b), the third semiconductor region 23 is formed in the first trench T1. For example, a p-type semiconductor layer to be the third semiconductor region 23 is epitaxially grown in each first trench T1. The upper surface of the p-type semiconductor layer is polished and flattened, and the position of the upper surface is retreated. Figure 3As shown in (b) , the third semiconductor region 23 is buried in the first trench T1 .

[0055] In this way, the third semiconductor region 23 is formed corresponding to the first trench T1 . Therefore, the relationship between the width and pitch of the first trench T1 and the relationship between the width and pitch of the third semiconductor region 23 are the same.

[0056] That is, for example Figure 3 As shown in (a), in the range of the element region R1, the pitch PT1 of the plurality of first trenches T1 is a constant pitch PT10. On the other hand, in the range of the end region R2, the pitch PT1 of the first trenches T1 becomes longer as it is farther from the element region R1 in the X direction. More specifically, Figure 3 In the example shown in (a), the spacing PT12 between the groove portion T12 and the groove portion T13 is longer than the spacing PT11 between the groove portion T11 and the groove portion T12. In addition, the spacing PT13 between the groove portion T14 and the groove portion T13 is longer than the spacing PT12. In addition, the groove portions T11 to T14 are each one of the first grooves T1. The groove portion T13 is located between the element region R1 and the groove portion T14. The groove portion T12 is located between the element region R1 and the groove portion T13. The groove portion T11 is located between the element region R1 and the groove portion T12. In addition, the width (length along the X direction) of the first groove T1 is constant.

[0057] like Figure 4 As shown in (a), a second trench T2 is formed on the upper surface 22t of the second semiconductor region 22. For example, by reactive ion etching, a portion of the second semiconductor region 22 is removed from the upper surface 22t side. A plurality of second trenches T2 are arranged in the X direction, and each second trench T2 extends in the Y direction. The second trench T2 is arranged to be located between two adjacent first trenches T1. That is, the plurality of second trenches T2 are arranged alternately in the X direction with the positions where the plurality of first trenches T1 are arranged. A portion between the first trench T1 and the second trench T2 in the second semiconductor region 22 corresponds to the second portion 22b. The second trench T2 can penetrate the second semiconductor region 22.

[0058] Then, if Figure 4 As shown in (b), the fourth semiconductor region 24 is formed in the second trench T2. For example, an n-type semiconductor layer to be the fourth semiconductor region 24 is epitaxially grown in each second trench T2. The upper surface of the n-type semiconductor layer is polished and flattened, and the position of the upper surface is retreated. Figure 4 As shown in (b) , the fourth semiconductor region 24 is buried in the second trench T2.

[0059] Thus, the fourth semiconductor region 24 is formed corresponding to the second trench T2. Therefore, the relationship between the width and pitch of the second trench T2 is the same as the relationship between the width and pitch of the fourth semiconductor region 24. Figure 4 As shown in (a) of FIG. 1 , in the range to be the device region R1 , the pitch PT2 of the plurality of second trenches T2 is a constant pitch PT20 .

[0060] On the other hand, in the range of the end region R2, the pitch PT1 of the second trench T2 becomes longer as it is farther away from the element region R1 in the X direction. In addition, the width (length along the X direction) of the second trench T2 is constant. The width of the second trench T2 may be the same as the width of the first trench T1. Alternatively, the width of the second trench T2 may be longer or shorter than the width of the first trench T1.

[0061] Then, if Figure 5 As shown in (a), an insulating layer serving as the insulating layer 33 is formed on the upper surfaces of the second semiconductor region 22, the third semiconductor region 23, and the fourth semiconductor region 24 by, for example, chemical vapor deposition (CVD). An opening is provided in the portion of the insulating layer serving as the element region R1 by, for example, RIE. Furthermore, in the range serving as the element region R1, an insulating layer 31a serving as the gate insulating layer 31 is formed by, for example, thermal oxidation.

[0062] like Figure 5 As shown in (b), a conductive material (polysilicon) is deposited on the insulating layer 33 and the insulating layer 31a by, for example, CVD to form a conductive layer. The conductive layer is patterned to form the gate electrode 13 and the conductive portion 16.

[0063] Then, for example, polysilicon is oxidized to form Figure 6 The interlayer film shown in (a) becomes the insulating layer 34. The interlayer film covers the insulating layer 33, the conductive portion 16, and the gate electrode 13. After forming a resist on the interlayer film, an opening is formed in the portion of the resist located above the gate electrodes 13 by photolithography, and the interlayer film is processed by RIE. Thus, an opening OP is formed between the gate electrodes 13. The opening OP penetrates the insulating layer 31a and the interlayer film (insulating layer 30a). Around the gate electrode 13, the second semiconductor region 22 and the fourth semiconductor region 24 are covered by the insulating layers 31a and 30a.

[0064] The p-type impurity ions are implanted into the upper surface of the third semiconductor region 23 provided in the element region R1 through the opening OP, thereby forming the fifth semiconductor region 25. Furthermore, the n-type impurity and the p-type impurity are implanted into the upper surface of the fifth semiconductor region 25 in sequence, thereby forming the sixth semiconductor region 26 and the seventh semiconductor region 27.

[0065] like Figure 6 As shown in (b), a metal layer is formed by sputtering so as to cover the insulating layer 30a. The metal layer is patterned to form the second electrode 12 in the device region R1.

[0066] Then, the back surface of the first semiconductor region 21 is polished as necessary. On the back surface of the first semiconductor region 21, the first electrode 11 is formed by sputtering.

[0067] Through the above steps, the semiconductor device 100 involved in the embodiment is manufactured. In addition, the order of the above steps can be appropriately changed within a possible range. For example, the order of forming the first trench T1 and the second trench T2 and burying them can be opposite to the above. For example, the fifth semiconductor region 25, the sixth semiconductor region 26 and the seventh semiconductor region 27 can be formed before forming the gate insulating layer 31 and the gate electrode 13.

[0068] The effects of the embodiment will be described.

[0069] In the semiconductor device 100 according to the embodiment, the second portion 22b of the n-type second semiconductor region 22 having a relatively low impurity concentration is arranged between the n-type fourth semiconductor region 24 having a relatively high impurity concentration and the p-type third semiconductor region 23. That is, the n-type semiconductor region having a high impurity concentration is prevented from directly contacting the p-type semiconductor region having a high impurity concentration. Therefore, it is possible to prevent the electric field strength at the pn junction from increasing, thereby improving the withstand voltage of the semiconductor device.

[0070] In the SJ structure, for example, from the perspective of maintaining the withstand voltage, in the element region, the amount of p-type semiconductor impurities is set to be consistent with the amount of n-type semiconductor impurities. Here, for example, in the SJ structure of the reference example in which the n-type column and the p-type column are alternately arranged in contact with each other, the balance of impurity concentration is adjusted by the impurity concentration in the n-type column and the impurity concentration in the p-type column. In such a reference example SJ structure, the p-type semiconductor region with a high impurity concentration is close to the n-type semiconductor region, so the amount of p-type impurities and n-type impurities that cancel each other out becomes more. In such a case, if the balance of the impurity amount in the element region changes, the withstand voltage is sometimes greatly deteriorated. In contrast, in the embodiment, the impurity concentration and width of the fourth semiconductor region 24 (n-type column), the third semiconductor region 23 (p-type column) and the second part 22b can be changed. Since the adjustable parameters increase, the degree of freedom of design is improved.

[0071] Furthermore, in the embodiment, the pitch P23 of the third semiconductor region 23 in the terminal region R2 is longer as it is farther away from the element region R1. Therefore, in the terminal region R2, the amount of n-type impurities becomes relatively more as it moves toward the outside. In this case, the depletion layer extending from the element region R1 toward the periphery of the terminal region R2 is suppressed from extending to the outermost third semiconductor region 23. Thus, the increase in the electric field strength in the outermost region of the terminal region R2 is suppressed. The degradation of the withstand voltage in the terminal region R2 can be suppressed, and the degradation of the withstand voltage of the semiconductor device 100 can be suppressed. Refer to Figure 7 (a)~ Figure 7 (d) explains this.

[0072] Figure 7 (a)~ Figure 7 (d) is a schematic cross-sectional view illustrating a simulation of characteristics of a semiconductor device.

[0073] Figure 7 (a) is a schematic cross-sectional view of a semiconductor device 190 used in the simulation. Figure 7 As shown in (a), in the semiconductor device 190, a plurality of third semiconductor regions 23 are arranged in the X direction in the n-type second semiconductor region 22. In the semiconductor device 190, the pitch of the third semiconductor regions 23 is constant in the element region R1 and the terminal region R2. Figure 7 (b) shows the distribution of the impact ionization rate when a positive voltage is applied to the drain side of the semiconductor device 190 in the off state.

[0074] Figure 7 (c) is a schematic cross-sectional view of the semiconductor device 110 used in the simulation. Figure 7 As shown in (c), in the semiconductor device 110, a plurality of third semiconductor regions 23 are also arranged in the X direction in the n-type second semiconductor region 22. In the semiconductor device 110, the pitch of the third semiconductor regions 23 in the element region R1 is constant, and the pitch of the third semiconductor regions 23 in the terminal region R2 becomes longer as they are farther away from the element region R1. More specifically, the pitch of the third semiconductor regions 23 becomes longer in units of 1.02 times as they are separated from the element region R1. Figure 7 (d) shows the distribution of the impact ionization rate when a positive voltage is applied to the drain side of the semiconductor device 110 in the off state.

[0075] In the cross-sectional view showing the impact ionization rate, the lighter (whiter) region in the semiconductor substrate S indicates a higher impact ionization rate. Figure 7In the semiconductor device 190 shown in (b), the impact ionization rate is high in the region R10 around the outermost third semiconductor region 23. It can be considered that if the depletion reaches the outermost third semiconductor region 23, the electric field strength becomes higher at its periphery and the impact ionization rate becomes higher. In this way, if the depletion layer expands to the outside of the terminal region R2, the electric field on the outer peripheral side of the terminal region R2 is enhanced. In this case, the withstand voltage of the terminal region R2 is sometimes degraded, and the withstand voltage of the semiconductor device is degraded.

[0076] On the other hand, Figure 7 In the semiconductor device 110 shown in (d), in the region R11 around the third semiconductor region 23 arranged on the inner side in the terminal region R2, the electric field is strong and the impact ionization rate is high. In the semiconductor device 110, the extension of the depletion layer to the outside of the terminal region R2 can be suppressed, and the electric field enhancement on the outer peripheral side of the terminal region R2 can be suppressed. Thus, for example, the degradation of the withstand voltage of the semiconductor device can be suppressed. In addition, for example, when the depletion layer does not extend to the outer peripheral side of the terminal region R2, the structure of the part on the outer peripheral side of the terminal region R2 can also be omitted. Thus, the semiconductor device can be miniaturized.

[0077] In the embodiment, for example, the pitch in the end region R2 of the plurality of third semiconductor regions 23 increases at a predetermined ratio as the distance from the device region R1 in the X direction increases. Figure 2 In the example, the ratio of the pitch P232 to the pitch P231 is a predetermined first ratio, and the ratio of the pitch P232 to the pitch P233 is the first ratio. The first ratio is greater than 1, for example, 1.01 to 1.03. Alternatively, for example, the pitch in the end region R2 of the plurality of third semiconductor regions 23 increases by a predetermined length each time as they are separated from the element region R1 in the X direction. That is, for example, Figure 2 In the example, the pitch P232 may be longer than the pitch P231 by a predetermined first length, and the pitch P233 may be longer than the pitch P232 by the first length. As described above, the pitch of the third semiconductor region 23 gradually increases, thereby suppressing a sharp change in the electric field intensity in the X direction.

[0078] For example, by making the spacing of the third semiconductor regions 23 in the element region R1 constant, the balance between the amount of n-type impurities and the amount of p-type impurities in the element region R1 is adjusted. Moreover, the spacing in the end region R2 of the third semiconductor region 23 is longer than the spacing in the element region R1 of the third semiconductor region 23. In addition, for example, the width W1 of the third semiconductor region 23 in the end region R2 in the X direction is greater than the distance L1 (see FIG. 1 ) between the third semiconductor regions 23 adjacent to each other in the end region R2. Figure 2) is short. The amount of n-type impurities increases as it moves toward the outside in the terminal region R2, and the expansion of the depletion layer to the outside in the terminal region R2 is suppressed. In addition, for example, the spacing of the third semiconductor region 23 at the innermost side (on the element region R1 side) of the terminal region R2 can be the same as the spacing of the third semiconductor region 23 in the element region R1.

[0079] For example, similarly to the plurality of third semiconductor regions 23, the pitch in the end region R2 of the plurality of fourth semiconductor regions 24 may be lengthened by a predetermined ratio as the region is separated from the element region R1 in the X direction. Alternatively, similarly to the plurality of third semiconductor regions 23, the pitch in the end region R2 of the plurality of fourth semiconductor regions 24 may be lengthened by a predetermined length each time the region is separated from the element region R1 in the X direction.

[0080] exist Figure 2 In the example shown, the distance D24 is the same as the distance D23. Figure 3 and Figure 4 The depth of the first trench T1 described above is the same as the depth of the second trench T2. This is not limiting, and for example, the distance D24 may be longer than the distance D23. When the fourth semiconductor region 24 is long in the Z direction, for example, the on-resistance can be reduced.

[0081] Embodiments may include the following structures.

[0082] (Structure 1)

[0083] A semiconductor device comprises a device region and a terminal region surrounding the device region.

[0084] The semiconductor device has:

[0085] A first electrode, disposed in the element region and the terminal region;

[0086] a first semiconductor region of a first conductivity type, disposed on the first electrode;

[0087] a second semiconductor region of the first conductivity type, provided on the first semiconductor region, having a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the first semiconductor region, and comprising a first portion and a plurality of second portions provided on a portion of the first portion;

[0088] A plurality of third semiconductor regions of the second conductivity type are provided on another portion of the first portion and are arranged in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, and the distance between the plurality of third semiconductor regions in the end region increases as they are farther away from the element region in the second direction;

[0089] a plurality of fourth semiconductor regions of the first conductivity type, separated from the third semiconductor region via the second portion in the second direction, arranged alternately with the plurality of third semiconductor regions in the second direction, and having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region;

[0090] a fifth semiconductor region of the second conductivity type, provided on the third semiconductor region in the element region;

[0091] a sixth semiconductor region of the first conductivity type, provided on the fifth semiconductor region and separated from the second portion via a portion of the fifth semiconductor region;

[0092] a gate electrode facing the portion of the fifth semiconductor region via a gate insulating layer; and

[0093] The second electrode is provided on the fifth semiconductor region and the sixth semiconductor region and is electrically connected to the fifth semiconductor region and the sixth semiconductor region.

[0094] (Structure 2)

[0095] The semiconductor device according to Structure 1, wherein:

[0096] A pitch between the plurality of third semiconductor regions in the terminal region increases at a predetermined ratio as the distance from the device region increases in the second direction.

[0097] (Structure 3)

[0098] The semiconductor device according to Structure 1, wherein:

[0099] The pitch between the plurality of third semiconductor regions in the terminal region increases by a predetermined length each time the third semiconductor regions are spaced apart from the device region in the second direction.

[0100] (Structure 4)

[0101] A semiconductor device as described in any one of Structures 1 to 3, wherein:

[0102] The plurality of third semiconductor regions are spaced at a constant interval in the device region.

[0103] (Structure 5)

[0104] A semiconductor device as described in any one of Structures 1 to 4, wherein:

[0105] A pitch between the plurality of third semiconductor regions in the terminal region is longer than a pitch between the plurality of third semiconductor regions in the element region.

[0106] (Structure 6)

[0107] A semiconductor device as described in any one of Structures 1 to 5, wherein:

[0108] In the element region, a width of the third semiconductor region in the second direction is shorter than a distance between adjacent third semiconductor regions.

[0109] (Structure 7)

[0110] A semiconductor device as described in any one of Structures 1 to 6, wherein

[0111] In the element region, a width of the third semiconductor region in the second direction is shorter than a distance between adjacent third semiconductor regions.

[0112] (Structure 8)

[0113] A semiconductor device as described in any one of Structures 1 to 6, wherein

[0114] In the device region, a width of the third semiconductor region in the second direction is equal to a distance between adjacent third semiconductor regions.

[0115] (Structure 9)

[0116] A semiconductor device as described in any one of Structures 1 to 8, wherein

[0117] The second conductivity type impurity concentration in the third semiconductor region is higher than the first conductivity type impurity concentration in the second semiconductor region.

[0118] (Structure 10)

[0119] A method for manufacturing a semiconductor device, comprising a device region and a terminal region surrounding the device region.

[0120] The method for manufacturing a semiconductor device comprises the following steps:

[0121] A step of forming a plurality of first trenches on an upper surface of a second semiconductor region, wherein the second semiconductor region is provided on a first semiconductor region of a first conductivity type, has a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the first semiconductor region, and is disposed in the element region and the terminal region, wherein the plurality of first trenches are arranged in a second direction perpendicular to the first direction toward the first semiconductor region, and the distance between the plurality of first trenches in the terminal region becomes longer as the distance from the element region in the second direction increases;

[0122] forming a plurality of third semiconductor regions of the second conductivity type in the plurality of first trenches, wherein the plurality of third semiconductor regions of the second conductivity type have a second conductivity type impurity concentration higher than a first conductivity type impurity concentration in the second semiconductor region;

[0123] A step of forming a plurality of second trenches on the upper surface of the second semiconductor region, wherein the plurality of second trenches are arranged alternately with positions where the plurality of first trenches are provided in the second direction and are separated from the first trenches in the second direction;

[0124] forming a plurality of fourth semiconductor regions of the first conductivity type in the plurality of second trenches, wherein the plurality of fourth semiconductor regions of the first conductivity type have a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region;

[0125] forming a gate insulating layer and a gate electrode above the second semiconductor region in the element region;

[0126] forming a fifth semiconductor region of the second conductivity type on the third semiconductor region in the element region, wherein a portion of the fifth semiconductor region of the second conductivity type faces the gate electrode via the gate insulating layer;

[0127] forming a sixth semiconductor region of the first conductivity type on the fifth semiconductor region, the sixth semiconductor region of the first conductivity type being adjacent to the portion of the fifth semiconductor region and separated from the second semiconductor region; and

[0128] A step of forming a first electrode electrically connected to the first semiconductor region and a second electrode electrically connected to the fifth semiconductor region and the sixth semiconductor region.

[0129] According to the embodiment, it is possible to provide a semiconductor device capable of suppressing degradation of withstand voltage and a method for manufacturing the same.

[0130] The relative height of the impurity concentration between each semiconductor region in each embodiment described above can be confirmed using, for example, SCM (scanning electrostatic capacitance microscope). In addition, the carrier concentration in each semiconductor region can be regarded as equal to the impurity concentration activated in each semiconductor region. Therefore, the relative height of the carrier concentration between each semiconductor region can also be confirmed using SCM. The relative height of the impurity concentration between each semiconductor region can be regarded as equivalent to the relative height of the carrier concentration between each semiconductor region. In addition, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (secondary ion mass spectrometry).

[0131] In the present specification, the term “electrically connected” includes not only a case of connection by direct contact but also a case of connection via other conductive members or the like.

[0132] The scope of "a certain element being disposed above other elements" includes not only the case where two such elements are in contact with each other, but also the case where other elements are disposed between the two such elements. For example, the scope of "a certain element being disposed above other elements" has nothing to do with whether the two such elements are in contact with each other (or whether they are continuous), and may include the case where the certain element is located above other elements.

[0133] Several embodiments of the present invention are illustrated above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are included in the invention described in the claims and their equivalents. In addition, the aforementioned embodiments can be combined with each other and implemented.

[0134] Description of Reference Numerals

[0135] 11: 1st electrode

[0136] 12: Second electrode

[0137] 13: Gate electrode

[0138] 15: 5th semiconductor region

[0139] 16: Conductive part

[0140] 21: 1st semiconductor region

[0141] 22: Second semiconductor region

[0142] 22a: Part 1

[0143] 22b: Part 2

[0144] 22t: Upper surface

[0145] 23: The third semiconductor region

[0146] 24: 4th semiconductor region

[0147] 25: 5th semiconductor region

[0148] 25a: Area

[0149] 26: 6th semiconductor region

[0150] 27: 7th semiconductor region

[0151] 30: Insulation

[0152] 30a: Insulation layer

[0153] 31: Gate insulation layer

[0154] 31a: Insulation layer

[0155] 33, 34: Insulation layer

[0156] 100, 110, 190: Semiconductor devices

[0157] 231-234: Area

[0158] D23, D24, L1, L2, L23, L24: Distance

[0159] OP: Opening

[0160] P23, P230~P233: Spacing

[0161] PT1, PT10~PT13: Spacing

[0162] PT2, PT20: Spacing

[0163] R1: Component area

[0164] R2: End zone

[0165] S: Semiconductor substrate

[0166] Sf: upper surface

[0167] T1: Groove 1

[0168] T11~T14: Groove

[0169] T2: Second groove

[0170] W1, W2: Width

[0171] a1~a3: Part

Claims

1. A semiconductor device comprising a device region and a terminal region surrounding the device region, The semiconductor device has: A first electrode, disposed in the element region and the terminal region; a first semiconductor region of a first conductivity type, disposed on the first electrode; a second semiconductor region of the first conductivity type, provided on the first semiconductor region, having a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the first semiconductor region, and comprising a first portion and a plurality of second portions provided on a portion of the first portion; A plurality of third semiconductor regions of the second conductivity type are provided on another portion of the first portion and are arranged in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, and the distance between the plurality of third semiconductor regions in the end region increases as they are farther away from the element region in the second direction; a plurality of fourth semiconductor regions of the first conductivity type, separated from the third semiconductor region via the second portion in the second direction, arranged alternately with the plurality of third semiconductor regions in the second direction, and having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region; a fifth semiconductor region of the second conductivity type, provided on the third semiconductor region in the element region; a sixth semiconductor region of the first conductivity type, provided on the fifth semiconductor region and separated from the second portion via a portion of the fifth semiconductor region; a gate electrode facing the portion of the fifth semiconductor region via a gate insulating layer; as well as The second electrode is provided on the fifth semiconductor region and the sixth semiconductor region and is electrically connected to the fifth semiconductor region and the sixth semiconductor region.

2. The semiconductor device according to claim 1, wherein: A pitch between the plurality of third semiconductor regions in the terminal region increases at a predetermined ratio as the distance from the device region increases in the second direction.

3. The semiconductor device according to claim 1, wherein: The pitch between the plurality of third semiconductor regions in the terminal region increases by a predetermined length as the third semiconductor regions are separated from the device region in the second direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The plurality of third semiconductor regions are spaced at a constant interval in the device region.

5. The semiconductor device according to any one of claims 1 to 3, wherein: A pitch between the plurality of third semiconductor regions in the terminal region is longer than a pitch between the plurality of third semiconductor regions in the element region.

6. The semiconductor device according to any one of claims 1 to 3, wherein: In the device region, a width of the third semiconductor region in the second direction is shorter than a distance between adjacent third semiconductor regions.

7. The semiconductor device according to any one of claims 1 to 3, wherein: In the device region, a width of the third semiconductor region in the second direction is equal to a distance between adjacent third semiconductor regions.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The second conductivity type impurity concentration in the third semiconductor region is higher than the first conductivity type impurity concentration in the second semiconductor region.

9. A method for manufacturing a semiconductor device, comprising: a semiconductor device comprising a device region and a terminal region surrounding the device region; The method for manufacturing a semiconductor device comprises the following steps: A step of forming a plurality of first trenches on an upper surface of a second semiconductor region, wherein the second semiconductor region is provided on a first semiconductor region of a first conductivity type, has a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the first semiconductor region, and is disposed in the element region and the terminal region, wherein the plurality of first trenches are arranged in a second direction perpendicular to the first direction toward the first semiconductor region, and the distance between the plurality of first trenches in the terminal region becomes longer as the distance from the element region in the second direction increases; forming a plurality of third semiconductor regions of the second conductivity type in the plurality of first trenches, wherein the plurality of third semiconductor regions of the second conductivity type have a second conductivity type impurity concentration higher than a first conductivity type impurity concentration in the second semiconductor region; A step of forming a plurality of second trenches on the upper surface of the second semiconductor region, wherein the plurality of second trenches are arranged alternately with positions where the plurality of first trenches are provided in the second direction and are separated from the first trenches in the second direction; forming a plurality of fourth semiconductor regions of the first conductivity type in the plurality of second trenches, wherein the plurality of fourth semiconductor regions of the first conductivity type have a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region; forming a gate insulating layer and a gate electrode above the second semiconductor region in the element region; forming a fifth semiconductor region of the second conductivity type on the third semiconductor region in the element region, wherein a portion of the fifth semiconductor region of the second conductivity type faces the gate electrode via the gate insulating layer; forming a sixth semiconductor region of the first conductivity type on the fifth semiconductor region, the sixth semiconductor region of the first conductivity type being adjacent to the portion of the fifth semiconductor region and being separated from the second semiconductor region; as well as A step of forming a first electrode electrically connected to the first semiconductor region and a second electrode electrically connected to the fifth semiconductor region and the sixth semiconductor region.

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