Display device

Abstract

A display device according to an embodiment includes: a substrate; a barrier layer on the substrate and including a trench; a first buffer layer on the barrier layer and disposed along a contour of the trench; a second buffer layer on the first buffer layer and disposed along a contour of the first buffer layer; a semiconductor layer on the second buffer layer and including a channel region overlapping the trench; a gate insulating layer on the semiconductor layer and overlapping the channel region; and a gate electrode on the gate insulating layer and overlapping the channel region, and a thickness of the first buffer layer is thinner than a thickness of the second buffer layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0120460 filed in the Korean Intellectual Property Office on September 11, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] An aspect of an embodiment of the present disclosure relates to a display device. Background Art

[0004] A display device is a device that displays an image, and includes a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a quantum dot light emitting diode (QLED) display, a micro light emitting diode (LED) display, and the like.

[0005] Such a display device includes pixels, and the pixels may include light-emitting elements such as organic light-emitting elements or inorganic light-emitting elements.

[0006] The display device includes a light emitting element and a transistor that controls the amount of current flowing through the light emitting element.

[0007] Recently, as display devices have become higher resolution and dead areas in display devices have decreased, the area where transistors are placed can be reduced.

[0008] Therefore, electrical characteristics of a transistor disposed in a relatively small area may be degraded. Summary of the invention

[0009] According to an aspect of an embodiment of the present disclosure, a display device having improved device reliability (device reliability) is provided. According to another aspect of an embodiment of the present disclosure, a display device including a transistor having improved device characteristics (device characteristics) is provided. According to another aspect of an embodiment of the present disclosure, the device characteristics of the transistor are improved by including a relatively long channel region in a limited area.

[0010] According to another aspect of an embodiment of the present disclosure, step coverage issues and device reliability in transistors including trench and / or fin structures are improved.

[0011] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a barrier layer on the substrate and including a groove; a first buffer layer on the barrier layer and arranged along the contour of the groove; a second buffer layer on the first buffer layer and arranged along the contour of the first buffer layer; a semiconductor layer on the second buffer layer and including a channel region overlapping the groove; a gate insulating layer on the semiconductor layer and overlapping the channel region; and a gate electrode on the gate insulating layer and overlapping the channel region, and the thickness of the first buffer layer is thinner than the thickness of the second buffer layer.

[0012] The trench may include a vertical portion connecting a portion of the barrier layer having the thinnest thickness and a portion of the barrier layer having the thickest thickness, the channel region may have a depth corresponding to the vertical portion of the trench, and the depth of the channel region may be to

[0013] The width of the channel region may be 5 μm or less.

[0014] The first buffer layer may include a material in which the amount of hydrogen emission increases as the stack thickness increases.

[0015] The second buffer layer may include a material in which the amount of hydrogen emission is constant as the stack thickness increases.

[0016] The first buffer layer may include silicon nitride, and the second buffer layer may include silicon oxide.

[0017] The first buffer layer may have to The thickness of the second buffer layer may be to Thickness.

[0018] The thickness of the gate insulating layer can be or greater and or smaller.

[0019] A corner portion of the groove may have a rounded shape.

[0020] The gate insulating layer may include Al 2 O 3 、TiO 2 and HfO 2 at least one of .

[0021] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a barrier layer on the substrate and including a fin structure; a first buffer layer on the barrier layer and arranged along the outline of the fin structure; a second buffer layer on the first buffer layer and arranged along the outline of the first buffer layer; a semiconductor layer on the second buffer layer and including a channel region overlapping with the fin structure; a gate insulating layer on the semiconductor layer and overlapping with the channel region; and a gate electrode on the gate insulating layer and overlapping with the channel region, and the thickness of the first buffer layer is thinner than the thickness of the second buffer layer.

[0022] The fin structure may include a vertical portion connecting a portion of the barrier layer having the thinnest thickness and a portion of the barrier layer having the thickest thickness, the channel region may have a depth corresponding to the vertical portion of the fin structure, and the depth of the channel region may be to

[0023] The width of the channel region may be 5 μm or less.

[0024] The first buffer layer may include a material in which the amount of hydrogen emission increases as the stack thickness increases.

[0025] The second buffer layer may include a material in which the amount of hydrogen emission is constant as the stack thickness increases.

[0026] The first buffer layer may include silicon nitride, and the second buffer layer may include silicon oxide.

[0027] The first buffer layer may have or less, and the second buffer layer may have to Thickness.

[0028] The thickness of the gate insulating layer can be or greater and or smaller.

[0029] A corner portion of the fin structure may have a rounded shape.

[0030] The gate insulating layer may include Al 2 O 3 、TiO 2 and HfO 2 at least one of .

[0031] According to aspects of one or more embodiments, device characteristics of a transistor are improved by securing a relatively long channel region in a limited area.

[0032] According to another aspect of one or more embodiments, a display device having improved device reliability in a transistor including a trench and / or a fin structure is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a plan view of a display device according to an embodiment.

[0034] Figure 2 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0035] Figures 3 to 6 is a cross-sectional view of a display device according to some embodiments.

[0036] Figure 7 is a graph for explaining the relationship between the thickness of a silicon oxide film and the defect rate according to an embodiment.

[0037] Figure 8 is a graph for explaining the amount of hydrogen emission according to the thickness of a gate insulating layer according to an embodiment.

[0038] Fig. 9 is a graph for explaining an amount of hydrogen emission according to a thickness of each buffer layer according to an embodiment.

[0039] Fig.10 and Fig.11 is a circuit diagram of a pixel of a display device according to some embodiments.

[0040] Description of Reference Numerals

[0041] SUB: Substrate; 10BAR: Barrier layer

[0042] BUF: buffer layer BF1: first buffer layer

[0043] BF2: Second buffer layer TCH: Trench

[0044] FIN: Fin ACT: Semiconductor layer

[0045] CA: Channel area GI: Gate insulation layer

[0046] GE: Gate electrode 15V1, V2: Vertical part

[0047] T1, T2, T3, T4, T5, T6, T7: transistors DETAILED DESCRIPTION

[0048] Herein, with reference to the accompanying drawings, various embodiments will be described in further detail so that those skilled in the art can easily realize the present invention.

[0049] However, the present invention may be embodied in many different forms and is not limited to the embodiments set forth herein.

[0050] In order to more clearly illustrate the present invention, parts not related to the description may be omitted, and the same or similar components are given the same reference numerals throughout the specification.

[0051] In addition, the size and thickness of each component shown in the drawings may be arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to what is shown.

[0052] In the drawings, the thickness may be exaggerated to more clearly show or explain various layers and regions. For example, in the drawings, the thickness of some layers and regions may be exaggerated for ease of explanation.

[0053] In addition, when a portion of a layer, film, region or plate is referred to as being "above" or "on" another portion, this includes not only the case where it is directly above the other portion, but also the case where there is another portion or multiple portions between the portion of the layer, film, region and the other portion.

[0054] In contrast, when a part is referred to as being “right on top of” or “directly on top of” another part, this means that there are no other parts between them.

[0055] Additionally, “above” or “on” a reference portion means positioned above or below the reference portion, and does not necessarily mean positioned “above” or “on” the reference portion in a direction opposite to gravity.

[0056] In addition, throughout the specification, when a part is referred to as “comprising” a certain component, this means that it may further include other components rather than excluding other components, unless explicitly stated otherwise.

[0057] In addition, throughout the specification, when “on a plane” is mentioned, this means when the target portion is viewed from above, and when “in a cross section” is mentioned, this means when the cross section of the target portion is cut vertically and viewed from the side.

[0058] Figure 1 is a plan view of a display device according to an embodiment.

[0059] refer to Figure 1 The display device 1000 according to the embodiment may be, for example, an organic light emitting display device, a plasma display device, a field emission display device, a quantum dot display device, a micro LED display device, a liquid crystal display device, or the like.

[0060] In the following description, the description focuses on an example in which the display device 1000 is an organic light emitting display device, but the embodiment is not limited thereto.

[0061] The display device 1000 includes a display area DS including a plurality of pixels PX as a plurality of units capable of displaying an image and a peripheral area PA around the display area DS. The display device 1000 includes a substrate SUB.

[0062] A plurality of pixels PX may be integrally disposed in the display region DS.

[0063] For example, a plurality of pixels PX may be arranged in a matrix form in the display region DS.

[0064] The peripheral area PA includes pixels PX capable of displaying an image and may or may not display an image.

[0065] The substrate SUB may have a surface parallel to the first direction DR1 and a second direction DR2 perpendicular to the first direction DR1 , and a direction perpendicular upward to the surface of the substrate SUB may be formed in the third direction DR3 .

[0066] A plurality of signal lines or a plurality of voltage lines that are electrically connected to the pixels PX and that may apply a signal or a driving voltage may be positioned in the display region DS.

[0067] The plurality of signal lines or the plurality of voltage lines may include a plurality of scan lines 151 that may transmit scan signals to the pixels PX, a plurality of data lines 171 that may transmit data signals to the pixels PX, and a plurality of driving voltage lines 172 that may transmit driving voltages to the pixels PX.

[0068] Each pixel PX may include at least one driving element (eg, a transistor, etc.), a light emitting element (eg, an organic light emitting diode, etc.), and a capacitor connected to the driving element.

[0069] The light emitting element may emit light by receiving a signal from the driving device.

[0070] In an embodiment, the first scan line 151 may extend substantially in the first direction DR1 across the display area DS, and the driving voltage line 172 and the data line 171 may extend substantially in the second direction DR2.

[0071] In the peripheral area PA, a scan driver 400 that may supply a scan signal connected to the plurality of scan lines 151 , a data driver 500 that may supply a data signal connected to the plurality of data lines 171 , and the like may be positioned.

[0072] The scan driver 400 may include transistors directly formed on the substrate together with transistors positioned in the display area DS.

[0073] Figure 1An example is shown in which the scan driver 400 is positioned at the left and right sides of the display area DS, but according to an embodiment, the scan driver 400 may be positioned only at one side of the display area DS.

[0074] In an embodiment, the data driver 500 may be formed as an integrated circuit and may be mounted on a substrate SUB or on a circuit board connected to the substrate SUB.

[0075] The data driver 500 may apply a driving voltage to the driving voltage line 172 .

[0076] Figure 2 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0077] The pixel PX of the display device may include a pixel circuit portion including a plurality of transistors T1 , T2 , T3 and a storage capacitor Cst, and at least one light emitting element LED connected to the pixel circuit portion.

[0078] In addition, according to an embodiment, the pixel circuit portion may further include a light emitting unit capacitor (not shown) connected to both ends of the light emitting element LED.

[0079] In the present embodiment, the description will be mainly based on an example in which one pixel PX includes one light emitting element LED.

[0080] In an embodiment, multiple transistors T1, T2, T3 are formed by a driving transistor T1 (also called a first transistor) and two switching transistors T2, T3, and the two switching transistors T2, T3 are divided into an input transistor T2 (also called a second transistor) and an initialization transistor T3 (also called a third transistor).

[0081] Each of the transistors T1 , T2 , T3 includes a gate electrode, a first electrode, and a second electrode, and further includes a semiconductor layer including a channel so that current flows or blocks the channel of the semiconductor layer depending on a voltage of the gate electrode.

[0082] Here, depending on a voltage applied to each transistor T1 , T2 , T3 , one of the first electrode and the second electrode may be a source electrode and the other of the first electrode and the second electrode may be a drain electrode.

[0083] The gate electrode of the driving transistor T1 is connected to a first end of the storage capacitor Cst, and is also connected to a second electrode (output electrode) of the input transistor T2.

[0084] In addition, a first electrode of the driving transistor T1 is connected to the driving voltage line 172 transmitting the driving voltage ELVDD, and a second electrode of the driving transistor T1 is connected to the electrode (anode) of the light emitting element LED, the second end of the storage capacitor Cst, and the first electrode of the initialization transistor T3.

[0085] The driving transistor T1 receives the data voltage DAT to the gate electrode according to the switching operation of the input transistor T2 and may supply a driving current to the light emitting element LED according to the voltage of the gate electrode.

[0086] At this time, the storage capacitor Cst stores and maintains the voltage of the gate electrode of the driving transistor T1.

[0087] The gate electrode of the driving transistor T1 may face the conductive pattern 111 , and the conductive pattern 111 may be electrically connected to the second electrode of the driving transistor T1 and the anode of the light emitting element LED.

[0088] The gate electrode of the input transistor T2 is connected to the first scan line 151 transmitting the first scan signal SC, and the first electrode of the input transistor T2 transmits the data voltage DAT or the reference voltage, and the first electrode of the input transistor T2 is connected to the data line 171, and the second electrode of the input transistor T2 is connected to one end of the storage capacitor Cst and the gate electrode of the driving transistor T1.

[0089] The input transistor T2 may be turned on according to the first scan signal SC to transfer the reference voltage or the data voltage DAT to the gate electrode of the driving transistor T1 and one end of the storage capacitor Cst.

[0090] A gate electrode of the initialization transistor T3 is connected to the second scan line 152 transmitting the second scan signal SS.

[0091] A first electrode of the initialization transistor T3 is connected to the second end of the storage capacitor Cst, the second electrode of the driving transistor T1 and one electrode (anode) of the light emitting element LED, and a second electrode of the initialization transistor T3 is connected to an initialization voltage line 173 supplying an initialization voltage INIT.

[0092] The initialization transistor T3 is turned on according to the second scan signal SS, which delivers the initialization voltage INIT to the anode of the light emitting element LED and the second end of the storage capacitor Cst, thereby initializing the voltage of the anode of the light emitting element LED.

[0093] The storage capacitor Cst has a first end connected to the gate electrode of the driving transistor T1 , and a second end connected to a first electrode of the initialization transistor T3 , a second electrode of the driving transistor T1 , and an anode of the light emitting element LED.

[0094] The cathode of the light emitting element LED is connected to a common voltage line transmitting a common voltage ELVSS.

[0095] The output current of the driving transistor T1 is transmitted to the anode of the light emitting element LED, the cathode of the light emitting element LED receives the common voltage through the common voltage line, the light emitting element LED receives the output current of the driving transistor T1, and emits light according to the output current to display grayscale.

[0096] In this article, we will refer to Figures 3 to 6 The structure of a transistor included in a pixel of a display device according to an embodiment is described.

[0097] For ease of explanation, Figures 3 to 6 The light emitting element LED is not shown, but only the light emitting element LED (see FIG. Figure 2 ) structure of the transistor below.

[0098] Figures 3 to 6 is a cross-sectional view of a display device according to some embodiments. Specifically, Figure 3 and Figure 4 is a cross-sectional view of some embodiments of a transistor including a trench structure; and Figure 5 and Figure 6 are cross-sectional views of some embodiments of transistors including fin structures.

[0099] refer to Figure 3 and Figure 4 , the display device according to the embodiment may include a substrate SUB.

[0100] In an embodiment, the substrate SUB may be a rigid substrate such as a glass substrate.

[0101] In another embodiment, the substrate SUB may be a flexible substrate that can be bent, folded, rolled, etc.

[0102] For example, the substrate SUB may include a polymer resin such as polyimide (PI), polyamide (PA), or polyethylene terephthalate (PET).

[0103] The substrate SUB may have a single layer or a multi-layer.

[0104] In an embodiment, the substrate SUB may have at least one base layer including a polymer resin and at least one inorganic layer sequentially alternately stacked.

[0105] The barrier layer BAR is positioned on the substrate SUB.

[0106] The barrier layer BAR can block impurities and the like from flowing through the substrate SUB.

[0107] The barrier layer BAR may be made of, for example, silicon nitride (SiNx ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) is formed by an inorganic insulating material.

[0108] These materials may be used alone or in combination with each other.

[0109] The barrier layer BAR may include a trench TCH.

[0110] The trench TCH may be formed from the top of the barrier layer BAR toward the substrate SUB.

[0111] The thickness of the barrier layer BAR in a portion where the trench TCH is formed may be thinner than the thickness of the barrier layer BAR in a portion where the trench TCH is not formed.

[0112] According to an embodiment, the trench TCH may penetrate the barrier layer BAR in the thickness direction to expose the top surface of the substrate SUB.

[0113] The trench TCH formed in the barrier layer BAR may include a vertical portion V1 .

[0114] The vertical portion V1 is a portion connecting, in a substantially vertical direction, the upper surface of the barrier layer BAR in a region where the trench TCH is not formed and the upper surface of the barrier layer BAR in a region where the trench TCH is formed.

[0115] In the cross section, the vertical portion V1 may correspond to a portion connecting the thinnest portion of the barrier layer BAR and the thickest portion of the barrier layer BAR.

[0116] According to an embodiment, when the trench TCH penetrates the barrier layer BAR to expose the upper surface of the substrate SUB, the length of the vertical portion V1 of the trench TCH may be the same as the thickness of the barrier layer BAR.

[0117] The length of the vertical portion V1 of the trench TCH may be from several hundred To several thousand

[0118] For example, the length of the vertical portion V1 may be approximately to

[0119] The length of the vertical portion V1 of the trench TCH may correspond to the depth D of the channel area CA of the semiconductor layer ACT.

[0120] If the length of the vertical portion V1 of the trench TCH is less than about It may then be difficult to ensure a sufficient channel length of the semiconductor layer ACT, which may worsen the short channel phenomenon.

[0121] The short channel phenomenon refers to a phenomenon in which the distance between the source and the drain is shortened because the channel does not have a sufficient length, and, therefore, the gate cannot function normally as a switch, resulting in leakage current and device performance degradation.

[0122] On the other hand, if the length of the vertical portion V1 of the trench TCH is greater than about If the trench TCH is long, as the step of the trench TCH increases, the thickness of the film adjacent to the channel region CA of the semiconductor layer ACT (such as the buffer layer BUF, the gate insulation layer GI, etc.) becomes thinner in the vertical part than in the horizontal part, aggravating the step coverage phenomenon, which may lead to differences in the device characteristics of the transistor.

[0123] The buffer layer BUF may be positioned on the barrier layer BAR.

[0124] The buffer layer BUF may prevent or substantially prevent penetration of unnecessary components such as impurity elements or moisture when the semiconductor layer ACT is formed.

[0125] In an embodiment, the buffer layer BUF may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and amorphous silicon (Si).

[0126] These materials may be used alone or in combination with each other.

[0127] The buffer layer BUF may overlap the trench TCH formed in the barrier layer BAR.

[0128] The buffer layer BUF may be formed along an outline of the trench TCH formed in the barrier layer BAR.

[0129] Forming along the contour may mean being formed with a step corresponding to a step of an upper surface of a lower layer.

[0130] In the case where the upper layer is formed along the contour, the upper layer has a step corresponding to the lower layer, but the total thickness may be constant.

[0131] The buffer layer BUF formed along the contour of the barrier layer BAR may have a step corresponding to a step of an upper surface of the barrier layer BAR and may be formed to have an overall constant thickness.

[0132] The buffer layer BUF may have a single layer or multiple layers.

[0133] In an embodiment, Figure 3 As shown in FIG, the buffer layer BUF may include a first buffer layer BF1 and a second buffer layer BF2.

[0134] The first buffer layer BF1 may be positioned on the barrier layer BAR, and the second buffer layer BF2 may be positioned on the first buffer layer BF1 .

[0135] The first buffer layer BF1 and the second buffer layer BF2 may overlap the trench TCH formed in the barrier layer BAR.

[0136] The first buffer layer BF1 may be formed along the outline of the trench TCH formed in the barrier layer BAR, and the second buffer layer BF2 may be formed along the outline of the first buffer layer BF1 .

[0137] The first buffer layer BF1 formed along the contour of the barrier layer BAR may have a step corresponding to the step of the upper surface of the barrier layer BAR and may have a constant total thickness, and the second buffer layer BF2 formed along the contour of the first buffer layer BF1 may have a step corresponding to the step of the upper surface of the first buffer layer BF1 and may have a constant total thickness.

[0138] According to an embodiment, a third buffer layer (not shown) may be further positioned on the second buffer layer BF2.

[0139] The third buffer layer may be formed along the outline of the second buffer layer BF2 and may overlap the trench TCH formed in the barrier layer BAR.

[0140] In embodiments, the thickness of the first buffer layer BF1 may be thinner than the thickness of the second buffer layer BF2 .

[0141] In an embodiment, the first buffer layer BF1 may include a material in which the amount of hydrogen emission (ie, the amount of hydrogen emission) increases as the stack thickness increases.

[0142] In an embodiment, the second buffer layer BF2 may include a material in which the amount of hydrogen emission is constant even as the stack thickness increases.

[0143] In an embodiment, for example, the first buffer layer BF1 may include silicon nitride (SiN x ), and the second buffer layer BF2 may include silicon oxide (SiO x ).

[0144] As will be described later, silicon nitride (SiN x ) than silicon oxide (SiO x ) The amount of hydrogen emitted per unit area of ​​silicon oxide (SiO x ) is large, and therefore, hydrogen is excessively injected into the semiconductor layer ACT formed subsequently, resulting in leakage current, and this can cause characteristic degradation.

[0145] Therefore, silicon nitride (SiN xThe first buffer layer BF1 may be formed to have a thickness greater than that of silicon oxide (SiO x )'s second buffer layer BF2 is thin.

[0146] In one embodiment, the silicon nitride (SiN x ) can be formed to a thickness of approximately to And contains silicon oxide (SiO x The thickness of the second buffer layer BF2 can be approximately to

[0147] According to an embodiment, the second buffer layer BF2 may have a thickness of about or greater thickness.

[0148] In this article, as will be referred to later Fig. 9 Described, made of silicon nitride (SiN x ) increases with the thickness of the stack, but the amount of hydrogen released by silicon oxide (SiO x )The amount of hydrogen released varies little depending on the stack thickness.

[0149] Therefore, by x )'s second buffer layer BF2 layer is stacked thickly to control hydrogen diffusion and ensure a sufficiently effective channel length.

[0150] In addition, the embodiments of the present invention limit the silicon nitride (SiN) with high hydrogen emission rate in the buffer layer BUF. x ) thickness and adjust the silicon oxide (SiO x ) can prevent or substantially prevent changes in device characteristics due to step coverage and improve device reliability.

[0151] The semiconductor layer ACT is positioned on the buffer layer BUF.

[0152] The semiconductor layer ACT may include an oxide semiconductor.

[0153] The oxide semiconductor includes at least one of indium (In), tin (Sn), zinc (Zn), gallium (Ga), titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and oxygen (O).

[0154] For example, the semiconductor layer ACT may include one or more of ITO, IGZO, ITGZO, and IGTO.

[0155] According to an embodiment, the semiconductor layer ACT may include a silicon semiconductor.

[0156] The semiconductor layer ACT may include a first area SA and a second area DA spaced apart from each other and a channel area CA between the first area SA and the second area DA.

[0157] The first area SA and the second area DA may be doped with impurities to have conductivity.

[0158] According to an embodiment, the semiconductor layer ACT may further include lightly doped drain (LDD) regions at both ends of the channel region CA.

[0159] The channel area CA may be formed to have a groove along the outline of the second buffer layer BF2 .

[0160] Since the second buffer layer BF2 is formed according to the profile of the first buffer layer BF1 , and the first buffer layer BF1 is formed according to the profile of the trench TCH formed in the barrier layer BAR, the channel area CA may be formed according to the profile of the trench TCH formed in the barrier layer BAR.

[0161] In this manner, the channel area CA may overlap the trench TCH formed in the barrier layer BAR, and may have a depth D corresponding to the length of the vertical portion V1 of the trench TCH.

[0162] The depth D of the channel area CA may be mainly determined by the length of the vertical portion V1 of the trench TCH formed in the barrier layer BAR.

[0163] In an embodiment, the depth D of the channel region CA may be approximately to

[0164] If the depth D of the channel region CA is less than about It is difficult to ensure sufficient channel length, and if the depth D is greater than about Then, a step coverage problem of adjacent insulating layers may occur, and device characteristics of the transistor may be degraded.

[0165] The width W of the channel area CA may be determined according to the width of the trench TCH formed in the barrier layer BAR and the thickness of the buffer layer BUF.

[0166] In an embodiment, the width W of the channel area CA may be formed to be about 5 μm or less.

[0167] For example, the width W of the channel area CA may be formed to be about 3 μm to about 5 μm.

[0168] If the width W of the channel area CA is less than about 3 μm, a short channel phenomenon may occur.

[0169] Meanwhile, if the width W of the channel area CA is greater than about 5 μm, it may be difficult to provide a display device having a sufficiently high resolution.

[0170] However, according to embodiments, the width W of the channel area CA may be formed to be about 3 μm or less.

[0171] Because the channel area CA according to the embodiment includes a groove structure, even when the width W of the channel area CA is narrow (about 3 μm or less), the depth D of the channel area CA can be adjusted, and thus, a sufficient channel length can be ensured, thereby alleviating the short channel phenomenon and providing a high-resolution display device with improved device reliability.

[0172] The gate insulating layer GI is positioned on the semiconductor layer ACT.

[0173] In an embodiment, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0174] These materials may be used alone or in combination with each other.

[0175] The gate insulating layer GI may have a single layer or a multi-layer.

[0176] In addition, the gate insulating layer GI may include a material having a high dielectric constant (eg, Al 2 O 3 、TiO 2 , HfO 2 etc.) to improve insulation performance.

[0177] The gate insulating layer GI may be formed along the outline of the channel area CA of the semiconductor layer ACT.

[0178] The gate insulating layer GI may be positioned to overlap the channel area CA of the semiconductor layer ACT.

[0179] In an embodiment, the gate insulating layer GI may have a thickness of about or less thickness.

[0180] As will be referred to later Figure 7 As described, if the thickness of the gate insulating layer GI increases, defects in the device may increase and characteristics thereof may deteriorate.

[0181] Therefore, in an embodiment, the thickness of the gate insulating layer GI is about or smaller.

[0182] As the thickness of the gate insulating layer GI becomes thinner, leakage current may increase.

[0183] In an embodiment, the thickness of the gate insulating layer GI for reducing the defect rate while minimizing or reducing the leakage current may be in the range of arrive within the range.

[0184] A gate conductive layer including a gate electrode GE may be located on the gate insulating layer GI.

[0185] In an embodiment, the gate conductive layer may include any one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and metal oxide, and may be a single layer or a multilayer including these.

[0186] The gate electrode GE may overlap the channel area CA.

[0187] In an embodiment, the gate electrode GE and the gate insulating layer GI are formed in the same process and may have the same planar shape.

[0188] The gate electrode GE may be positioned to overlap the semiconductor layer ACT and the substrate SUB in a direction perpendicular to the surface.

[0189] An interlayer insulating layer ILD may be positioned on the semiconductor layer ACT and the gate electrode GE.

[0190] In an embodiment, the interlayer insulating layer ILD may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ), and may be a single layer or multiple layers comprising these.

[0191] When the interlayer insulating layer ILD has a multi-layer and includes silicon nitride and silicon oxide, the layer including silicon nitride may be closer to the substrate SUB than the layer including silicon oxide.

[0192] A data conductive layer including the first electrode SE and the second electrode DE is located on the interlayer insulating layer ILD.

[0193] In an embodiment, the data conductive layer includes any one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and metal oxide, and may be a single layer or a multilayer including these.

[0194] The first electrode SE may make contact with the first area SA of the semiconductor layer ACT through an opening formed in the interlayer insulating layer ILD.

[0195] The second electrode DE may contact the second area DA of the semiconductor layer ACT through an opening formed in the interlayer insulating layer ILD.

[0196] The insulating film VIA is positioned on the data conductive layer.

[0197] The insulating film VIA may include any organic insulating material such as a general polymer such as polystyrene (PS), polymethyl methacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer such as polyimide, and a siloxane polymer.

[0198] Although not shown, a light emitting element LED including an anode, a light emitting layer, and a cathode may be positioned on the insulating film VIA.

[0199] Figure 4 is a cross-sectional view of a display device according to an embodiment.

[0200] Figure 4 Examples and Figure 3 The embodiment of FIG. 4 is different in that the corners of the trench TCH are rounded.

[0201] For Figure 3 The same components of the embodiments may not be repeated Figure 3 Description.

[0202] The buffer layer BUF and the semiconductor layer ACT may be formed along the outline of the trench TCH formed in the barrier layer BAR.

[0203] Forming along the contour may mean being formed with a step corresponding to a step of an upper surface of a lower layer.

[0204] In the case where the upper layer is formed along the contour, the upper layer has a step corresponding to the lower layer, but the total thickness may be constant.

[0205] In an embodiment, the channel region CA of the semiconductor layer ACT formed along the outline of the barrier layer BAR may include a gentle parabolic corner portion corresponding to the rounded corner of the trench TCH formed in the barrier layer BAR.

[0206] Therefore, a short channel phenomenon caused by the electric field concentration in the corner can be reduced.

[0207] In addition, since a reduction in threshold voltage due to electric field concentration can be prevented or substantially prevented, device performance can be further improved.

[0208] Figure 5 and Figure 6 is a cross-sectional view of a display device according to some embodiments.

[0209] Figure 5 and Figure 6 is a cross-sectional view of a transistor including a fin structure.

[0210] Further detailed description of the same configuration as that of the previously described embodiment may be omitted.

[0211] refer to Figure 5 , providing a substrate SUB.

[0212] The substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc.

[0213] The substrate SUB may be a single layer or a multi-layer.

[0214] In an embodiment, the substrate SUB may have at least one base layer including a polymer resin sequentially stacked and at least one inorganic layer alternately stacked.

[0215] A barrier layer BAR including a fin structure FIN is positioned on a substrate SUB.

[0216] The fin structure FIN may be formed to protrude from an upper surface of the barrier layer BAR.

[0217] The thickness of the barrier layer BAR in a region where the fin structure FIN is formed may be thicker than the thickness of the barrier layer BAR in a region where the fin structure FIN is not formed.

[0218] That is, a height of a top surface of the barrier layer BAR in a region where the fin structure FIN is formed may be higher than a height of a top surface of the barrier layer BAR in a region where the fin structure FIN is not formed.

[0219] The fin structure FIN formed in the barrier layer BAR may include a vertical portion V2 .

[0220] The vertical portion V2 may be a section substantially connecting an upper surface of the barrier layer BAR in a region where the fin structure FIN is formed and an upper surface of the barrier layer BAR in a region where the fin structure FIN is not formed in a vertical direction.

[0221] In the cross section, the vertical portion V2 of the fin structure FIN may correspond to a portion connecting the thinnest portion of the barrier layer BAR and the thickest portion of the barrier layer BAR.

[0222] The length of the vertical portion V2 of the fin structure FIN can be several hundred To several thousand

[0223] In an embodiment, for example, the length of the vertical portion V2 may be about About between.

[0224] The length of the vertical portion V2 of the fin structure FIN may correspond to the height H of the channel area CA of the semiconductor layer ACT.

[0225] If the length of the vertical portion V2 of the fin structure FIN is less than about It is difficult to ensure sufficient channel length, and if the length is greater than about Then, a buffer layer BUF, a gate insulating layer GI, etc. are required in a subsequent process. As the step coverage problem becomes more serious during the process, a difference in transistor device characteristics may occur.

[0226] The buffer layer BUF may be positioned on the barrier layer BAR.

[0227] The buffer layer BUF may be formed along an outline of the fin structure FIN formed in the barrier layer BAR.

[0228] In an embodiment, the buffer layer BUF may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and amorphous silicon (Si).

[0229] These materials may be used alone or in combination with each other.

[0230] The buffer layer BUF may overlap the fin structure FIN formed in the barrier layer BAR.

[0231] The buffer layer BUF may be formed along an outline of the fin structure FIN formed in the barrier layer BAR.

[0232] Forming along the contour may mean being formed with a step corresponding to a step of an upper surface of a lower layer.

[0233] In the case where the upper layer is formed along the contour, the upper layer has a step corresponding to the lower layer, but the total thickness may be constant.

[0234] The buffer layer BUF may be a single layer or multiple layers.

[0235] exist Figure 5 In the embodiment shown in , the buffer layer BUF may include a first buffer layer BF1 and a second buffer layer BF2 .

[0236] The first buffer layer BF1 may be positioned on the barrier layer BAR, and the second buffer layer BF2 may be positioned on the first buffer layer BF1 .

[0237] The first buffer layer BF1 and the second buffer layer BF2 may overlap the fin structure FIN formed in the barrier layer BAR.

[0238] The first buffer layer BF1 may be formed along the outline of the fin structure FIN formed on the barrier layer BAR, and the second buffer layer BF2 may be formed along the outline of the first buffer layer BF1 .

[0239] In embodiments, a third buffer layer (not shown) may be further located on the second buffer layer BF2.

[0240] The third buffer layer may be formed along the outline of the second buffer layer BF2 and may overlap the fin structure FIN formed in the barrier layer BAR.

[0241] In embodiments, the thickness of the first buffer layer BF1 may be thinner than the thickness of the second buffer layer BF2 .

[0242] The first buffer layer BF1 may include a material in which the amount of hydrogen emission increases as the stack thickness increases.

[0243] The second buffer layer BF2 may include a material in which the amount of hydrogen emission is constant even as the stack thickness increases.

[0244] In an embodiment, for example, the first buffer layer BF1 may include silicon nitride (SiN x ), and the second buffer layer BF2 may include silicon oxide (SiO x ).

[0245] As will be described later, silicon nitride (SiN x ) than silicon oxide (SiO x ) The amount of hydrogen emitted per unit area is large, and therefore, hydrogen is excessively injected into a semiconductor layer ACT formed subsequently, causing leakage current, which may cause characteristic degradation.

[0246] Therefore, silicon nitride (SiN x The first buffer layer BF1 may be formed to have a thickness greater than that of silicon oxide (SiO x )'s second buffer layer BF2 is thin.

[0247] In an embodiment, the silicon nitride (SiN x ) has a first buffer layer BF1 having a or less in thickness, and includes silicon oxide (SiO x ) has a second buffer layer BF2 having a and in an embodiment may be formed to be approximately or greater thickness.

[0248] In this article, as will be discussed later Fig. 9 As described in the x) increases with the thickness of the stack, but the amount of hydrogen released by silicon oxide (SiO x )The amount of hydrogen released varies little depending on the thickness of the stack.

[0249] Therefore, by x ) is stacked thicker, which can improve device reliability by preventing or substantially preventing changes in device characteristics due to step coverage while ensuring a sufficient effective channel length.

[0250] The semiconductor layer ACT is located on the buffer layer BUF.

[0251] The semiconductor layer ACT may include an oxide semiconductor.

[0252] The oxide semiconductor may include at least one of indium (In), tin (Sn), zinc (Zn), gallium (Ga), titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and oxygen (O).

[0253] In an embodiment, for example, the semiconductor layer ACT may include one or more of ITO, IGZO, ITGZO, and IGTO.

[0254] According to an embodiment, the semiconductor layer ACT may include a silicon semiconductor.

[0255] The semiconductor layer ACT may include a first area SA and a second area DA spaced apart from each other and a channel area CA between the first area SA and the second area DA.

[0256] The first area SA and the second area DA may be doped with impurities to have conductivity.

[0257] According to an embodiment, the semiconductor layer ACT may further include a lightly doped drain (LDD) between both ends of the channel area CA and the first and second areas SA and DA.

[0258] The channel area CA may be formed to have a fin structure FIN along the outline of the second buffer layer BF2 .

[0259] Since the second buffer layer BF2 is formed according to the profile of the first buffer layer BF1 and the first buffer layer BF1 is formed according to the profile of the fin structure FIN formed in the barrier layer BAR, the channel area CA may be formed according to the profile of the fin structure FIN formed in the barrier layer BAR.

[0260] In this manner, the channel area CA may overlap the fin structure FIN formed in the barrier layer BAR, and may have a height H corresponding to the length of the vertical portion V2 of the fin structure FIN.

[0261] The height H of the channel area CA may be mainly determined by the length of the vertical portion V2 of the fin structure FIN formed in the barrier layer BAR.

[0262] In an embodiment, the height H of the channel region CA may be formed to be approximately to

[0263] If the height H of the channel region CA is less than about It is difficult to ensure a sufficient channel length, and if the height H is greater than about Then, a step coverage problem of adjacent insulating layers may occur, which may degrade the device characteristics of the transistor.

[0264] The width W of the channel area CA may be determined according to the width of the fin structure FIN formed in the barrier layer BAR and the thickness of the buffer layer BUF.

[0265] In an embodiment, the width W of the channel area CA may be formed to be about 5 μm or less.

[0266] In an embodiment, for example, the width W of the channel area CA may be about 3 μm to 5 μm.

[0267] If the width W of the channel region CA is less than about 3 μm, a short channel phenomenon may occur, and if the width W of the channel region CA is greater than about 5 μm, it is difficult to provide a display device having a sufficiently high resolution.

[0268] However, according to embodiments, the width W of the channel area CA may be formed to be about 3 μm or less.

[0269] Because the channel region CA according to the embodiment includes the fin structure FIN, the height H of the channel region CA can be adjusted even when the width W of the channel region CA is narrow (about 3 μm or less), and thus, a sufficient channel length can be ensured, thereby alleviating the short channel phenomenon and providing a high-resolution display device with improved device reliability.

[0270] The gate insulating layer GI is positioned on the semiconductor layer ACT.

[0271] In an embodiment, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0272] These materials may be used alone or in combination with each other.

[0273] In addition, the gate insulating layer GI may include, for example, Al2 O 3 、TiO 2 , HfO 2 Materials with high dielectric constants such as 200V and 250V are used to improve insulation performance.

[0274] The gate insulating layer GI may be a single layer or a multi-layer.

[0275] The gate insulating layer GI may be formed along the outline of the channel area CA of the semiconductor layer ACT.

[0276] The gate insulating layer GI may be positioned to overlap the channel area CA of the semiconductor layer ACT.

[0277] In an embodiment, the gate insulating layer GI may have a thickness of about or less thickness.

[0278] As will be referred to later Figure 7 As described, if the thickness of the gate insulating layer GI increases, defects in the device may increase and characteristics may deteriorate.

[0279] Therefore, in an embodiment, the thickness of the gate insulating layer GI is about or smaller.

[0280] As the thickness of the gate insulating layer GI becomes thinner, leakage current may increase.

[0281] In an embodiment, the thickness of the gate insulating layer GI for reducing the defect rate while minimizing or reducing the leakage current may be in the range of to within the range.

[0282] A gate conductive layer including a gate electrode GE may be located on the gate insulating layer GI.

[0283] In an embodiment, the gate conductive layer may include any one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and metal oxide, and may be a single layer or a multilayer including these.

[0284] An interlayer insulating layer ILD may be positioned on the semiconductor layer ACT and the gate electrode GE.

[0285] In an embodiment, the interlayer insulating layer ILD may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) and may be a single layer or multiple layers comprising these.

[0286] A data conductive layer including the first electrode SE and the second electrode DE is located on the interlayer insulating layer ILD.

[0287] In an embodiment, the data conductive layer may include any one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and metal oxide, and may be a single layer or a multilayer including these.

[0288] The first electrode SE may make contact with the first area SA of the semiconductor layer ACT through an opening formed in the interlayer insulating layer ILD.

[0289] The second electrode DE may contact the second area DA of the semiconductor layer ACT through an opening formed in the interlayer insulating layer ILD.

[0290] The insulating film VIA is positioned on the data conductive layer.

[0291] The insulating film VIA may include any organic insulating material such as a general polymer such as polystyrene (PS), polymethyl methacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer such as polyimide, and a siloxane polymer.

[0292] Figure 6 is a cross-sectional view of a display device according to an embodiment.

[0293] Figure 6 Examples and Figure 5 The embodiment of FIG. 1 is different in that the corners of the fin structure FIN are rounded.

[0294] For Figure 5 For the same components of the embodiments, the description thereof may not be repeated.

[0295] The buffer layer BUF and the semiconductor layer ACT may be formed along an outline of the fin structure FIN formed in the barrier layer BAR.

[0296] Forming along the contour may mean being formed with a step corresponding to a step of an upper surface of a lower layer.

[0297] In the case where the upper layer is formed along the contour, the upper layer has a step corresponding to the lower layer, but the total thickness may be constant.

[0298] In an embodiment, the channel region CA of the semiconductor layer ACT formed along the outline of the barrier layer BAR may include a gentle parabolic corner portion corresponding to the rounded corner of the fin structure FIN of the barrier layer BAR.

[0299] Therefore, the short channel phenomenon caused by the electric field concentration in the corner can be reduced.

[0300] In addition, since a reduction in threshold voltage due to electric field concentration can be prevented or substantially prevented, device performance can be further improved.

[0301] Figure 7 is a diagram showing silicon oxide (SiO x ) and the defect rate.

[0302] Figure 7 Silicon oxide (SiO x ) deposited to The thickness of the film and silicon oxide (SiO x ) deposited to The results obtained by the electron spin resonance test are shown in Table 1 below.

[0303] In electron spin resonance testing, the number of spins per unit area is proportional to the defect density.

[0304] Table 1

[0305]

[0306] refer to Figure 7 From Table 1, it can be seen that when silicon oxide (SiO x ) When the deposition is thick, the defect density is large.

[0307] That is, silicon oxide (SiO x ) has a larger thickness, the oxygen-deficient region and / or the higher the concentration of hydrogen, so that the amount of hydrogen injected into the semiconductor layer increases, which may degrade the device characteristics.

[0308] In an embodiment, a silicon oxide (SiO x ) is formed to have a thickness of about or smaller to manage device characteristics.

[0309] Figure 8 is a graph for explaining the amount of hydrogen emission according to the thickness of a gate insulating layer according to an embodiment.

[0310] Figure 8 The simulation shows samples (C0, E0) in which the gate insulating layer GI according to the embodiment has a reference thickness (Ref), the gate insulating layer GI has a thickness greater than the reference thickness. Thickness The samples (C1, E1), and the gate insulating layer GI has a thickness greater than the reference thickness. Thickness Results of hydrogen emission of samples (C2, E2).

[0311] refer to Figure 8 , it can be seen that the amount of hydrogen emission increases with the thickness of the gate insulating layer GI.

[0312] In this manner, if the thickness of the gate insulating layer GI is thick, the amount of released hydrogen increases, and thus, the amount of hydrogen injected into the semiconductor layer increases, and an effective channel area decreases, which may cause degradation of device characteristics.

[0313] Fig. 9 is a graph for explaining an amount of hydrogen emission according to a thickness of each buffer layer according to an embodiment.

[0314] According to an embodiment, the buffer layer BUF is made of silicon oxide (SiO x ) layer BBO and silicon nitride (SiN x ) layers of BBN, and the hydrogen emission was tested by changing the thickness of each layer.

[0315] Fig. 9 The samples (C0, E0) from which the buffer layer BUF has a reference thickness (Ref), the buffer layer BUF containing silicon oxide (SiO x ) layer BBO has a thickness greater than the reference Thickness The samples (C1, E1) and the buffer layer BUF containing silicon oxide (SiO x ) layer BBO has a thickness greater than the reference Thickness The samples (C2, E2), the buffer layer BUF containing silicon nitride (SiN x ) of the BBN layer has a thickness greater than the reference Thickness The samples (C3, E3), and the buffer layer BUF containing silicon nitride (SiN x ) of the BBN layer has a thickness greater than the reference Thickness The amount of hydrogen emission (exhaust volume) of the samples (C4, E4).

[0316] refer to Fig. 9 It can be seen that the buffer layer BUF contains silicon oxide (SiO x ) has little effect on the amount of hydrogen emission.

[0317] On the other hand, it can be seen that the amount of hydrogen emission increases with the amount of silicon nitride (SiN x ) increases with the increase of the thickness of the BBN layer.

[0318] In this way, when silicon nitride (SiN x) when the thickness of the layer BBN of the buffer layer BUF is thick, the amount of released hydrogen increases, and accordingly, the amount of hydrogen injected into the semiconductor layer increases and the effective channel area decreases, which may lead to degradation of device characteristics.

[0319] At the same time, the layer BBO containing silicon oxide (SiOx) of the buffer layer BUF can be formed by x ) is adjusted to control the thickness of the buffer layer BUF without changing the characteristics of the device, because even when the thickness is increased, the hydrogen emission amount is similar to that of the standard sample (C0, E0).

[0320] In one embodiment, the buffer layer BUF includes silicon nitride (SiN x ) layer BBN thickness is controlled to about to about to limit the amount of hydrogen emission, and the BBO layer contains silicon oxide (SiO x ). The thickness of the BBO layer can be controlled to about to The buffer layer BUF is made thick enough not to increase the amount of hydrogen released from the buffer layer BUF.

[0321] According to an embodiment, the silicon oxide (SiO x ) can be formed to a thickness of or larger.

[0322] In this manner, according to embodiments, the buffer layer BUF has a sufficient thickness and can be controlled to keep the hydrogen emission amount of the buffer layer BUF constant, so that a step coverage problem caused by the trench or fin structure FIN can be improved and device defects can be minimized or reduced.

[0323] Fig.10 is a circuit diagram of a pixel of a display device according to an embodiment.

[0324] according to Fig.10 The pixel includes a plurality of transistors T1, T2, T3, T4, T5 connected to various wirings 127, 151, 152, 153, 155, 171, 172, 173, as well as a storage capacitor Cst, a holding capacitor Chold, and a light emitting element LED.

[0325] Here, the transistor and the capacitor other than the light emitting element LED constitute a pixel circuit portion, and one pixel may include the pixel circuit portion and the light emitting element LED.

[0326] A plurality of wirings 127 , 151 , 152 , 153 , 155 , 171 , 172 , and 173 are connected to one pixel PX.

[0327] The plurality of wirings include a reference voltage line 127 , a first scan line 151 , a second scan line 152 , a third scan line 153 , a light emission control line 155 , a data line 171 , a driving voltage line 172 , and an initialization voltage line 173 .

[0328] In addition, a common voltage line transmitting a common voltage ELVSS may be connected to one side of the light emitting element LED.

[0329] The first scan line 151 transmits the first scan signal SC to the gate electrode of the second transistor T2 , and the second scan line 152 transmits the second scan signal SS to the gate electrode of the third transistor T3 .

[0330] The third scan line 153 transmits the third scan signal SI to the gate electrode of the fourth transistor T4, and the light emitting control line 155 transmits the emission signal EM to the gate electrode of the fifth transistor T5.

[0331] The data line 171 is a wiring for transmitting a data voltage DAT generated from a data driving part (not shown). Therefore, the magnitude of the light emitting current transmitted to the light emitting element LED changes, which in turn changes the brightness of the light emitting element.

[0332] The driving voltage line 172 applies a driving voltage ELVDD.

[0333] The reference voltage line 127 supplies a reference voltage REF, and the initialization voltage line 173 supplies an initialization voltage INIT.

[0334] In an embodiment, each voltage applied to the driving voltage line 172 , the reference voltage line 127 , and the initialization voltage line 173 may be a constant voltage.

[0335] The magnitude of the light emitting current output to one electrode (anode) of the light emitting element LED is adjusted according to the magnitude of the voltage of the gate electrode of the driving transistor T1 (also referred to as the driving gate electrode or the first driving gate electrode in this article) (i.e., the voltage stored in the storage capacitor Cst).

[0336] The magnitude of the light emitting current output to one electrode (anode) of the light emitting element LED may be adjusted according to the data voltage DAT applied to the pixel.

[0337] To this end, the first electrode of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5 .

[0338] Meanwhile, a second electrode of the driving transistor T1 outputs a light emitting current to the light emitting element LED and is connected to one electrode (anode) of the light emitting element LED.

[0339] The data voltage DAT is applied to the driving gate electrode of the driving transistor T1 through the second transistor T2.

[0340] Meanwhile, the driving gate electrode of the driving transistor T1 is connected to one electrode (referred to herein as a second storage electrode) of the storage capacitor Cst.

[0341] Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the light emitting current output by the driving transistor T1 changes accordingly.

[0342] The storage capacitor Cst is used to keep the voltage of the gate electrode of the driving transistor T1 constant during one frame.

[0343] Meanwhile, the driving gate electrode of the driving transistor T1 is also connected to the third transistor T3 and may be initialized by receiving the reference voltage REF.

[0344] In addition, the driving transistor T1 may also include an overlapping electrode (also referred to herein as a second driving gate electrode) overlapping with the channel positioned in the semiconductor layer, and the overlapping electrode is an electrode (anode) of the light emitting element LED. It is connected to the second electrode of the fourth transistor T4 and the second electrode of the holding capacitor Chold.

[0345] The overlapping electrode (second driving gate electrode) is connected to one electrode (anode) of the light emitting element LED so that the characteristics of the driving transistor T1 can be maintained unchanged during the light emitting period.

[0346] The second transistor T2 is a transistor that receives the data voltage DAT into the pixel.

[0347] A gate electrode of the second transistor T2 is connected to the first scan line 151 .

[0348] A first electrode of the second transistor T2 is connected to the data line 171, and a second electrode of the second transistor T2 is connected to the driving gate electrode of the driving transistor T1, the second electrode of the third transistor T3, and the second storage electrode of the storage capacitor Cst.

[0349] When the second transistor T2 is turned on by the positive polarity voltage of the first scan signal SC transmitted through the first scan line 151, the data voltage DAT transmitted through the data line 171 is transmitted to the driving gate electrode of the driving transistor T1, and at this time, the data voltage DAT is stored in the second storage electrode of the storage capacitor Cst.

[0350] According to an embodiment, a parasitic capacitor is provided between the first scan line 151 and the driving gate electrode of the driving transistor T1 (or the second storage electrode of the storage capacitor Cst or the second electrode of the third transistor T3 ), and may form a type of boosting capacitor (not shown).

[0351] The third transistor T3 transmits the reference voltage REF to the driving gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0352] A gate electrode of the third transistor T3 is connected to the second scan line 152 , and a first electrode of the third transistor T3 is connected to the reference voltage line 127 .

[0353] A second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the driving gate electrode of the driving transistor T1, and the second electrode of the second transistor T2.

[0354] The third transistor T3 is turned on by the positive voltage of the second scan signal SS received through the second scan line 152, and at this time, the reference voltage REF is applied to the driving transistor T1, and the driving transistor T1 is initialized by transferring the reference voltage REF to the driving gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0355] The fourth transistor T4 is used to initialize one electrode (anode) of the light emitting element LED.

[0356] Herein, the fourth transistor T4 is also referred to as a light emitting diode initialization transistor.

[0357] When one electrode (anode) of the light emitting element LED is initialized, the fourth transistor T4 is connected to the overlapping electrode (second driving gate electrode) of the driving transistor T1, the first storage electrode of the storage capacitor Cst, and the second electrode of the holding capacitor Chold is also initialized.

[0358] The gate electrode of the fourth transistor T4 is connected to the third scan line 153, and the second electrode of the fourth transistor T4 is an electrode of the light-emitting element LED and the overlapping electrode of the driving transistor T1 (the second driving gate electrode), the first storage electrode of the storage capacitor Cst and the second electrode of the holding capacitor Chold, and the first electrode of the fourth transistor T4 is connected to the initialization voltage line 173.

[0359] When the third scan line 153 is turned on by the positive voltage of the third scan signal SI, the initialization voltage INIT is applied to the first electrode of the light emitting element LED, the overlapping electrode (second driving gate electrode) of the driving transistor T1, the first storage electrode of the storage capacitor Cst, and the second electrode of the holding capacitor Chold to initialize them.

[0360] The fifth transistor T5 transmits the driving voltage ELVDD to the first electrode of the driving transistor T1 .

[0361] A gate electrode of the fifth transistor T5 is connected to the light emission control line 155 , a first electrode of the fifth transistor T5 is connected to the driving voltage line 172 , and a second electrode of the fifth transistor T5 is connected to the first electrode of the driver transistor T1 .

[0362] When the fifth transistor T5 is turned on by the positive polarity voltage of the light emitting signal EM flowing through the light emitting control line 155 , the driving voltage ELVDD is applied to the first electrode of the driving transistor T1 .

[0363] A first storage electrode of the storage capacitor Cst is connected to the second electrode of the fourth transistor T4, the second electrode of the driving transistor T1, the overlapping electrode of the driving transistor T1 (the second driving gate electrode), the light emitting element LED, and the second electrode of the holding capacitor Chold, and a second storage electrode is connected to the gate electrode of the driving transistor T1, the second electrode of the third transistor T3, and the second electrode of the second transistor T2.

[0364] The storage capacitor Cst is used to keep the voltage of the driving gate electrode of the driving transistor T1 constant during one frame.

[0365] The first electrode of the holding capacitor Chold is connected to the driving voltage line 172, and the second electrode of the holding capacitor Chold is connected to the overlapping electrode (second driving gate electrode) of the driver transistor T1, one electrode (anode) of the light emitting element LED, the second electrode of the fourth transistor T4 and the first storage electrode of the storage capacitor Cst.

[0366] The holding capacitor Chold ensures that the voltage of the overlapping electrode (second driving gate electrode) of the driving transistor T1 and one electrode (anode) of the light emitting element LED is constant, and in particular, serves to keep the voltage constant during the light emitting period.

[0367] Fig.11 is a circuit diagram of a pixel of a display device according to an embodiment.

[0368] according to Fig.11The pixel includes a plurality of transistors T1, T2, T3, T4, T5, T6, T7 connected to various wirings 151, 152, 153, 155, 171, 172, 741, 173, a storage capacitor Cst, a boost capacitor Cboost, and a light emitting element LED.

[0369] However, depending on the embodiment, the boost capacitor Cboost may be omitted.

[0370] A plurality of wirings 151, 152, 153, 155, 171, 172, 741, and 173 are connected to one pixel PX (see FIG. Figure 1 ).

[0371] The plurality of wirings include a first scan line 151 , a second scan line 152 , a third scan line 153 , a light emission control line 155 , a data line 171 , a driving voltage line 172 , a common voltage line 741 , and an initialization voltage line 173 .

[0372] The first scan line 151 transmits the first scan signal SC to the second transistor T2 and the seventh transistor T7.

[0373] A voltage having a polarity opposite to that of a voltage applied to the first scan line 151 may be applied to the second scan line 152 simultaneously with a signal of the first scan line 151 .

[0374] For example, when a negative voltage is applied to the first scan line 151 , a positive voltage may be applied to the second scan line 152 .

[0375] The second scan line 152 transmits the second scan signal SS to the third transistor T3 .

[0376] The third scan line 153 transmits the initialization control signal SI to the fourth transistor T4.

[0377] The light emitting control line 155 transmits the light emitting control signal EM to the fifth transistor T5 and the sixth transistor T6 .

[0378] The data line 171 is a wiring that transmits a data voltage DAT, and therefore, the magnitude of a light emitting current transmitted to the light emitting element LED changes, and the brightness emitted by the light emitting element LED also changes.

[0379] The driving voltage line 172 applies a driving voltage ELVDD.

[0380] The initialization voltage line 173 transmits an initialization voltage INIT.

[0381] The common voltage line 741 applies a common voltage ELVSS to a cathode of a light emitting element LED (eg, a light emitting diode (LED)).

[0382] In an embodiment, voltages applied to the driving voltage line 172 , the initialization voltage line 173 , and the common voltage line 741 may each be a constant voltage.

[0383] In an embodiment, the magnitude of the light emitting current output to the anode of the light emitting diode (LED) is adjusted according to the magnitude of the voltage of the gate electrode of the driving transistor T1 (ie, the voltage stored in the storage capacitor Cst).

[0384] The brightness of the light emitting diode (LED) is adjusted according to the magnitude of the light emitting current output to the anode electrode of the light emitting diode (LED), and the light emitting brightness of the light emitting diode (LED) can be adjusted according to the data voltage DAT applied to the pixel.

[0385] To this end, the first electrode of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5 .

[0386] In addition, the first electrode of the driving transistor T1 is connected to the second electrode of the second transistor T2 to receive the data voltage DAT.

[0387] The second electrode of the driving transistor T1 outputs a light emitting current to a light emitting diode (LED) and is connected to an anode of the light emitting diode via a sixth transistor T6 (also referred to herein as an output control transistor).

[0388] In addition, the second electrode of the driving transistor T1 is connected to the third transistor T3 and transfers the data voltage DAT applied to the first electrode to the third transistor T3.

[0389] The gate electrode of the driving transistor T1 is connected to one electrode (referred to herein as a 'second storage electrode') of the storage capacitor Cst.

[0390] Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the light emitting current output by the driving transistor T1 changes accordingly.

[0391] The storage capacitor Cst is used to keep the voltage of the gate electrode of the driving transistor T1 constant during one frame.

[0392] The gate electrode of the driving transistor T1 is also connected to the third transistor T3 , so that the data voltage DAT applied to the first electrode of the driving transistor T1 reaches the gate electrode of the driving transistor T1 through the third transistor T3 .

[0393] The gate electrode of the driving transistor T1 is also connected to the fourth transistor T4 and may be initialized by receiving an initialization voltage INIT.

[0394] The second transistor T2 is a transistor that receives the data voltage DAT into the pixel.

[0395] The gate electrode of the second transistor T2 is connected to the first scan line 151 and one electrode of the boosting capacitor Cboost (referred to herein as a “lower boosting electrode”).

[0396] A first electrode of the second transistor T2 is connected to the data line 171 .

[0397] The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1.

[0398] When the second transistor T2 is turned on by the negative voltage of the first scan signal SC transmitted through the first scan line 151, the data voltage DAT transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1, and finally, the data voltage DAT is transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

[0399] The third transistor T3 electrically connects the second electrode of the driving transistor T1 to the gate electrode of the driving transistor T1 .

[0400] Therefore, the data voltage DAT is compensated by the threshold voltage of the driving transistor T1 and is thereafter stored in the second storage electrode of the storage capacitor Cst.

[0401] A gate electrode of the third transistor T3 is connected to the second scan line 152 , and a first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1 .

[0402] A second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the other electrode of the boosting capacitor Cboost (referred to herein as a “boosting electrode”).

[0403] The third transistor T3 is turned on by the positive voltage of the second scan signal SS received through the second scan line 152, and the gate electrode and the second electrode of the driving transistor T1 are connected, and the voltage applied to the gate electrode of the driving transistor T1 is transmitted to the second storage electrode of the storage capacitor Cst and stored in the storage capacitor Cs.

[0404] At this time, the voltage stored in the storage capacitor Cst when the driving transistor T1 is turned off is the voltage of the gate electrode of the driving transistor T1 , so that the threshold voltage (Vth) value of the driving transistor T1 is stored in the compensation state.

[0405] The fourth transistor T4 is used to initialize the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0406] A gate electrode of the fourth transistor T4 is connected to the third scan line 153 , and a first electrode of the fourth transistor T3 is connected to the initialization voltage line 173 .

[0407] The second electrode of the fourth transistor T4 is connected to the second gate electrode of the third transistor T3, the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boosting electrode of the boosting capacitor Cboost.

[0408] The fourth transistor T4 is turned on by the positive polarity voltage of the initialization control signal SI received through the third scan line 153, and the initialization voltage INIT is applied to the driving transistor T1. It is initialized by being transferred to the gate electrode, the second storage electrode of the storage capacitor Cst, and the boosting electrode of the boosting capacitor Cboost.

[0409] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1 .

[0410] The gate electrode of the fifth transistor T5 is connected to the light emission control line 155 , the first electrode of the fifth transistor T5 is connected to the driving voltage line 172 , and the second electrode is connected to the first electrode of the driving transistor T1 .

[0411] The sixth transistor T6 is used to transmit the light emitting current output from the driving transistor T1 to the light emitting diode (LED).

[0412] A gate electrode of the sixth transistor T6 is connected to the light emission control line 155, a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and a second electrode of the sixth transistor T6 is connected to the anode of the light emitting diode (LED).

[0413] The seventh transistor T7 is used to initialize the anode of the light emitting diode (LED).

[0414] A gate electrode of the seventh transistor T7 is connected to the first scan line 151 , a first electrode of the seventh transistor T7 is connected to an anode of a light emitting diode (LED), and a second electrode of the seventh transistor T7 is connected to an initialization voltage line 173 .

[0415] Here, the gate electrode of the seventh transistor T7 is connected to the first scan line 151 of the previous pixel, not to the same first scan line 151 as the gate electrode of the second transistor T2 of the same pixel, but to the same first scan line 151 as the gate electrode of the second transistor T2 of the previous pixel.

[0416] When the seventh transistor T7 is turned on by the negative voltage of the first scan line 151, the initialization voltage INIT is applied to the anode of the light emitting diode (LED) and is initialized.

[0417] The gate electrode of the seventh transistor T7 may be connected to a separate bypass control line through which a bypass signal is transmitted, and may be controlled by a line separate from the first scan line 151 .

[0418] In addition, according to an embodiment, the initialization voltage line 173 to which the initialization voltage INIT is applied may be the same as the initialization voltage line 173 to which the initialization voltage INIT is applied.

[0419] A single pixel PX is described as including seven transistors T1 to T7 and two capacitors (storage capacitor Cst, boosting capacitor Cboost), but the embodiment is not limited thereto and the boosting capacitor Cboost may be excluded depending on the embodiment.

[0420] The structure of the pixel PX included in the display device according to the embodiment can be applied to Figure 2 , Fig.10 and Fig.11 The circuit diagram shown in FIG. 1 may have various pixel structures depending on the type of the display device.

[0421] In an embodiment, each of the transistors T1, T2, T3, T4, T5, T6 and T7 may have the above Figures 3 to 6 The structure of the transistor.

[0422] Although some embodiments have been described above, the scope of the present invention is not limited thereto and various modifications and improvements may be made by those skilled in the art using the basic concept of the invention as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: substrate; a barrier layer on the substrate and comprising grooves; a first buffer layer disposed on the barrier layer and along a contour of the groove; a second buffer layer, the second buffer layer being disposed on the first buffer layer and along a contour of the first buffer layer; a semiconductor layer on the second buffer layer and including a channel region overlapping the trench; a gate insulating layer on the semiconductor layer and overlapping the channel region; and a gate electrode on the gate insulating layer and overlapping the channel region, The first buffer layer has a thickness thinner than that of the second buffer layer.

2. The display device according to claim 1, wherein: The trench includes a vertical portion connecting a portion of the barrier layer having the thinnest thickness and a portion of the barrier layer having the thickest thickness, The channel region has a depth corresponding to the vertical portion of the trench, The depth of the channel region is to and The channel region has a width of 5 μm or less.

3. The display device according to claim 1, wherein: The first buffer layer includes a material whose amount of hydrogen emission increases as the stack thickness increases, and The second buffer layer includes a material whose amount of hydrogen emission is constant as the stack thickness increases.

4. The display device according to claim 1, wherein: The first buffer layer includes silicon nitride, and the second buffer layer includes silicon oxide, The first buffer layer has to The thickness of the second buffer layer is to Thickness, The gate insulating layer has or greater and or less in thickness, and The gate insulating layer includes at least one of Al2O3, TiO2 and HfO2.

5. The display device according to claim 1, wherein: A corner portion of the groove has a rounded shape.

6. A display device, wherein: The display device comprises: substrate; a barrier layer on the substrate and including a fin structure; a first buffer layer, the first buffer layer being arranged on the barrier layer and along a contour of the fin structure; a second buffer layer, the second buffer layer being disposed on the first buffer layer and along a contour of the first buffer layer; a semiconductor layer on the second buffer layer and including a channel region overlapping the fin structure; a gate insulating layer on the semiconductor layer and overlapping the channel region; and a gate electrode on the gate insulating layer and overlapping the channel region, The first buffer layer has a thickness thinner than that of the second buffer layer.

7. The display device according to claim 6, wherein: The fin structure includes a vertical portion connecting a portion of the barrier layer having a thinnest thickness and a portion of the barrier layer having a thickest thickness, The channel region has a depth corresponding to the vertical portion of the fin structure, The depth of the channel region is to and The channel region has a width of 5 μm or less.

8. The display device according to claim 6, wherein: The first buffer layer includes a material whose amount of hydrogen emission increases as the stack thickness increases, and The second buffer layer includes a material whose amount of hydrogen emission is constant as the stack thickness increases.

9. The display device according to claim 6, wherein: The first buffer layer includes silicon nitride, and the second buffer layer includes silicon oxide, The first buffer layer has or less, and the second buffer layer has to The thickness of The gate insulating layer has or greater and or less thickness, and The gate insulating layer includes at least one of Al2O3, TiO2 and HfO2.

10. The display device according to claim 6, wherein: A corner portion of the fin structure has a rounded shape.

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