Display panel and display device

Abstract

A display panel is provided. The display panel comprises a plurality of sub-pixels, a plurality of antenna units, a color film and a black matrix. The color film comprises a plurality of color film blocks. The orthographic projection of each color film block in the plurality of color film blocks on the first substrate base plate is at least partially overlapped with the orthographic projection of the third electrode on the first substrate base plate, and is at least partially overlapped with the orthographic projection of the fourth electrode on the first substrate base plate. The orthographic projection of the black matrix on the first substrate is at least partially overlapped with the orthographic projection of the first electrode on the first substrate, and the orthographic projection of the black matrix on the first substrate is at least partially overlapped with the orthographic projection of the second electrode on the first substrate.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a display panel and a display device. Background Art

[0002] Liquid crystal antennas are antennas that use liquid crystal technology to dynamically control their characteristics and optimize their performance. Liquid crystals are materials that exhibit the properties of both liquids and crystals, typically with an ordered molecular structure that can be manipulated with external stimuli such as electric fields. Summary of the invention

[0003] In one aspect, the present disclosure provides a display panel comprising a plurality of sub-pixels and a plurality of antenna units; wherein each of the plurality of antenna units comprises a first substrate, a first transistor located on the first substrate, a first electrode connected to the first transistor, and a second electrode; the display panel further comprises a liquid crystal layer extending through the plurality of sub-pixels and the plurality of antenna units; the first electrode and the second electrode are configured to apply an electric field across a portion of the liquid crystal layer; each of the plurality of sub-pixels comprises the first substrate, a second transistor located on the first substrate, a third electrode connected to the second transistor, and a fourth electrode; the display panel further comprises a color film and a black matrix; the color film comprises a plurality of color film blocks; the orthographic projection of each of the plurality of color film blocks on the first substrate at least partially overlaps with the orthographic projection of the third electrode on the first substrate, and at least partially overlaps with the orthographic projection of the fourth electrode on the first substrate; and the orthographic projection of the black matrix on the first substrate at least partially overlaps with the orthographic projection of the first electrode on the first substrate, and at least partially overlaps with the orthographic projection of the second electrode on the first substrate.

[0004] Optionally, the orthographic projection of the black matrix on the first base substrate substantially covers the orthographic projection of the first electrode on the first base substrate, and substantially covers the orthographic projection of the second electrode on the first base substrate.

[0005] Optionally, the orthographic projection of the color filter on the first substrate does not substantially overlap with the orthographic projection of the first electrode on the first substrate, and does not substantially overlap with the orthographic projection of the second electrode on the first substrate; and the orthographic projection of the black matrix on the first substrate does not substantially overlap with the orthographic projection of the third electrode on the first substrate, and does not substantially overlap with the orthographic projection of the fourth electrode on the first substrate.

[0006] Optionally, the display panel further comprises a ground plate and a radiation plate spaced apart from each other; wherein an orthographic projection of the black matrix on the first substrate at least partially overlaps with an orthographic projection of the ground plate on the first substrate.

[0007] Optionally, the orthographic projection of the black matrix on the first substrate substantially covers the orthographic projection of the ground plane on the first substrate.

[0008] Optionally, the orthographic projection of the ground plate on the first substrate does not substantially overlap with the orthographic projection of the third electrode on the first substrate, and does not substantially overlap with the orthographic projection of the fourth electrode on the first substrate; and the orthographic projection of the ground plate on the first substrate at least partially overlaps with the orthographic projection of the first electrode on the first substrate, and at least partially overlaps with the orthographic projection of the second electrode on the first substrate.

[0009] Optionally, an orthographic projection of the color filter on the first substrate at least partially overlaps with an orthographic projection of the radiation plate on the first substrate.

[0010] Optionally, the orthographic projection of the radiation plate on the first substrate partially overlaps with a portion of the black matrix located in an area, in which the first electrode and the second electrode do not exist.

[0011] Optionally, the orthographic projection of the radiation plate on the first substrate does not substantially overlap with the orthographic projection of the first electrode on the first substrate, and does not substantially overlap with the orthographic projection of the second electrode on the first substrate; and the orthographic projection of the radiation plate on the first substrate at least partially overlaps with the orthographic projection of the third electrode on the first substrate, and at least partially overlaps with the orthographic projection of the fourth electrode on the first substrate.

[0012] Optionally, an orthographic projection of the black matrix on the first substrate at least partially overlaps with an orthographic projection of the radiation plate on the first substrate.

[0013] Optionally, the orthographic projection of the radiation plate on the first substrate does not substantially overlap with the orthographic projection of the first electrode on the first substrate, and does not substantially overlap with the orthographic projection of the second electrode on the first substrate; and the orthographic projection of the radiation plate on the first substrate does not substantially overlap with the orthographic projection of the third electrode on the first substrate, and does not substantially overlap with the orthographic projection of the fourth electrode on the first substrate.

[0014] Optionally, the display panel includes a light-transmitting area and an antenna area outside the light-transmitting area; wherein the display panel includes a transistor board; a first conductive layer located on the transistor board; a first planarization layer located on a side of the first conductive layer away from the transistor board; a second conductive layer located on a side of the first planarization layer away from the transistor board; the liquid crystal layer located on a side of the second conductive layer away from the transistor board; a third conductive layer located on a side of the liquid crystal layer away from the transistor board; the color film and the black matrix located on a side of the third conductive layer away from the transistor board; and a radiation plate and a ground plate located on a side of the color film and the black matrix away from the transistor board; wherein the third electrode and the fourth electrode are configured to modulate a portion of the liquid crystal layer located in the light-transmitting area; and the first electrode and the second electrode are configured to modulate a portion of the liquid crystal layer located in the antenna area.

[0015] Optionally, the first conductive layer includes the fourth electrode located in the light-transmitting area and the first electrode located in the antenna area; the fourth electrode and the first electrode are located in the same layer; the second conductive layer includes the third electrode located in the light-transmitting area and the second electrode located in the antenna area; and the third electrode and the second electrode are located in the same layer.

[0016] Optionally, the first conductive layer includes the fourth electrode located in the light-transmitting area and the first electrode located in the antenna area; the fourth electrode and the first electrode are located in the same layer; the second conductive layer includes the third electrode located in the light-transmitting area; the third conductive layer includes the second electrode located in the antenna area; and the third electrode and the second electrode are located in different layers.

[0017] Optionally, the first conductive layer includes the first electrode located in the antenna area; the second conductive layer includes the third electrode located in the light-transmitting area; the third conductive layer includes the fourth electrode located in the light-transmitting area and the second electrode located in the antenna area; the fourth electrode and the second electrode are located in the same layer; and the third electrode and the first electrode are located in different layers.

[0018] Optionally, the first conductive layer includes the fourth electrode located in the light-transmitting area; the second conductive layer includes the third electrode located in the light-transmitting area, the first electrode located in the antenna area and the second electrode located in the antenna area; and the third electrode, the first electrode and the second electrode are located in the same layer.

[0019] Optionally, the first conductive layer includes the third electrode and the fourth electrode located in the light-transmitting area, and the first electrode and the second electrode located in the antenna area; and the first electrode, the second electrode, the third electrode and the fourth electrode are located in the same layer.

[0020] Optionally, the first conductive layer includes the first electrode located in the antenna area; the second conductive layer includes the third electrode located in the light-transmitting area and the second electrode located in the antenna area; the third conductive layer includes the fourth electrode located in the light-transmitting area; the third electrode and the second electrode are located in the same layer; and the fourth electrode and the first electrode are located in different layers.

[0021] Optionally, the second conductive layer includes the first electrode and the second electrode located in the antenna area, and the third electrode located in the light-transmitting area; the third conductive layer includes the fourth electrode located in the light-transmitting area; and the first electrode, the second electrode and the third electrode are located in the same layer.

[0022] In another aspect, the present disclosure provides a display device, including a display panel described herein or manufactured by the method described herein, and one or more integrated circuits connected to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0025] Figure 2A is a plan view of a second electrode, a black matrix, and a color film in a display panel according to some embodiments of the present disclosure.

[0026] Figure 2B is a plan view of a second electrode, a black matrix, and a color film in a display panel according to some embodiments of the present disclosure.

[0027] Figure 2C is a plan view of a second electrode, a black matrix, and a color film in a display panel according to some embodiments of the present disclosure.

[0028] Figure 3 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0029] Figure 4 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0030] Figure 5 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0031] Figure 6 is a plan view of a second electrode, a black matrix, and a color film in a display panel according to some embodiments of the present disclosure.

[0032] Figure 7 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0033] Figure 8 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0034] Fig. 9 is a plan view of a second electrode, a fourth electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure.

[0035] Fig.10 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0036] Fig.11 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0037] Fig.12 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0038] Fig.13 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0039] Fig.14 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0040] Fig.15 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0041] Fig.16 is a plan view of a fourth electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure.

[0042] Fig.17 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0043] Fig.18 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0044] Fig.19 is a plan view of a fourth electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure.

[0045] Fig. 20 is a schematic diagram showing the structure of a display panel in some embodiments of the present disclosure.

[0046] Fig.21 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure.

[0047] Fig. 22 is a plan view of a second electrode, a fourth electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure.

[0048] Fig.23 is a schematic diagram showing the layout of a ground plate and a radiation plate in a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0049] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0050] In the related display devices, antennas are mounted on the screen frame or back plate of the display panel. These antennas in the related display devices generally have a mechanical or electronic structure for transmitting or receiving electromagnetic signals. However, the related display devices have low integration, lack precise control of signal transmission and reception of the antennas, and have low signal transmission efficiency. In addition, the related display devices generally use passive antennas, which cannot achieve precise control of large-area antenna arrays.

[0051] Therefore, the present disclosure provides, in particular, a display panel and a display device, which substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a display panel. In some embodiments, the display panel includes a plurality of sub-pixels and a plurality of antenna units. Optionally, each of the plurality of antenna units includes a first substrate, a first transistor located on the first substrate, a first electrode connected to the first transistor, and a second electrode. Optionally, the display panel also includes a liquid crystal layer extending through the plurality of sub-pixels and the plurality of antenna units. Optionally, the first electrode and the second electrode are configured to apply an electric field across a portion of the liquid crystal layer. Optionally, each of the plurality of sub-pixels includes a first substrate, a second transistor located on the first substrate, a third electrode connected to the second transistor, and a fourth electrode. Optionally, the display panel also includes a color filter and a black matrix. Optionally, the color filter includes a plurality of color filter blocks. Optionally, the orthographic projection of each of the plurality of color filter blocks on the first substrate overlaps at least partially with the orthographic projection of the third electrode on the first substrate, and overlaps at least partially with the orthographic projection of the fourth electrode on the first substrate. Optionally, the orthographic projection of the black matrix on the first substrate at least partially overlaps with the orthographic projection of the first electrode on the first substrate, and at least partially overlaps with the orthographic projection of the second electrode on the first substrate.

[0052] In a liquid crystal antenna, the structure of the antenna includes liquid crystal material to provide tunability. Traditional antennas have fixed geometry and operating frequencies, but liquid crystal antennas can modify their electrical properties, such as resonant frequency, beam direction, polarization, and impedance, by applying an electric field to the liquid crystal material. The basic principle of liquid crystal antennas includes changing the orientation or arrangement of liquid crystal molecules in response to an applied electric field. This change in the molecular arrangement affects the propagation of electromagnetic waves through the antenna structure, resulting in changes in the electrical characteristics of the antenna. Liquid crystal antennas provide the ability to reconfigure or adapt the properties of the antenna in real time, enabling dynamic adjustment to changing environmental conditions or communication requirements. Liquid crystal antennas can also facilitate multifunctional antennas that can operate on multiple frequency bands or support various communication protocols.

[0053] Figure 1 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Figure 1In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0054] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example from the second electrode E2. The liquid crystal layer LC is configured to introduce a controlled phase shift to the signal passing through it.

[0055] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0056] In some embodiments, the display panel further includes a color filter CF and a black matrix BM. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0057] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0058] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0059] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0060] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0061] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other.

[0062] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0063] In some embodiments, the orthographic projection of the color filter CF on the first base substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first base substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first base substrate BS1 partially overlaps with a portion of the black matrix BM located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0064] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0065] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0066] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0067] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0068] In some embodiments, the display panel is an Advanced Super Dimension Switch (ADS) display panel. In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; a first passivation layer PVX1 located on a side of the second transistor TFT2 away from the first substrate BS1; a fourth electrode E4 located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of the first planarization layer PLN1 or the second passivation layer PVX2 located on a side of the fourth electrode E4 away from the first substrate BS1; a third electrode E3 located on a side of at least one of the first planarization layer PLN1 or the second passivation layer PVX2 away from the first substrate BS1; a second A planarization layer PLN2, which is located on the side of the third electrode E3 away from the first substrate BS1; a first alignment layer AL1, which is located on the side of the second planarization layer PLN2 away from the first substrate BS1; a liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate BS1; a color film CF, which is located on the side of the second alignment layer AL2 away from the first substrate BS1; a second substrate BS2, which is located on the side of the color film CF away from the first substrate BS1; and a radiation plate RP, which is located on the side of the second substrate BS2 away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel further includes an overcoat layer OC, which is located on the side of the second alignment layer AL2 away from the first substrate BS1 and on the side of the color film CF close to the first substrate BS1.

[0069] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the first transistor TFT1 away from the first substrate BS1; a first electrode E1, which is located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of the first planarization layer PLN1 or the second passivation layer PVX2, which is located on a side of the first electrode E1 away from the first substrate BS1; a second electrode E2, which is located on a side of at least one of the first planarization layer PLN1 or the second passivation layer PVX2 away from the first substrate BS1; and a second electrode E3. A planarization layer PLN2, which is located on the side of the second electrode E2 away from the first substrate BS1; a first alignment layer AL1, which is located on the side of the second planarization layer PLN2 away from the first substrate BS1; a liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate BS1; a black matrix BM, which is located on the side of the second alignment layer AL2 away from the first substrate BS1; a second substrate BS2, which is located on the side of the black matrix BM away from the first substrate BS1; and a ground plane GP, which is located on the side of the second substrate BS2 away from the first substrate BS1. The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further includes an overcoat layer OC, which is located on the side of the second alignment layer AL2 away from the first substrate BS1 and on the side of the black matrix BM close to the first substrate BS1.

[0070] In some embodiments, the fourth electrode E4 of each sub-pixel is located in the same layer as the first electrode E1 of each antenna unit. In some embodiments, the third electrode E3 of each sub-pixel is located in the same layer as the second electrode E2 of each antenna unit. As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the fourth electrode E4 and the first electrode E1 are formed due to one or more steps of the same patterning process performed in a layer deposited in the same deposition process, the fourth electrode E4 is located in the same layer as the first electrode E1. In another example, the fourth electrode E4 and the first electrode E1 can be formed in the same layer by simultaneously performing the step of forming the fourth electrode E4 and the step of forming the first electrode E1. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0071] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first conductive layer CT1 located on the transistor plate TP; a first planarization layer PLN1 located on a side of the first conductive layer CT1 away from the transistor plate TP; a second conductive layer CT2 located on a side of the first planarization layer PLN1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the second conductive layer CT2 away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the liquid crystal layer LC away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0072] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the first conductive layer CT1 includes the fourth electrode E4 located in the light transmission region LTR and the first electrode E1 located in the antenna region AR. The fourth electrode E4 and the first electrode E1 are located in the same layer. In some embodiments, the second conductive layer CT2 includes the third electrode E3 located in the light transmission region LTR and the second electrode E2 located in the antenna region AR. The third electrode E3 and the second electrode E2 are located in the same layer.

[0073] See also Figure 1 In some embodiments, the orthographic projection of the first electrode E1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1, thereby forming a capacitor. The inventors of the present disclosure have found that the capacitor helps maintain the state of the liquid crystal molecules in the liquid crystal layer LC.

[0074] Figure 2A is a plan view of a second electrode, a black matrix, and a color filter in a display panel according to some embodiments of the present disclosure. As described above, in some embodiments, the second electrode E2 is used as a feeder configured to transmit and / or receive electromagnetic signals. Figure 2A In some embodiments, the display panel includes a feed line structure FLS, which includes a plurality of second electrodes (for example, the second electrode E2 is a part of the plurality of second electrodes). In some embodiments, the plurality of second electrodes are arranged in a plurality of rows. Each second electrode in the plurality of second electrodes is located between two adjacent rows of color film blocks of the color film CF.

[0075] exist Figure 2AIn the specific example depicted in , the orthographic projection of the black matrix BM on the substrate covers the orthographic projection of the feed line structure FLS on the substrate. Optionally, the black matrix BM is an integral structure extending through the inter-subpixel region of the display panel. In an example, the black matrix BM includes a plurality of horizontal rows and a plurality of vertical columns interconnected together.

[0076] Figure 2B is a plan view of a second electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure. Figure 2B In some embodiments, the display panel includes a feed line structure FLS, which includes a plurality of second electrodes (for example, the second electrode E2 is a part of the plurality of second electrodes). In some embodiments, the plurality of second electrodes are arranged in a plurality of columns. Each second electrode in the plurality of second electrodes is located between two adjacent columns of color film blocks of the color film CF.

[0077] exist Figure 2B In the specific example depicted in , the orthographic projection of the black matrix BM on the substrate covers the orthographic projection of the feed line structure FLS on the substrate. Optionally, the black matrix BM is an integral structure extending through the inter-subpixel region of the display panel. In an example, the black matrix BM includes a plurality of horizontal rows and a plurality of vertical columns interconnected together.

[0078] Figure 2C is a plan view of a second electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure. Figure 2C In some embodiments, the display panel includes a feed line structure FLS that substantially surrounds the plurality of color film blocks of the color film CF, for example, at least 30% (for example, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%) of the periphery of the area having the plurality of color film blocks of the color film CF. Optionally, the feed line structure FLS includes one or more rows of second electrodes and one or more columns of second electrodes (for example, the second electrode E2 is part of the feed line structure FLS).

[0079] Figure 3 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Figure 3In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0080] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0081] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0082] Figure 4 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Figure 4 In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0083] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example, from the second electrode E2. The first electrode E1 and the liquid crystal layer LC combination are configured to introduce a controlled phase shift to the signal passing through it.

[0084] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0085] In some embodiments, the display panel further includes a color filter CF and a black matrix BM. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0086] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0087] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0088] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0089] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0090] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other.

[0091] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0092] In some embodiments, the orthographic projection of the color filter CF on the first base substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first base substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first base substrate BS1 partially overlaps with a portion of the black matrix BM located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0093] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0094] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0095] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0096] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0097] In some embodiments, the display panel is an advanced super-dimensional field switching technology (ADS) display panel. In some embodiments, each sub-pixel in the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the second transistor TFT2 away from the first substrate BS1; a fourth electrode E4, which is located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of the first planarization layer PLN1 or the second passivation layer PVX2, which is located on a side of the fourth electrode E4 away from the first substrate BS1; a third electrode E3, which is located at least one of the first planarization layer PLN1 or the second passivation layer PVX2; at least one side away from the first substrate BS1; a first alignment layer AL1, which is located on the side of the third electrode E3 away from the first substrate BS1; a liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate BS1; a color film CF, which is located on the side of the second alignment layer AL2 away from the first substrate BS1; a second substrate BS2, which is located on the side of the color film CF away from the first substrate BS1; and a radiation plate RP, which is located on the side of the second substrate BS2 away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel further includes an overcoat layer OC, which is located on the side of the second alignment layer AL2 away from the first substrate BS1 and on the side of the color film CF close to the first substrate BS1.

[0098] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; a first passivation layer PVX1 located on a side of the first transistor TFT1 away from the first substrate BS1; a first electrode E1 located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of a first planarization layer PLN1 or a second passivation layer PVX2 located on a side of the first electrode E1 away from the first substrate BS1; a first alignment layer AL1 located in the first planarization layer PLN1 or the second passivation layer PVX2; at least one side away from the first substrate substrate BS1; a liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate substrate BS1; a second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate substrate BS1; a second electrode E2, which is located on the side of the second alignment layer AL2 away from the first substrate substrate BS1; a black matrix BM, which is located on the side of the second electrode E2 away from the first substrate substrate BS1; a second substrate substrate BS2, which is located on the side of the black matrix BM away from the first substrate substrate BS1; and a ground plane GP, which is located on the side of the second substrate substrate BS2 away from the first substrate substrate BS1. The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further includes an overcoat layer OC, which is located on the side of the second electrode E2 away from the first substrate substrate BS1 and on the side of the black matrix BM close to the first substrate substrate BS1. Optionally, the display panel further includes a third planarization layer PLN3, which is located on the side of the second alignment layer AL2 away from the first substrate substrate BS1 and on the side of the second electrode E2 close to the first substrate substrate BS1.

[0099] In some embodiments, the fourth electrode E4 of each sub-pixel and the first electrode E1 of each antenna unit are located in the same layer. In some embodiments, the third electrode E3 of each sub-pixel and the second electrode E2 of each antenna unit are located in different layers.

[0100] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first conductive layer CT1 located on the transistor plate TP; a first planarization layer PLN1 located on a side of the first conductive layer CT1 away from the transistor plate TP; a second conductive layer CT2 located on a side of the first planarization layer PLN1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the second conductive layer CT2 away from the transistor plate TP; a third conductive layer CT3 located on a side of the liquid crystal layer LC away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the third conductive layer CT3 away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0101] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the first conductive layer CT1 includes the fourth electrode E4 located in the light transmission region LTR and the first electrode E1 located in the antenna region AR. The fourth electrode E4 and the first electrode E1 are located in the same layer. In some embodiments, the second conductive layer CT2 includes the third electrode E3 located in the light transmission region LTR. In some embodiments, the third conductive layer CT3 includes the second electrode E2 located in the antenna region AR. The third electrode E3 and the second electrode E2 are located in different layers.

[0102] See also Figure 4 In some embodiments, the orthographic projection of the first electrode E1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1, thereby forming a capacitor. The inventors of the present disclosure have found that the capacitor helps to maintain the state of the liquid crystal molecules in the liquid crystal layer LC. Optionally, the orthographic projection of the first electrode E1 on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the second electrode E2 on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0103] Figure 5 Schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Figure 5 In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0104] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0105] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0106] Figure 6 is a plan view of a second electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure. Figure 6 In some embodiments, the orthographic projection of the black matrix BM on the base substrate substantially covers the orthographic projection of the second electrode E2 on the base substrate (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the second electrode E2 on the base substrate does not substantially overlap with the orthographic projection of the color film CF on the base substrate (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0107] Figure 7 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Figure 7In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0108] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example, from the second electrode E2. The first electrode E1 and the liquid crystal layer LC combination are configured to introduce a controlled phase shift to the signal passing through it.

[0109] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0110] In some embodiments, the display panel further includes a color filter CF and a black matrix BM. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0111] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0112] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0113] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0114] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0115] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other.

[0116] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0117] In some embodiments, the orthographic projection of the color filter CF on the first base substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first base substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first base substrate BS1 partially overlaps with a portion of the black matrix BM located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0118] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0119] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0120] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0121] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0122] In some embodiments, the display panel is a twisted nematic (TN) display panel. In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; at least one of a first passivation layer PVX1, a first planarization layer PLN1, or a second passivation layer PVX2, which is located on a side of the second transistor TFT2 away from the first substrate BS1; a third electrode E3, which is located on a side of at least one of the first passivation layer PVX1, a first planarization layer PLN1, or a second passivation layer PVX2 away from the first substrate BS1; a first alignment layer AL1, which is located on a side of the third electrode E3 away from the first substrate BS1; The display panel further comprises a first substrate BS1, a liquid crystal layer LC, which is located on a side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on a side of the liquid crystal layer LC away from the first substrate BS1; a fourth electrode E4, which is located on a side of the second alignment layer AL2 away from the first substrate BS1; a color film CF, which is located on a side of the fourth electrode E4 away from the first substrate BS1; a second substrate BS2, which is located on a side of the color film CF away from the first substrate BS1; and a radiation plate RP, which is located on a side of the second substrate BS2 away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel further comprises an overcoat layer OC, which is located on a side of the fourth electrode E4 away from the first substrate BS1 and on a side of the color film CF close to the first substrate BS1. Optionally, the display panel further comprises a third planarization layer PLN3, which is located on a side of the second alignment layer AL2 away from the first substrate BS1 and on a side of the fourth electrode E4 close to the first substrate BS1.

[0123] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; a first passivation layer PVX1 located on a side of the first transistor TFT1 away from the first substrate BS1; a first electrode E1 located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of a first planarization layer PLN1 or a second passivation layer PVX2 located on a side of the first electrode E1 away from the first substrate BS1; a first alignment layer AL1 located in the first planarization layer PLN1 or the second passivation layer PVX2; at least one side away from the first substrate substrate BS1; a liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate substrate BS1; a second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate substrate BS1; a second electrode E2, which is located on the side of the second alignment layer AL2 away from the first substrate substrate BS1; a black matrix BM, which is located on the side of the second electrode E2 away from the first substrate substrate BS1; a second substrate substrate BS2, which is located on the side of the black matrix BM away from the first substrate substrate BS1; and a ground plane GP, which is located on the side of the second substrate substrate BS2 away from the first substrate substrate BS1. The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further includes an overcoat layer OC, which is located on the side of the second electrode E2 away from the first substrate substrate BS1 and on the side of the black matrix BM close to the first substrate substrate BS1. Optionally, the display panel further includes a third planarization layer PLN3, which is located on the side of the second alignment layer AL2 away from the first substrate substrate BS1 and on the side of the second electrode E2 close to the first substrate substrate BS1.

[0124] In some embodiments, the fourth electrode E4 of each sub-pixel and the second electrode E2 of each antenna unit are located in the same layer. In some embodiments, the third electrode E3 of each sub-pixel and the first electrode E1 of each antenna unit are located in different layers.

[0125] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first conductive layer CT1 located on the transistor plate TP; a first planarization layer PLN1 located on a side of the first conductive layer CT1 away from the transistor plate TP; a second conductive layer CT2 located on a side of the first planarization layer PLN1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the second conductive layer CT2 away from the transistor plate TP; a third conductive layer CT3 located on a side of the liquid crystal layer LC away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the third conductive layer CT3 away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0126] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the first conductive layer CT1 includes the first electrode E1 located in the antenna region AR. In some embodiments, the second conductive layer CT2 includes the third electrode E3 located in the light transmission region LTR. In some embodiments, the third conductive layer CT3 includes the fourth electrode E4 located in the light transmission region LTR and the second electrode E2 located in the antenna region AR. The fourth electrode E4 and the second electrode E2 are located in the same layer. The third electrode E3 and the first electrode E1 are located in different layers.

[0127] See also Figure 7 In some embodiments, the orthographic projection of the first electrode E1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1, thereby forming a capacitor. The inventors of the present disclosure have found that the capacitor helps to maintain the state of the liquid crystal molecules in the liquid crystal layer LC. Optionally, the orthographic projection of the first electrode E1 on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the second electrode E2 on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0128] See also Figure 7 In some embodiments, the orthographic projection of the third electrode E3 on the first substrate BS1 at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the third electrode E3 on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0129] Figure 8is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Figure 8 In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0130] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0131] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0132] Fig. 9 is a plan view of a second electrode, a fourth electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure. Fig. 9 In some embodiments, the orthographic projection of the black matrix BM on the base substrate substantially covers the orthographic projection of the second electrode E2 on the base substrate (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the second electrode E2 on the base substrate does not substantially overlap with the orthographic projection of the color film CF on the base substrate (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0133] In some embodiments, the orthographic projection of the color filter CF on the base substrate substantially covers the orthographic projection of the fourth electrode E4 on the base substrate (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the base substrate does not substantially overlap with the orthographic projection of the black matrix BM on the base substrate (for example, does not overlap by at least 80%, does not overlap by at least 85%, does not overlap by at least 90%, does not overlap by at least 95%, does not overlap by at least 99%, or does not overlap at all).

[0134] Fig.10 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig.10 In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0135] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example, from the second electrode E2. The first electrode E1 and the liquid crystal layer LC combination are configured to introduce a controlled phase shift to the signal passing through it.

[0136] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0137] In some embodiments, the display panel further includes a color filter CF and a black matrix BM. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0138] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0139] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0140] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0141] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0142] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other.

[0143] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0144] In some embodiments, the orthographic projection of the color filter CF on the first base substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first base substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first base substrate BS1 partially overlaps with a portion of the black matrix BM located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0145] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0146] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0147] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0148] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0149] In some embodiments, the display panel is an advanced super-dimensional field switching technology (ADS) display panel. In some embodiments, each sub-pixel in the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the second transistor TFT2 away from the first substrate BS1; a fourth electrode E4, which is located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of the first planarization layer PLN1 or the second passivation layer PVX2, which is located on a side of the fourth electrode E4 away from the first substrate BS1; a third electrode E3, which is located on a side of at least one of the first planarization layer PLN1 or the second passivation layer PVX2 away from the first substrate BS1; a second A planarization layer PLN2, which is located on the side of the third electrode E3 away from the first substrate BS1; a first alignment layer AL1, which is located on the side of the second planarization layer PLN2 away from the first substrate BS1; a liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate BS1; a color film CF, which is located on the side of the second alignment layer AL2 away from the first substrate BS1; a second substrate BS2, which is located on the side of the color film CF away from the first substrate BS1; and a radiation plate RP, which is located on the side of the second substrate BS2 away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel further includes an overcoat layer OC, which is located on the side of the second alignment layer AL2 away from the first substrate BS1 and on the side of the color film CF close to the first substrate BS1.

[0150] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the first transistor TFT1 away from the first substrate BS1; at least one of a first planarization layer PLN1 or a second passivation layer PVX2, which is located on a side of the first passivation layer PVX1 away from the first substrate BS1; a first electrode E1 and a second electrode E2, which are located on a side of at least one of the first planarization layer PLN1 or the second passivation layer PVX2 away from the first substrate BS1; a second planarization layer PLN2, which is located The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further comprises an outer coating OC, which is located on the side of the second alignment layer AL2 away from the first substrate BS1 and on the side of the black matrix BM close to the first substrate BS1.

[0151] In some embodiments, the first electrode E1 and the second electrode E2 of each antenna unit are located in the same layer. In some embodiments, the third electrode E3 of each sub-pixel and the first electrode E1 and the second electrode E2 of each antenna unit are located in the same layer.

[0152] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first conductive layer CT1 located on the transistor plate TP; a first planarization layer PLN1 located on a side of the first conductive layer CT1 away from the transistor plate TP; a second conductive layer CT2 located on a side of the first planarization layer PLN1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the second conductive layer CT2 away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the liquid crystal layer LC away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0153] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the first conductive layer CT1 includes the fourth electrode E4 located in the light transmission region LTR. In some embodiments, the second conductive layer CT2 includes the third electrode E3 located in the light transmission region LTR, the first electrode E1 located in the antenna region AR, and the second electrode E2 located in the antenna region AR. The third electrode E3, the first electrode E1, and the second electrode E2 are located in the same layer.

[0154] See also Fig.10 In some embodiments, the orthographic projection of the first electrode E1 on the first base substrate BS1 does not overlap with the orthographic projection of the second electrode E2 on the first base substrate BS1.

[0155] Fig.11 Schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Fig.11 In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0156] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0157] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0158] Fig.12 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig.12 In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0159] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example, from the second electrode E2. The first electrode E1 and the liquid crystal layer LC combination are configured to introduce a controlled phase shift to the signal passing through it.

[0160] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0161] In some embodiments, the display panel further includes a color filter CF and a black matrix BM. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0162] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0163] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0164] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0165] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0166] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other.

[0167] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0168] In some embodiments, the orthographic projection of the color filter CF on the first base substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first base substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first base substrate BS1 partially overlaps with a portion of the black matrix BM located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0169] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0170] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0171] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0172] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0173] In some embodiments, the display panel is an In-Plane Switching (IPS) display panel. In some embodiments, each sub-pixel in the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the second transistor TFT2 away from the first substrate BS1; a third electrode E3 and a fourth electrode E4, which are located on a side of the first passivation layer PVX1 away from the first substrate BS1; a first planarization layer PLN1, which is located on a side of the third electrode E3 and the fourth electrode E4 away from the first substrate BS1; a first alignment layer AL1, which is located on a side of the first planarization layer PLN1 away from the first substrate BS1; a liquid crystal layer LC, which is located on a side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on a side of the liquid crystal layer LC away from the first substrate BS1; a color film CF, which is located on a side of the second alignment layer AL2 away from the first substrate BS1; a second substrate BS2, which is located on a side of the color film CF away from the first substrate BS1; and a radiation plate RP, which is located on a side of the second substrate BS2 away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel further comprises an overcoat layer OC, which is located on a side of the second alignment layer AL2 away from the first substrate BS1 and on a side of the color film CF close to the first substrate BS1.

[0174] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the first transistor TFT1 away from the first substrate BS1; a first electrode E1 and a second electrode E2, which are located on a side of the first passivation layer PVX1 away from the first substrate BS1; a first planarization layer PLN1, which is located on a side of the first electrode E1 and the second electrode E2 away from the first substrate BS1; a first alignment layer AL1, which is located on a side of the first planarization layer PLN1 away from the first substrate BS1; a liquid crystal layer LC, which is located on a side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on a side of the liquid crystal layer LC away from the first substrate BS1; a black matrix BM, which is located on a side of the second alignment layer AL2 away from the first substrate BS1; a second substrate BS2, which is located on a side of the color film CF away from the first substrate BS1; and a ground plane GP, which is located on a side of the second substrate BS2 away from the first substrate BS1. The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further comprises an overcoat layer OC, which is located on a side of the second alignment layer AL2 away from the first substrate BS1 and on a side of the black matrix BM close to the first substrate BS1.

[0175] In some embodiments, the first electrode E1 and the second electrode E2 of each antenna unit are located in the same layer. In some embodiments, the third electrode E3 and the fourth electrode E4 of each sub-pixel are located in the same layer. In some embodiments, the first electrode E1 and the second electrode E2 of each antenna unit and the third electrode E3 and the fourth electrode E4 of each sub-pixel are located in the same layer.

[0176] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first conductive layer CT1 located on the transistor plate TP; a first planarization layer PLN1 located on a side of the first conductive layer CT1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the first planarization layer PLN1 away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the liquid crystal layer LC away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0177] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the first conductive layer CT1 includes the third electrode E3 and the fourth electrode E4 located in the light transmission region LTR, and the first electrode E1 and the second electrode E2 located in the antenna region AR. The first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4 are located in the same layer.

[0178] See also Fig.12 In some embodiments, the orthographic projection of the first electrode E1 on the first base substrate BS1 does not overlap with the orthographic projection of the second electrode E2 on the first base substrate BS1.

[0179] Fig.13 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Fig.13 In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0180] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0181] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0182] Fig.14Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig.14 In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0183] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example, from the second electrode E2. The first electrode E1 and the liquid crystal layer LC combination are configured to introduce a controlled phase shift to the signal passing through it.

[0184] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0185] In some embodiments, the display panel further includes a color filter CF and a black matrix BM. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0186] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0187] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0188] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0189] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0190] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other.

[0191] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0192] In some embodiments, the orthographic projection of the color filter CF on the first base substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first base substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first base substrate BS1 partially overlaps with a portion of the black matrix BM located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0193] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0194] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0195] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0196] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0197] In some embodiments, the display panel is a twisted nematic (TN) display panel. In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; at least one of a first passivation layer PVX1, a first planarization layer PLN1, or a second passivation layer PVX2, which is located on a side of the second transistor TFT2 away from the first substrate BS1; a third electrode E3, which is located on a side of at least one of the first passivation layer PVX1, a first planarization layer PLN1, or a second passivation layer PVX2 away from the first substrate BS1; a first alignment layer AL1, which is located on a side of the third electrode E3 away from the first substrate BS1; The display panel further comprises a first substrate BS1 and a second substrate BS2, wherein the first substrate BS1 is provided on a side of the liquid crystal layer LC away from the first substrate BS1; a second substrate BS2 is provided on a side of the liquid crystal layer LC away from the first substrate BS1; a fourth electrode E4 is provided on a side of the second alignment layer AL2 away from the first substrate BS1; a color film CF is provided on a side of the fourth electrode E4 away from the first substrate BS1; a second substrate BS2 is provided on a side of the color film CF away from the first substrate BS1; and a radiation plate RP is provided on a side of the second substrate BS2 away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel further comprises an overcoat layer OC, which is provided on a side of the second alignment layer AL2 away from the first substrate BS1 and on a side of the color film CF close to the first substrate BS1.

[0198] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the first transistor TFT1 away from the first substrate BS1; a first electrode E1, which is located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of the first planarization layer PLN1 or the second passivation layer PVX2, which is located on a side of the first electrode E1 away from the first substrate BS1; a second electrode E2, which is located on a side of at least one of the first planarization layer PLN1 or the second passivation layer PVX2 away from the first substrate BS1; and a second electrode E3. A planarization layer PLN2, which is located on the side of the second electrode E2 away from the first substrate BS1; a first alignment layer AL1, which is located on the side of the second planarization layer PLN2 away from the first substrate BS1; a liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate BS1; a black matrix BM, which is located on the side of the second alignment layer AL2 away from the first substrate BS1; a second substrate BS2, which is located on the side of the black matrix BM away from the first substrate BS1; and a ground plane GP, which is located on the side of the second substrate BS2 away from the first substrate BS1. The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further includes an overcoat layer OC, which is located on the side of the second alignment layer AL2 away from the first substrate BS1 and on the side of the black matrix BM close to the first substrate BS1.

[0199] In some embodiments, the third electrode E3 of each sub-pixel and the second electrode E2 of each antenna unit are located in the same layer. In some embodiments, the fourth electrode E4 of each sub-pixel and the first electrode E1 of each antenna unit are located in different layers.

[0200] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first conductive layer CT1 located on the transistor plate TP; a first planarization layer PLN1 located on a side of the first conductive layer CT1 away from the transistor plate TP; a second conductive layer CT2 located on a side of the first planarization layer PLN1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the second conductive layer CT2 away from the transistor plate TP; a third conductive layer CT3 located on a side of the liquid crystal layer LC away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the third conductive layer CT3 away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0201] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the first conductive layer CT1 includes the first electrode E1 located in the antenna region AR. In some embodiments, the second conductive layer CT2 includes the third electrode E3 located in the light transmission region LTR and the second electrode E2 located in the antenna region AR. In some embodiments, the third conductive layer CT3 includes the fourth electrode E4 located in the light transmission region LTR. The third electrode E3 and the second electrode E2 are located in the same layer. The fourth electrode E4 and the first electrode E1 are located in different layers.

[0202] See also Fig.14 In some embodiments, the orthographic projection of the first electrode E1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1, thereby forming a capacitor. The inventors of the present disclosure have found that the capacitor helps to maintain the state of the liquid crystal molecules in the liquid crystal layer LC. Optionally, the orthographic projection of the first electrode E1 on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the second electrode E2 on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0203] See also Fig.14 In some embodiments, the orthographic projection of the third electrode E3 on the first substrate BS1 at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the third electrode E3 on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0204] Fig.15 Schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Fig.15 In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0205] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0206] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0207] Fig.16 is a plan view of a fourth electrode, a black matrix and a color filter in a display panel according to some embodiments of the present disclosure. Fig.16 In some embodiments, the orthographic projection of the color filter CF on the base substrate substantially covers the orthographic projection of the fourth electrode E4 on the base substrate (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the base substrate does not substantially overlap with the orthographic projection of the black matrix BM on the base substrate (for example, does not overlap by at least 80%, does not overlap by at least 85%, does not overlap by at least 90%, does not overlap by at least 95%, does not overlap by at least 99%, or does not overlap at all).

[0208] Fig.17 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig.17In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0209] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example, from the second electrode E2. The first electrode E1 and the liquid crystal layer LC combination are configured to introduce a controlled phase shift to the signal passing through it.

[0210] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0211] In some embodiments, the display panel further includes a color filter CF and a black matrix BM. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0212] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0213] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0214] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0215] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0216] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other.

[0217] In some embodiments, the orthographic projection of the black matrix BM on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the black matrix BM on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0218] In some embodiments, the orthographic projection of the color filter CF on the first base substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first base substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first base substrate BS1 partially overlaps with a portion of the black matrix BM located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0219] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0220] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the radiation plate RP on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0221] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0222] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0223] In some embodiments, the display panel is a twisted nematic (TN) display panel. In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; at least one of a first passivation layer PVX1, a first planarization layer PLN1, or a second passivation layer PVX2, which is located on a side of the second transistor TFT2 away from the first substrate BS1; a third electrode E3, which is located on a side of at least one of the first passivation layer PVX1, the first planarization layer PLN1, or the second passivation layer PVX2 away from the first substrate BS1; a second planarization layer PLN2, which is located on a side of the third electrode E3 away from the first substrate BS1; a first alignment layer A L1, which is located on the side of the second planarization layer PLN2 away from the first substrate BS1; the liquid crystal layer LC, which is located on the side of the first alignment layer AL1 away from the first substrate BS1; the second alignment layer AL2, which is located on the side of the liquid crystal layer LC away from the first substrate BS1; the fourth electrode E4, which is located on the side of the second alignment layer AL2 away from the first substrate BS1; the color film CF, which is located on the side of the fourth electrode E4 away from the first substrate BS1; the second substrate BS2, which is located on the side of the color film CF away from the first substrate BS1; and the radiation plate RP, which is located on the side of the second substrate BS2 away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel also includes an overcoat layer OC, which is located on the side of the second alignment layer AL2 away from the first substrate BS1 and on the side of the color film CF close to the first substrate BS1.

[0224] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; at least one of a first passivation layer PVX1, a first planarization layer PLN1, or a second passivation layer PVX2, which is located on a side of the first transistor TFT1 away from the first substrate BS1; a first electrode E1 and a second electrode E2, which are located on a side of at least one of the first passivation layer PVX1, the first planarization layer PLN1, or the second passivation layer PVX2 away from the first substrate BS1; a second planarization layer PLN2, which is located between the first electrode E1 and the second electrode E2. 2 is located on a side away from the first substrate BS1; a first alignment layer AL1 is located on a side away from the first substrate BS1 of the second planarization layer PLN2; a liquid crystal layer LC is located on a side away from the first substrate BS1 of the first alignment layer AL1; a second alignment layer AL2 is located on a side away from the first substrate BS1 of the liquid crystal layer LC; a black matrix BM is located on a side away from the first substrate BS1 of the second alignment layer AL2; a second substrate BS2 is located on a side away from the black matrix BM of the first substrate BS1; and a ground plane GP is located on a side away from the first substrate BS1 of the second substrate BS2. The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further includes an overcoat layer OC, which is located on a side away from the first substrate BS1 of the second alignment layer AL2 and on a side of the black matrix BM close to the first substrate BS1.

[0225] In some embodiments, the first electrode E1 and the second electrode E2 of each antenna unit are located in the same layer. In some embodiments, the third electrode E3 of each sub-pixel is located in the same layer as the first electrode E1 and the second electrode E2 of each antenna unit. In some embodiments, the fourth electrode E4 of each sub-pixel is located in a different layer from the first electrode E1 and the second electrode E2 of each antenna unit.

[0226] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first planarization layer PLN1 located on the transistor plate TP; a second conductive layer CT2 located on a side of the first planarization layer PLN1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the second conductive layer CT2 away from the transistor plate TP; a third conductive layer CT3 located on a side of the liquid crystal layer LC away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the third conductive layer CT3 away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0227] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the second conductive layer CT2 includes the first electrode E1 and the second electrode E2 located in the antenna region AR and the third electrode E3 located in the light transmission region LTR. In some embodiments, the third conductive layer CT3 includes the fourth electrode E4 located in the light transmission region LTR. The first electrode E1, the second electrode E2, and the third electrode E3 are located in the same layer.

[0228] See also Fig.17 In some embodiments, the orthographic projection of the first electrode E1 on the first base substrate BS1 does not overlap with the orthographic projection of the second electrode E2 on the first base substrate BS1.

[0229] See also Fig.17 In some embodiments, the orthographic projection of the third electrode E3 on the first substrate BS1 at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the third electrode E3 on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0230] Fig.18 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Fig.18 In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0231] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0232] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0233] Fig.19 is a plan view of a fourth electrode, a black matrix and a color filter in a display panel according to some embodiments of the present disclosure. Fig.19 In some embodiments, the orthographic projection of the color filter CF on the substrate substantially covers the orthographic projection of the fourth electrode E4 on the substrate (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the substrate does not substantially overlap with the orthographic projection of the black matrix BM on the substrate (for example, does not overlap by at least 80%, does not overlap by at least 85%, does not overlap by at least 90%, does not overlap by at least 95%, does not overlap by at least 99%, or does not overlap at all).

[0234] Fig. 20 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Fig. 20In some embodiments, the display panel includes a plurality of sub-pixels Sp and a plurality of antenna units AU. In some embodiments, each of the plurality of antenna units AU includes a first substrate substrate BS1, a first transistor TFT1 located on the first substrate substrate BS1, a first electrode E1 connected to the first transistor TFT1, and a second electrode E2. In some embodiments, the display panel further includes a liquid crystal layer LC extending through the plurality of sub-pixels Sp and the plurality of antenna units AU. The first electrode E1 and the second electrode E2 are configured to apply an electric field across a portion of the liquid crystal layer LC. The electric field causes a change in the refractive index of the liquid crystal material, which in turn changes the phase of the transmitted electromagnetic wave. By adjusting the voltage applied to the first electrode E1, the phase shift of the wave passing through the liquid crystal layer LC can be precisely controlled. In some embodiments, the first electrode E1 is connected to the drain of the first transistor TFT1 and is configured to be provided with a first data signal.

[0235] In some embodiments, the second electrode E2 is used as a feed line for each antenna unit. In some embodiments, the second electrode E2 is configured to transmit and / or receive electromagnetic signals. The liquid crystal layer LC is configured to adjust the phase of an input signal, for example, from the second electrode E2. The first electrode E1 and the liquid crystal layer LC combination are configured to introduce a controlled phase shift to the signal passing through it.

[0236] In some embodiments, each of the plurality of sub-pixels Sp includes a first substrate BS1, a second transistor TFT2 located on the first substrate BS1, a third electrode E3 connected to the second transistor TFT2, and a fourth electrode E4. In some embodiments, the third electrode E3 is used as a pixel electrode, and the fourth electrode E4 is used as a common electrode.

[0237] In some embodiments, the display panel further includes a color filter CF and a black matrix. In some embodiments, the color filter CF includes a plurality of color filter blocks. Each of the plurality of color filter blocks is at least partially located in a corresponding sub-pixel of the plurality of sub-pixels Sp. The orthographic projection of each color filter block on the first base substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first base substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first base substrate BS1.

[0238] In some embodiments, the black matrix includes a first black matrix layer BM1 located on the overcoat layer OC, and a second black matrix layer BM2 located on a side of the first black matrix layer BM1 away from the overcoat layer OC. Optionally, the orthographic projection of the first black matrix layer BM1 on the first substrate BS1 covers the orthographic projection of the second black matrix layer BM2 on the first substrate BS1. In some embodiments, the second black matrix layer BM2 is located on the same layer as the ground plate GP and / or the radiation plate RP. Optionally, the ground plate GP and / or the radiation plate RP exist in the antenna area AR. Optionally, the second black matrix layer BM2 does not exist in the antenna area AR. Optionally, the second black matrix layer BM2 exists in an area outside the light-transmitting area LTR and outside the antenna area AR.

[0239] In some embodiments, the orthographic projection of the first black matrix layer BM1 on the first substrate BS1 partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the first black matrix layer BM1 on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the first black matrix layer BM1 on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0240] In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the color filter CF on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0241] In some embodiments, the orthographic projection of the black matrix (including the first black matrix layer BM1 and the second black matrix layer BM2) on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the black matrix (including the first black matrix layer BM1 and the second black matrix layer BM2) on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0242] In some embodiments, the orthographic projection of the color film CF on the first substrate BS1 at least partially overlaps with the orthographic projection of the third electrode E3 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the color film CF on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0243] In some embodiments, the display panel further includes a ground plate GP and a radiation plate RP. In some embodiments, the ground plate GP and the radiation plate RP are spaced apart from each other. Fig. 20 In one example shown, the ground plate GP and the radiation plate RP are spaced apart from each other by a portion of the first black matrix layer BM1.

[0244] In some embodiments, the orthographic projection of the first black matrix layer BM1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the ground plate GP on the first substrate BS1. Optionally, the orthographic projection of the first black matrix layer BM1 on the first substrate BS1 substantially covers the orthographic projection of the ground plate GP on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0245] In some embodiments, the orthographic projection of the first black matrix layer BM1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the radiation plate RP on the first substrate BS1. Optionally, the orthographic projection of the second black matrix layer BM2 on the first substrate BS1 partially overlaps with a portion of the first black matrix layer BM1 located in an area, in which the first electrode E1 and the second electrode E2 do not exist.

[0246] In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the radiation plate RP on the first substrate BS1 does not substantially overlap with the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0247] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all). In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 does not substantially overlap with the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, at least 80% does not overlap, at least 85% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap, or does not overlap at all).

[0248] In some embodiments, the orthographic projection of the ground plate GP on the first substrate BS1 at least partially overlaps with the orthographic projection of the first electrode E1 on the first substrate BS1, and at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1. Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the ground plate GP on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0249] Various suitable black matrix materials may be used to form the first black matrix layer BM1. Examples of suitable black matrix materials for manufacturing the first black matrix layer BM1 include organic black materials such as black resin, black polyimide, black acrylic resin, black polycarbonate, black polyester, black polyolefin.

[0250] Various suitable black matrix materials can be used to form the second black matrix layer BM2. Examples of suitable black matrix materials for making the second black matrix layer BM2 include metal materials such as molybdenum, aluminum, and copper. In one example, the total thickness of the first black matrix layer BM1 and the second black matrix layer BM2 is about 1 μm.

[0251] In some embodiments, the display panel is a twisted nematic (TN) display panel. In some embodiments, each sub-pixel in the plurality of sub-pixels Sp includes a first substrate BS1; a second transistor TFT2 located on the first substrate BS1; at least one of the first passivation layer PVX1, the first planarization layer PLN1 or the second passivation layer PVX2, which is located on a side of the second transistor TFT2 away from the first substrate BS1; a third electrode E3, which is located on a side of at least one of the first passivation layer PVX1, the first planarization layer PLN1 or the second passivation layer PVX2 away from the first substrate BS1; a first alignment layer AL1, which is located on a side of the third electrode E3 away from the first substrate BS1; a liquid crystal layer LC, which is located on a side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on a side of the liquid crystal layer LC away from the first substrate BS1; a fourth electrode E4, which is located on a side of the second alignment layer AL2 away from the first substrate BS1; a color film CF, which is located on a side of the fourth electrode E4 away from the first substrate BS1; and a second substrate BS2, which is located on a side of the color film CF away from the first substrate BS1. The third electrode E3 is connected to the drain of the second transistor TFT2. Optionally, the display panel further includes an overcoat layer OC, which is located on a side of the fourth electrode E4 away from the first substrate BS1 and on a side of the color film CF close to the first substrate BS1. Optionally, the display panel further includes a third planarization layer PLN3, which is located on a side of the second alignment layer AL2 away from the first substrate BS1 and on a side of the fourth electrode E4 close to the first substrate BS1.

[0252] In some embodiments, each antenna unit in the plurality of antenna units AU includes a first substrate BS1; a first transistor TFT1 located on the first substrate BS1; a first passivation layer PVX1, which is located on a side of the first transistor TFT1 away from the first substrate BS1; a first electrode E1, which is located on a side of the first passivation layer PVX1 away from the first substrate BS1; at least one of a first planarization layer PLN1 or a second passivation layer PVX2, which is located on a side of the first electrode E1 away from the first substrate BS1; a first alignment layer AL1, which is located on at least one of the first planarization layer PLN1 or the second passivation layer PVX2 away from the first electrode E1. The display panel comprises a first substrate BS1, a liquid crystal layer LC, which is located on a side of the first alignment layer AL1 away from the first substrate BS1; a second alignment layer AL2, which is located on a side of the liquid crystal layer LC away from the first substrate BS1; a second electrode E2, which is located on a side of the second alignment layer AL2 away from the first substrate BS1; a first black matrix layer BM1, which is located on a side of the second electrode E2 away from the first substrate BS1; a ground plate GP and a radiation plate RP, which are located on a side of the first black matrix layer BM1 away from the first substrate BS1; and a second substrate BS2, which is located on a side of the ground plate GP and the radiation plate RP away from the first substrate BS1. The first electrode E1 is connected to the drain of the first transistor TFT1. Optionally, the display panel further comprises an overcoat layer OC, which is located on a side of the second electrode E2 away from the first substrate BS1 and on a side of the first black matrix layer BM1 close to the first substrate BS1. Optionally, the display panel further includes a third planarization layer PLN3, which is located on a side of the second alignment layer AL2 away from the first substrate BS1 and on a side of the second electrode E2 close to the first substrate BS1.

[0253] In some embodiments, the fourth electrode E4 of each sub-pixel and the second electrode E2 of each antenna unit are located in the same layer. In some embodiments, the third electrode E3 of each sub-pixel and the first electrode E1 of each antenna unit are located in different layers.

[0254] In some embodiments, the display panel includes a light-transmitting region LTR and an antenna region AR outside the light-transmitting region LTR. In some embodiments, the display panel includes a transistor plate TP; a first conductive layer CT1 located on the transistor plate TP; a first planarization layer PLN1 located on a side of the first conductive layer CT1 away from the transistor plate TP; a second conductive layer CT2 located on a side of the first planarization layer PLN1 away from the transistor plate TP; a liquid crystal layer LC located on a side of the second conductive layer CT2 away from the transistor plate TP; a third conductive layer CT3 located on a side of the liquid crystal layer LC away from the transistor plate TP; a color film CF and a black matrix BM located on a side of the third conductive layer CT3 away from the transistor plate TP; and a radiation plate RP and a ground plate GP located on a side of the color film CF and the black matrix BM away from the transistor plate TP.

[0255] In some embodiments, the third electrode E3 and the fourth electrode E4 are configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR. The first electrode E1 and the second electrode E2 are configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. In some embodiments, the first conductive layer CT1 includes the first electrode E1 located in the antenna region AR. In some embodiments, the second conductive layer CT2 includes the third electrode E3 located in the light transmission region LTR. In some embodiments, the third conductive layer CT3 includes the fourth electrode E4 located in the light transmission region LTR and the second electrode E2 located in the antenna region AR. The fourth electrode E4 and the second electrode E2 are located in the same layer. The third electrode E3 and the first electrode E1 are located in different layers.

[0256] See also Fig. 20 In some embodiments, the orthographic projection of the first electrode E1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the second electrode E2 on the first substrate BS1, thereby forming a capacitor. The inventors of the present disclosure have found that the capacitor helps to maintain the state of the liquid crystal molecules in the liquid crystal layer LC. Optionally, the orthographic projection of the first electrode E1 on the first substrate BS1 substantially covers the orthographic projection of the second electrode E2 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the second electrode E2 on the first substrate BS1 substantially covers the orthographic projection of the first electrode E1 on the first substrate BS1 (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0257] See also Fig. 20In some embodiments, the orthographic projection of the third electrode E3 on the first substrate BS1 at least partially overlaps with the orthographic projection of the fourth electrode E4 on the first substrate BS1. Optionally, the orthographic projection of the third electrode E3 on the first substrate BS1 substantially covers the orthographic projection of the fourth electrode E4 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the first substrate BS1 substantially covers the orthographic projection of the third electrode E3 on the first substrate BS1 (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers).

[0258] Fig.21 is a schematic diagram showing the layout of signal lines and electrodes in a display panel according to some embodiments of the present disclosure. Fig.21 In some embodiments, the display panel includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first data lines DL1, and a plurality of second data lines DL2. The gate of the first transistor TFT1 is connected to a corresponding first gate line among the plurality of first gate lines GL1. The source of the first transistor TFT1 is connected to a corresponding first data line among the plurality of first data lines DL1. The drain of the first transistor TFT1 is connected to the first electrode E1. The gate of the second transistor TFT2 is connected to a corresponding second gate line among the plurality of second gate lines GL2. The source of the second transistor TFT2 is connected to a corresponding second data line among the plurality of second data lines DL2. The drain of the second transistor TFT2 is connected to the third electrode E3.

[0259] Each first data line is configured to provide a first data signal configured to modulate a portion of the liquid crystal layer LC located in the antenna region AR. Each second data line is configured to provide a second data signal configured to modulate a portion of the liquid crystal layer LC located in the light transmission region LTR to display an image. Each first data signal and each second data signal are independent of each other. Optionally, each first data signal and each second data signal are different from each other.

[0260] The first transistor TFT1 and the second transistor TFT2 are independently controlled by the corresponding first gate line and the corresponding second gate line, respectively. Each first gate line is configured to provide each first gate scan signal. Each second gate line is configured to provide each second gate scan signal. Each first gate scan signal and each second gate scan signal are independent of each other. Optionally, each first gate scan signal and each second gate scan signal are different from each other.

[0261] Fig. 22is a plan view of a second electrode, a fourth electrode, a black matrix and a color film in a display panel according to some embodiments of the present disclosure. Fig. 22 In some embodiments, the orthographic projection of the first black matrix layer BM1 on the base substrate substantially covers the orthographic projection of the second electrode E2 on the base substrate (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the second electrode E2 on the base substrate does not substantially overlap with the orthographic projection of the color film CF on the base substrate (for example, does not overlap by at least 80%, does not overlap by at least 85%, does not overlap by at least 90%, does not overlap by at least 95%, does not overlap by at least 99%, or does not overlap at all).

[0262] In some embodiments, the orthographic projection of the color filter CF on the base substrate substantially covers the orthographic projection of the fourth electrode E4 on the base substrate (for example, covers at least 75%, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers). Optionally, the orthographic projection of the fourth electrode E4 on the base substrate does not substantially overlap with the orthographic projection of the black matrix BM on the base substrate (for example, does not overlap by at least 80%, does not overlap by at least 85%, does not overlap by at least 90%, does not overlap by at least 95%, does not overlap by at least 99%, or does not overlap at all).

[0263] Fig.23 is a schematic diagram showing the layout of the ground plate and the radiation plate in the display panel according to some embodiments of the present disclosure. Fig.23 In some embodiments, the ground plate GP is located in an area having the second electrode, and the radiation plate RP is located in an area not including the second electrode. In some embodiments, the orthographic projection of the ground plate GP on the substrate substrate at least partially overlaps with the orthographic projection of the feed line structure (including the second electrode) on the substrate substrate. Optionally, the orthographic projection of the ground plate GP on the substrate substrate substantially covers the orthographic projection of the feed line structure on the substrate substrate (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering). Optionally, the orthographic projection of the feed line structure on the substrate substrate substantially covers the orthographic projection of the ground plate GP on the substrate substrate (for example, covering at least 75%, covering at least 80%, covering at least 85%, covering at least 90%, covering at least 95%, covering at least 99%, or completely covering).

[0264] In some embodiments, the orthographic projection of the radiation plate RP on the substrate substrate does not substantially overlap with the orthographic projection of the feed line structure on the substrate substrate (for example, at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or no overlap at all).

[0265] In some embodiments, the feeder structure includes a plurality of radiating plates respectively in the plurality of antenna units. The plurality of radiating plates are arranged in a plurality of rows. Each row of the plurality of radiating plates is located between two adjacent rows of color filter blocks. Each row of the plurality of radiating plates includes a plurality of radiating plates. Each radiating plate of the plurality of radiating plates is located between two adjacent color filter blocks in the same column of color filter blocks.

[0266] In some embodiments, the ground plate GP includes a plurality of ground bars. Each of the plurality of ground bars is located between two adjacent columns of color film blocks. Optionally, the plurality of ground bars are part of the overall structure. The ground plate also includes a horizontal bar connecting the plurality of ground bars together.

[0267] Various suitable conductive materials can be used to make the first electrode. Examples of suitable conductive materials for making the first electrode include low resistance, low loss metals or alloys, such as copper, gold and silver. Other examples of suitable conductive materials for making the first electrode include transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide and indium gallium zinc oxide.

[0268] Various suitable conductive materials can be used to make the second electrode. Examples of suitable conductive materials for making the second electrode include low resistance, low loss metals or alloys, such as copper, gold and silver. Other examples of suitable conductive materials for making the first electrode include transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide and indium gallium zinc oxide.

[0269] Various suitable conductive materials can be used to make the third electrode. Examples of suitable conductive materials for making the third electrode include various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide.

[0270] Various suitable conductive materials can be used to make the fourth electrode. Examples of suitable conductive materials for making the fourth electrode include various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide.

[0271] Various suitable semiconductor materials can be used to manufacture the active layer of the first transistor. Examples of suitable semiconductor materials for manufacturing the active layer of the first transistor include polycrystalline silicon, amorphous silicon and metal oxides, such as indium gallium zinc oxide, zinc oxide, gallium oxide, indium oxide. Semiconductor materials with high mobility and stability can be achieved by doping with rare earth elements. Examples of rare earth element dopants include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), yttrium (Y) and scandium (Sc).

[0272] In another aspect, the present invention provides a display device, including a display panel described herein or manufactured by a method described herein, and one or more integrated circuits connected to the display panel. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is a liquid crystal display device.

[0273] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A display panel comprising a plurality of sub-pixels and a plurality of antenna units; in, Each antenna unit of the plurality of antenna units includes a first substrate substrate, a first transistor located on the first substrate substrate, a first electrode connected to the first transistor, and a second electrode; The display panel further includes a liquid crystal layer extending through the plurality of sub-pixels and the plurality of antenna units; The first electrode and the second electrode are configured to apply an electric field across a portion of the liquid crystal layer; Each sub-pixel of the plurality of sub-pixels includes the first substrate, a second transistor located on the first substrate, a third electrode connected to the second transistor, and a fourth electrode; The display panel also includes a color film and a black matrix; The color film includes a plurality of color film blocks; The orthographic projection of each color filter block in the plurality of color filter blocks on the first substrate at least partially overlaps with the orthographic projection of the third electrode on the first substrate, and at least partially overlaps with the orthographic projection of the fourth electrode on the first substrate; as well as The orthographic projection of the black matrix on the first substrate at least partially overlaps with the orthographic projection of the first electrode on the first substrate, and at least partially overlaps with the orthographic projection of the second electrode on the first substrate.

2. The display panel according to claim 1, wherein: The orthographic projection of the black matrix on the first substrate substantially covers the orthographic projection of the first electrode on the first substrate, and substantially covers the orthographic projection of the second electrode on the first substrate.

3. The display panel according to claim 1, wherein: The orthographic projection of the color filter on the first substrate does not substantially overlap with the orthographic projection of the first electrode on the first substrate, and does not substantially overlap with the orthographic projection of the second electrode on the first substrate; as well as The orthographic projection of the black matrix on the first base substrate does not substantially overlap with the orthographic projection of the third electrode on the first base substrate, and does not substantially overlap with the orthographic projection of the fourth electrode on the first base substrate.

4. The display panel according to claim 1, further comprising a ground plate and a radiation plate spaced apart from each other; in, The orthographic projection of the black matrix on the first substrate at least partially overlaps with the orthographic projection of the ground plate on the first substrate.

5. The display panel according to claim 4, wherein: The orthographic projection of the black matrix on the first substrate substantially covers the orthographic projection of the ground plate on the first substrate.

6. The display panel according to claim 4, wherein: The orthographic projection of the ground plate on the first substrate does not substantially overlap with the orthographic projection of the third electrode on the first substrate, and does not substantially overlap with the orthographic projection of the fourth electrode on the first substrate; as well as The orthographic projection of the ground plate on the first substrate at least partially overlaps with the orthographic projection of the first electrode on the first substrate, and at least partially overlaps with the orthographic projection of the second electrode on the first substrate.

7. The display panel according to claim 4, wherein: The orthographic projection of the color film on the first substrate at least partially overlaps with the orthographic projection of the radiation plate on the first substrate.

8. The display panel according to claim 7, wherein: The orthographic projection of the radiation plate on the first base substrate partially overlaps with a portion of the black matrix located in an area, in which the first electrode and the second electrode do not exist.

9. The display panel according to claim 4, wherein: The orthographic projection of the radiation plate on the first substrate does not substantially overlap with the orthographic projection of the first electrode on the first substrate, and does not substantially overlap with the orthographic projection of the second electrode on the first substrate; as well as The orthographic projection of the radiation plate on the first substrate at least partially overlaps with the orthographic projection of the third electrode on the first substrate, and at least partially overlaps with the orthographic projection of the fourth electrode on the first substrate.

10. The display panel according to claim 4, wherein: The orthographic projection of the black matrix on the first substrate at least partially overlaps with the orthographic projection of the radiation plate on the first substrate.

11. The display panel according to claim 4, wherein: The orthographic projection of the radiation plate on the first substrate does not substantially overlap with the orthographic projection of the first electrode on the first substrate, and does not substantially overlap with the orthographic projection of the second electrode on the first substrate; as well as The orthographic projection of the radiation plate on the first base substrate does not substantially overlap with the orthographic projection of the third electrode on the first base substrate, and does not substantially overlap with the orthographic projection of the fourth electrode on the first base substrate.

12. The display panel according to claim 1, comprising a light-transmitting area and an antenna area outside the light-transmitting area; in, The display panel includes a transistor plate; a first conductive layer located on the transistor plate; a first planarization layer located on a side of the first conductive layer away from the transistor plate; a second conductive layer located on a side of the first planarization layer away from the transistor plate; the liquid crystal layer located on a side of the second conductive layer away from the transistor plate; a third conductive layer located on a side of the liquid crystal layer away from the transistor plate; the color film and the black matrix located on a side of the third conductive layer away from the transistor plate; and a radiation plate and a ground plate located on a side of the color film and the black matrix away from the transistor plate. The third electrode and the fourth electrode are configured to modulate a portion of the liquid crystal layer located in the light-transmitting area; and The first electrode and the second electrode are configured to modulate a portion of the liquid crystal layer located in the antenna region.

13. The display panel according to claim 12, wherein: The first conductive layer includes the fourth electrode located in the light-transmitting area and the first electrode located in the antenna area; The fourth electrode and the first electrode are located in the same layer; The second conductive layer includes the third electrode located in the light-transmitting area and the second electrode located in the antenna area; and The third electrode and the second electrode are located in the same layer.

14. The display panel according to claim 12, wherein: The first conductive layer includes the fourth electrode located in the light-transmitting area and the first electrode located in the antenna area; The fourth electrode and the first electrode are located in the same layer; The second conductive layer includes the third electrode located in the light-transmitting area; The third conductive layer includes the second electrode located in the antenna area; and The third electrode and the second electrode are located in different layers.

15. The display panel according to claim 12, wherein: The first conductive layer includes the first electrode located in the antenna area; The second conductive layer includes the third electrode located in the light-transmitting area; The third conductive layer includes the fourth electrode located in the light-transmitting area and the second electrode located in the antenna area; The fourth electrode and the second electrode are located in the same layer; and The third electrode and the first electrode are located in different layers.

16. The display panel according to claim 12, wherein: The first conductive layer includes the fourth electrode located in the light-transmitting area; The second conductive layer includes the third electrode located in the light-transmitting area, the first electrode located in the antenna area, and the second electrode located in the antenna area; and The third electrode, the first electrode and the second electrode are located in the same layer.

17. The display panel according to claim 12, wherein: The first conductive layer includes the third electrode and the fourth electrode located in the light-transmitting area, and the first electrode and the second electrode located in the antenna area; and The first electrode, the second electrode, the third electrode and the fourth electrode are located in the same layer.

18. The display panel according to claim 12, wherein: The first conductive layer includes the first electrode located in the antenna area; The second conductive layer includes the third electrode located in the light-transmitting area and the second electrode located in the antenna area; The third conductive layer includes the fourth electrode located in the light-transmitting area; The third electrode and the second electrode are located in the same layer; and The fourth electrode and the first electrode are located in different layers.

19. The display panel according to claim 12, wherein: The second conductive layer includes the first electrode and the second electrode located in the antenna area, and the third electrode located in the light-transmitting area; The third conductive layer includes the fourth electrode located in the light-transmitting area; and The first electrode, the second electrode and the third electrode are located in the same layer.

20. A display device comprising a display panel according to any one of claims 1 to 19, and one or more integrated circuits connected to the display panel.

Images