TSV semiconductor device including inductance compensation loop

Abstract

A semiconductor device includes a semiconductor die formed with a through-silicon via (TSV). The TSVs are coupled to contact pads in a surface of the semiconductor die by forming coils of an inductive loop at a plurality of contact pads. These inductive loops are used to distribute capacitance at each bond pad along the transmission line, such capacitance distribution making it possible to significantly increase the read / write bandwidth of the semiconductor die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 222,632, filed with the U.S. Patent and Trademark Office on July 17, 2023, entitled “TSV SEMICONDUCTOR DEVICE INCLUDING INDUCTIVE COMPENSATION LOOPS,” and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 435,310, filed on December 26, 2022. Background Art

[0003] Strong growth in demand for portable consumer electronic devices has driven the need for high-capacity memory devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, have been widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, and rugged design, as well as their high reliability and large capacity, make such memory devices very suitable for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular phones, and solid-state drives.

[0004] The semiconductor memory may be disposed within a semiconductor package that protects the semiconductor memory and enables communication between the memory and a host device. Examples of semiconductor packages include a system-in-package (SiP) or a multi-chip module (MCM), in which multiple dies are mounted and interconnected on a small footprint substrate. The dies in such packages are typically stacked in a stepped offset pattern so that the die bonding pads of each die are exposed at the stepped edge of the die stack. Wire bonds may then be formed between corresponding die bonding pads of the dies in the die stack and the wire bonds may be formed to the substrate to enable signal exchange to / from a selected die in the die stack.

[0005] Some memory and IC companies are turning from wire bonding to technology using through silicon vias (TSVs), in which wire bonding is replaced by metal or conductive traces that pass through the wafer or die from top to bottom. This enables wafers or chips to be stacked on top of each other and electrically and mechanically bonded. TSV interconnects have many advantages, such as higher pin-out counts, lower impedance that enables higher data rates, reduced die size, and shortened interconnect lengths, thereby improving latency. Although TSV interconnects provide improved bandwidth compared to traditional wire-bonded semiconductor packages, the direct connection of contact pads between stacked semiconductor dies in the package results in parasitic capacitance in the package. Since capacitance is inversely proportional to input / output frequency and bandwidth, higher bandwidth performance is currently required in today's semiconductor packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a flow chart for forming a semiconductor device according to an embodiment of the present technology.

[0007] Figure 2 is a plan view of a first main surface of a semiconductor wafer according to an embodiment of the present technology.

[0008] Figure 3 According to the implementation scheme of the present technology Figure 2 A plan view of the semiconductor die of the wafer is shown.

[0009] Figure 4 is a plan view of a cross section through a semiconductor die showing inductive loops associated with certain die bond pads in accordance with an embodiment of the present technology.

[0010] Figure 5A and Figure 5B is an enlarged view of a semiconductor die and associated inductive loop and I / O circuitry in accordance with an embodiment of the present technology.

[0011] Figure 6 is a cross-sectional view of a semiconductor die showing through-silicon vias associated with each contact pad and inductive loop in accordance with an embodiment of the present technology.

[0012] Figure 7 is a diagram showing an embodiment of the present technology. Figure 5A Circuit diagram of the input / output circuit associated with the inductive loop.

[0013] Figure 8 is an enlarged view of a semiconductor die and associated inductive loop according to an alternative embodiment of the present technology.

[0014] Fig. 9is an enlarged view of a semiconductor die and associated inductive loop according to a further alternative embodiment of the present technology.

[0015] Fig.10 is a diagram showing an embodiment of the present technology. Figure 8 Circuit diagram of the input / output circuit associated with the inductive loop.

[0016] Fig.11 is a flow chart for forming a semiconductor device using a semiconductor die according to an embodiment of the present technology.

[0017] Fig.12 is a perspective view of a semiconductor device at a first fabrication stage with a semiconductor die stacked on a substrate in accordance with an embodiment of the present technology.

[0018] Fig.13 is an edge view of a complete semiconductor device according to an embodiment of the present technology.

[0019] Fig.14 is a plan view of a complete semiconductor device according to an alternative embodiment of the present technology.

[0020] Fig.15 is based on Fig.14 A perspective view of a complete semiconductor device of an alternative embodiment.

[0021] Fig.16 is a circuit diagram of a complete semiconductor device including multiple semiconductor dies according to an embodiment of the present technology.

[0022] Fig.17 is a graph illustrating the input / output bandwidth of a complete semiconductor device according to an embodiment of the present technology. DETAILED DESCRIPTION

[0023] The present technology will now be described with reference to the accompanying drawings, which in embodiments relate to a semiconductor device including a semiconductor die formed with through silicon vias (TSVs). The TSVs are coupled to contact pads in the surface of the semiconductor die by forming coils of inductive loops at a plurality of contact pads. These inductive loops are used to distribute capacitance at each bonding pad along a transmission line, and this capacitance distribution makes it possible to significantly increase the read / write bandwidth of the semiconductor die.

[0024] It should be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and the present invention will be fully communicated to those skilled in the art. In fact, the present invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are all included in the scope and essence of the present invention as defined by the appended claims. In addition, in the following specific embodiments of the present invention, many specific details are given in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention can be implemented without such specific details.

[0025] The terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal" and their forms as used herein, as may be used herein only by way of example and for purposes of illustration, and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. In addition, as used herein, the terms "substantially" and / or "approximately" mean that the specified dimension or parameter may vary within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±1.5 mm or alternatively ±2.5% of a given dimension.

[0026] For purposes of this disclosure, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when a first element is referred to as being connected, attached, mounted, or coupled to a second element, the first element and the second element may be directly connected, attached, mounted, or coupled to each other or indirectly connected, attached, mounted, or coupled to each other. When a first element is referred to as being directly connected, attached, mounted, or coupled to a second element, there are no intermediate elements between the first element and the second element (except for an adhesive or molten metal that may be used to connect, attach, mount, or couple the first element and the second element).

[0027] Now refer to Figure 1 and Fig.11 Flowchart and Figures 2 to 10 and Figures 12 to 17 In step 200, the semiconductor wafer 100 can be processed into Figure 2 A plurality of semiconductor dies 102 are shown. Although not critical to the present technology, semiconductor wafer 100 may begin with an ingot of wafer material, which may be single crystal silicon grown according to a Czochralski (CZ) or a floating zone (FZ) process. In other embodiments, wafer 100 may be formed of other materials and by other processes.

[0028] The semiconductor wafer 100 may be cut from the ingot and polished on both the first main surface (active surface) 104 and the second main surface (not shown, inactive surface) opposite the surface 104 to provide a smooth surface. In step 200, the first main surface 104 may undergo various processing steps to separate the wafer 100 into respective semiconductor dies 102 and to form integrated circuits of the respective semiconductor dies 102 on and / or in the first main surface 104. Figure 2 The number of semiconductor dies 102 shown is for illustration purposes only, and the number of dies 102 may vary in different implementations of wafer 100 .

[0029] Semiconductor die 102 may be, for example, a memory die such as 2D NAND flash memory or 3D BiCS (bit cost scaling), V-NAND or other 3D flash memory. However, die 102 may be other types of dies, including, for example, a controller die such as an ASIC, or a RAM such as SDRAM, DDR SDRAM, LPDDR, and GDDR.

[0030] The various processing steps may also include a back-end of the line (BEOL) step 202 of forming metallization layers in and on the semiconductor die 102. The metallization step 202 may also include depositing metal contacts including contact pads 106, 108 exposed on the first major surface 104. The metallization step may also include depositing metal interconnect layers and vias within the wafer. These metal interconnect layers and vias may be provided for passing signals to and from the integrated circuit and providing known structural support for the integrated circuit.

[0031] The contact pads include low frequency contact pads 106, for example, used as power and ground contacts in semiconductor die 102. The contact pads may also include high frequency contact pads 108, for example, used to pass input / output (I / O) signals to and from semiconductor die 102. Figure 3 An example of a semiconductor die 102 is illustrated that includes a row of low-frequency contact pads 106 and a plurality of rows of high-frequency contact pads 108. However, the number and positioning of contact pads 106 and contact pads 108 are for illustration purposes only and may vary in different implementations of semiconductor die 102. Some of signal pads 108 may also be low-frequency logic pads.

[0032] According to aspects of the present technique, metallization step 202 may also include forming a coil adjacent to contact pad 108 and below major planar surface 104, such as at Figure 41 through the semiconductor die 102. These coils form an inductive loop 110 that is used to distribute the capacitance, thereby increasing the read / write bandwidth as described below. Each contact pad 108 (whether high frequency or low frequency) can be coupled to an associated inductive loop 110. In an embodiment, the low frequency power supply contact pad 106 does not have an associated inductive loop 110. However, in other embodiments, one or more contact pads 108 may not have an associated inductive loop 110, and one or more low frequency contact pads 106 may have an associated inductive loop 110.

[0033] The structure and position of the inductive loop 110 relative to the contact pad 108 may vary in various embodiments, but in one example, each inductive loop may include one or more planar coils formed in a single metallization layer. In an embodiment, the one or more coils of the inductive loop may include, for example, 1 to 6 coils, including, for example, 2 coils. The width and depth of each coil may be, for example, 1 micrometer (μm) to 10 μm, such as, for example, 3 μm, and each coil may be spaced 1 μm to 10 μm from the next inner coil or outer coil, such as, for example, 3 μm. In other embodiments, the number of coils and each of the above-mentioned sizes and spacings of the coils may vary outside the range. The inductive loop 110 may be formed, for example, of copper or aluminum, but may be formed of other materials in other embodiments. These other materials include, but are not limited to, gold, silver, tungsten, and alloys of these metals (including alloys of copper and / or aluminum).

[0034] Figure 5A and Figure 5B is an enlarged view of a single contact pad 108 and inductive loop 110 . Figure 6 1 is a cross-sectional edge view of a semiconductor die 102 including an inductive loop 110. The one or more coils forming the inductive loop 110 may be spirally wound. The innermost portion of the coils of the inductive loop 110 may define an open central region 112, which in an embodiment may have a width of 10 μm to 30 μm, such as, for example, 20 μm. In other embodiments, the open central region may be smaller or larger than this. Figure 5A In an embodiment, the inductive loop 110 can be formed to one side of the contact pads 108. In one embodiment, the center-to-center spacing of the contact pads 108 can be 100 μm. In such an embodiment, the width of the inductive loop 110 can be 50 μm, positioned between adjacent contact pads 108. The inductive loop 110 can have a conductive trace 114 ( Figure 5A and Figure 6 ) is electrically coupled to the first end of the contact pad 108. The inductive loop 110 may have a conductive hole 116 ( Figure 6and enter Figure 5A The conductive trace 114, 118 and the hole 116 may be formed in a metallization step 202 during which the inductive loop 110 is formed.

[0035] exist Figure 5A In the embodiment of the present invention, the inductor is placed after the capacitive load of the I / O circuit 122. The inductor 110 and the capacitor in the circuit 122 are connected to the TSV 120 through the via 116 and the conductive trace 118. Then, the other side of the inductor 110 is connected to the pad 108 through the conductive trace 114. Figure 5B Another embodiment is shown in which the inductor is placed before the capacitive load of the I / O circuit 122. Figure 5B In the embodiment of the present invention, the inductor 110 and the capacitor in the circuit 122 are connected to the pad 108 through the conductive trace 114. Then, the other side of the inductor 110 is connected to the TSV 120 through the via 116 and the conductive trace 118.

[0036] exist Figure 6 In the embodiment of FIG. 1 , a 5-bit bus structure including 5 bit lines is shown. A complete bit line is shown within box 130 and includes contact pad 108, inductive loop 110, TSV 130 and electrical connectors 114, 116 and 118. Although Figure 6 A 5-bit bus structure (with 5 bit lines) is shown, but this is for illustration purposes only, and in alternative embodiments, other numbers of bit lines may be present in the bus structure, including, for example, 8 bit lines.

[0037] The coil of the inductive loop 110 may be formed at a depth of 10 μm to 100 μm below the surface 104 of the semiconductor die 102. In this embodiment, the depth of the contact pad 108 may be greater than or equal to the depth of the coil of the inductive loop. Therefore, the coil of the inductive loop may be coupled to the contact pad 108 with a first electrical connector consisting of a horizontal conductive trace 114. The TSV 120 may have a base 120a that extends to a depth lower than the depth of the coil of the inductive loop 110. Therefore, the coil of the inductive loop may be coupled to the TSV 120 with a second electrical connector consisting of a vertical hole 116 and a horizontal conductive trace 118.

[0038] However, it should be understood that the depth of the coil of the inductive loop 110 between the opposing surfaces of the semiconductor die 102 may be different in other embodiments. For example, the depth of the coil may be greater than the depth of the contact pad 108 but less than the depth of the base 120a of the TSV 120 (i.e., positioned at a depth between the contact pad 108 and the TSV base 120a). In such embodiments, the coil of the inductive loop may be coupled to the contact pad 108 with a first electrical connector consisting of a vertical hole and a horizontal conductive trace, and the coil of the inductive loop may be coupled to the TSV 120 with a second electrical connector consisting of a vertical hole and a horizontal conductive trace. In another embodiment, the depth of the coil may be greater than the depth of the contact pad 108 and greater than or equal to the depth of the base 120a of the TSV 120 (i.e., positioned at a depth along the length of the TSV 120). In such embodiments, the coil of the inductive loop may be coupled to the contact pad 108 with a first electrical connector comprised of a vertical via and a horizontal conductive trace, and the coil of the inductive loop may be coupled to the TSV 120 with a second electrical connector comprised of a horizontal conductive trace.

[0039] The inductive loop 110 including the coil, traces 114, 118 and holes 116 and other metal interconnect layers and holes may be formed in a continuous damascene process or a dual-damascene process, wherein a dielectric substrate material is applied in a deposition process, patterned and filled with a metal to form a horizontal planar metal layer and a vertical hole. The deposition process may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrografting (eG). The inductive loop 110 may be formed in any of the various metallization layers of the semiconductor die 102. In an embodiment, the inductive loops 110 associated with all contact pads 108 may each be formed in the same metallization layer or in multiple metallization layers. In yet other embodiments, a single contact pad 108 may have multiple associated inductive loops 110 formed in different metallization layers, each coupled to each other, the contact pad 108 , and the TSV 120 .

[0040] The conductive loops 110 associated with the various high frequency signal contact pads 108 are used to distribute and otherwise compensate for the total capacitance associated with read / write operations of the semiconductor die 102 . Figure 7 1 is a circuit diagram showing components of I / O circuit 122 formed in an integrated circuit with semiconductor die 102. I / O circuit 122 includes a power supply voltage V DD and ground voltage V SS , and having capacitive elements such as C respectively composed of P-MOS circuit elements and N-MOS circuit elementsP and C N The magnetic field that causes the current to be stored in the inductive loop 110 will be used to distribute and reduce the current stored as a capacitor such as C P and capacitor C N As described below, after completion, multiple semiconductor dies can be stacked and electrically interconnected through TSVs 120. Adding the inductive loop 110 associated with the high frequency signal contact pads 108 changes the lumped sum of the total capacitance of each die (the number of dies in the stack multiplied by the capacitance of each die). By adding a series inductor (L) at each die, the capacitance (C) is distributed to form a transmission line. Wherein, the transmission line terminates at the end die at the top of the die stack. It is well known that greater capacitance is a factor that limits the I / O bandwidth. Without the addition of series inductance (L), the capacitance may have to be considered as the lumped capacitance of all the connected dies. Therefore, by distributing the capacitance, the present technology allows a significant increase in bandwidth.

[0041] As previously mentioned, in alternative embodiments of the present technology, the inductive loop 110 may be disposed in various locations and in different structures. Figure 8 An embodiment is illustrated in which the inductive loop 110 is positioned below and generally centered relative to the contact pad 108. This embodiment can be used, for example, where the thickness of the semiconductor die is such that there can be sufficient vertical spacing between the contact pad 108 and the inductive loop 110 so that the added capacitance is not an issue.

[0042] Fig. 9 An embodiment is illustrated in which the inductive loop 110 includes a center-tapped spiral having coils 110a and 110b. Fig. 9 The dashed line segments of the inductive loop 110 shown represent portions of the coils 110a and 110b that are in a different horizontal plane than other portions of the coils 110a and 110b. Fig. 9 The portions of the coils 110a and 110b that are in different planes are coupled to each other. Fig.10 As shown in the I / O circuit diagram 125 in FIG. 1 , this configuration of coils 110a and 110b implements a pair of inductors connected in series with each other. Compared to the embodiment shown in FIG. 5 , for example, this configuration implements a larger amount of current storage in the inductive loop 110 and enables more compensation of the capacitor voltage.

[0043] Reference again Figure 1After the metallization step 202 of forming the inductive loop 110 according to the present technology, the semiconductor wafer can then be flipped over and supported on a wafer carrier (not shown) in step 204. In step 206, the wafer can be thinned in a back grinding process to a final thickness of, for example, 25 μm to 36 μm, although the wafer can be thinner or thicker than in other embodiments. The wafer can be thinned using, for example, a grinding wheel. In step 210, a layer of die attach film (DAF) 123 ( Figure 6 ) is applied to the back (inactive) surface of the wafer. Alternatively, the adhesive material in liquid form can be applied to the back surface by spin coating, followed by a baking process.

[0044] In step 214, TSVs 120 may be formed through the back surface of wafer 100 and DAF layer 123. Further details of step 214 will now be explained with reference to steps 218 to 226. In step 218, a photoresist layer may be applied over DAF layer 123 and patterned by removing photoresist regions over sections of die 102 where TSVs 120 are to be formed. These regions correspond to the locations of contact pads 106 and / or 108.

[0045] In step 220, a hole is formed at the removed photoresist area. The hole corresponding to the contact pad 108 can be formed to a predetermined depth toward the front surface 104 of the wafer 100, for example, 5 μm to 50 μm vertically spaced from the planar layer including the inductive loop 110. In addition, the hole is formed at a position so that the conductive trace 118 (Figures 5 and Figure 6 ) exposes a hole in the metallization layer. In one example, the hole can be etched by deep reactive ion etching (DRIE) or other anisotropic etching process.

[0046] In steps 224 and 226, the holes may be plated and / or filled to form TSV 120. In an embodiment, seed layer 124 ( Figure 6 ) is deposited on all surfaces within the cavity. The seed layer can be any of a variety of conductive materials such as copper deposited by a variety of techniques including physical vapor deposition (PVD) or electrografting (eG). Figure 6 As shown, in step 226, electrical conductors 126 may be formed on the seed layer to fill or plate TSVs 120 and complete the formation of TSVs 120. Electrical conductors 126 may be various conductive materials, including, for example, copper or tungsten, applied by various processes including electroplating or with solder utilizing capillary action.

[0047] The order of the steps described above is not limiting of the present technology, and the steps may be performed in other orders in other embodiments. For example, in one embodiment, the TSV 120 may be formed first, and then the integrated circuit and metallization layers including the contact pads 106, 108 and the inductor coil 110 may be formed.

[0048] Here, in one embodiment, semiconductor die 102 may be diced from wafer 100 using known dicing methods such as by blade, laser, water jet, etc. in step 228. Wafer 100 may be flipped and attached to a dicing tape. As will now be referenced Fig.11 Flowchart and Figures 12 to 17 As explained in the view of FIG. 1 , the carrier may be removed and then a pick-and-place robot may pick up a single semiconductor die 102 and package the single semiconductor die into a semiconductor device.

[0049] First reference Fig.12 1 , in step 230, a semiconductor device 150 may be formed by mounting a plurality of semiconductor dies 102 on a substrate 152 to form a die stack 154. The dies may be attached to each other and to the substrate 152 via a DAF layer 123 on the bottom surface of each die, cured to a B stage to initially attach the dies 102 in the stack 154, and then cured to a final C stage to permanently attach the dies 102 in the stack 154.

[0050] Although the illustrated embodiment includes four semiconductor dies 102-0 to 102-3, embodiments may include different numbers of semiconductor dies in die stack 154, including, for example, 1, 2, 4, 8, 16, 32, or 64 dies. In other embodiments of stack 154, other numbers of dies may be present. As described above, semiconductor die 102 is fabricated to include TSVs 120. Thus, when die 102 is added to the stack, the TSVs 120 of the die are physically and electrically coupled to contact pads 106 and / or 108 of the semiconductor die directly below. Substrate 152 includes contact pads 156 ( Fig.13 ) such that the TSV 120 of the bottommost semiconductor die 102-0 in the stack is physically and electrically coupled to the contact pad 156 on the substrate 152.

[0051] In view of the use of TSVs 120 to manufacture die 102, in the case of including multiple semiconductor dies 102, semiconductor dies 102 may be stacked directly on top of each other without offset or spacing to form die stack 154. Therefore, the footprint of die stack 154 on substrate 152 is the same size as the footprint of a single die 102.

[0052] In step 232, a controller die 160, such as an ASIC, may be mounted on the substrate 152 for controlling data transfer between the semiconductor device 150 and a host device (not shown), such as a printed circuit board. The controller die 160 is shown as being wire bonded to the substrate 152 next to the die stack 154. However, in other embodiments, the controller die may be electrically coupled to the substrate 152 by other methods, including flip chip bonding. Although not shown, one or more passive components may also be attached to the substrate 152. The one or more passive components may include, for example, one or more capacitors, resistors, and / or inductors, although other components are also contemplated.

[0053] In step 234, the device 150 may be encapsulated in a molding compound 162, such as Fig.13 1. A molding compound 162 may be applied to encapsulate and protect the semiconductor die 102, 160. The molding compound 162 may include, for example, a solid epoxy resin, a phenolic resin, fused silica, crystalline silica, carbon black, and / or a metal hydroxide. Other molding compounds are contemplated. The molding compound may be applied by various known processes, including by FFT (no flow thin) molding, compression molding, transfer molding, or injection molding techniques.

[0054] In step 236, solder balls (not shown) may be applied to the bottom surface of substrate 152 to attach semiconductor device 150 to a host device such as a printed circuit board. Step 236 is shown in phantom because it may be omitted in alternative embodiments.

[0055] The semiconductor devices 150 may be assembled simultaneously on a panel of substrates 152 to achieve economies of scale. In step 240, the substrates 152 may be cut from the panel to form Fig.13 A finished semiconductor device 150 is shown.

[0056] Fig.14 and Fig.15 1 and 10 are plan and perspective views, respectively, of an alternative embodiment of a semiconductor device 170 that can be assembled using semiconductor die 102 manufactured as described above. Die 102 can be mounted into die stack 172 such that when die 102 is added to the stack, the TSVs 120 of the die are physically and electrically coupled to the contact pads 106 and / or 108 of the semiconductor die directly below. In this embodiment, the substrate can be omitted, and the die stack itself forms the finished semiconductor device 170. Although the illustrated embodiment includes 4 semiconductor dies, embodiments can include different numbers of semiconductor dies in die stack 172, including, for example, 1, 2, 4, 8, 16, 32, or 64 dies. In other embodiments of stack 172, other numbers of dies can be present.

[0057] In this embodiment, solder balls 176 may be placed on the top surface and / or the bottom surface of semiconductor device 170 . Fig.14 An example is shown in which solder balls 176 are attached to contact pads 106 and / or 108 on a first (top) surface of semiconductor device 170 . Fig.15 An example is shown in which solder balls 176 are mounted on TSVs 120, the solder balls being exposed on the second (bottom) surface of semiconductor device 170 through DAF layer 123. Semiconductor device 170 of any one embodiment may be mounted to a host device such as a printed circuit board through solder balls 176. Using solder balls 176 on the top and bottom surfaces of semiconductor device 170 may make it possible to mount the semiconductor device to a printed circuit board and then mount the second semiconductor device 170 on top of the first semiconductor device.

[0058] Fig.16 1 is a circuit diagram 180 of semiconductor devices 150 and 170 for passing current between a top semiconductor die (TermG1) and a bottom semiconductor die (TermG2) in an embodiment including four semiconductor dies. The circuit diagram 180 illustrates the bit lines 130 ( 130 ) electrically coupled to each other through the TSVs 120 and the contact pads 108 in each die 102 in the die stack 154, 172. Figure 6 ) circuit flow. Each inductive loop 110 in the channel is shown as an inductor 182 in the circuit diagram 180. Capacitor 184 represents the capacitance of the circuit and the contact pad capacitance of all the dies in the stack 154, 172. Fig.16 In the embodiment, the inductor 182 is placed before the capacitor 184 in each semiconductor die (e.g. Figure 5B shown).

[0059] Fig.17 is through Fig.16 The circuit diagram 180 depicts a graph of the bandwidth of a single channel of TSV 120 and contact pad 108. In one example, the TSV capacitance value of the signal channel at each node can be 0.6pF. The inductance of each inductor 182 in the circuit diagram can be greater than or equal to 200pH. The inductance of inductor 182 can be higher in other embodiments, such as up to 600pH, or can be less than 200pH. Fig.17 As shown, by using these values, the inductor compensated circuit enables a bandwidth through the channel of approximately 12.6 GHz. This represents a significant improvement over conventional frequencies, for example five times higher than what can be achieved in a similar circuit without inductor compensation.

[0060] In summary, the present technology relates to a semiconductor die, which includes: a first surface, a second surface and a depth between the first surface and the second surface; a contact pad, which is formed in the first surface of the semiconductor die; a through-silicon via, which is formed to pass through the second surface of the semiconductor die and extend through the depth toward the first surface; and an inductive loop, which is formed in the depth of the semiconductor die, and the inductive loop includes: one or more coils, which are made of a spirally wound conductive material; a first electrical connector, which electrically couples a first end of the inductive loop to the contact pad; and a second electrical connector, which electrically couples a second end of the inductive loop to the through-silicon via.

[0061] In another example, the present technology relates to a semiconductor device, which includes: a plurality of semiconductor die, each semiconductor die including: a contact pad formed in a first surface of the semiconductor die; a through-silicon via formed to pass through a second surface of the semiconductor die opposite to the first surface, the through-silicon via extending through a depth of the semiconductor die toward the first surface; and an inductive loop formed in the depth of the semiconductor die, the inductive loop including: one or more coils made of a spirally wound conductive material; a first electrical connector electrically coupling a first end of the inductive loop to the contact pad; and a second electrical connector electrically coupling a second end of the inductive loop to the through-silicon via; wherein the through-silicon via of a first semiconductor die among the plurality of semiconductor die is physically and electrically coupled to the contact pad of a second semiconductor die positioned directly below the first semiconductor die.

[0062] In another example, the present technology relates to a semiconductor die, comprising: a contact pad formed in a first surface of the semiconductor die, wherein the contact pad comprises a high-frequency signal pad for input / output signal transmission; a through-silicon via formed to pass through a second surface of the semiconductor die opposite to the first surface, the through-silicon via extending through the depth of the semiconductor die toward the first surface; and a device electrically coupled to the contact pad and the through-silicon via, the device being used to store current in a magnetic field so that capacitance is distributed within the semiconductor die.

[0063] The above specific embodiments of the present invention have been proposed for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In light of the above teachings, many modifications and variations are possible. The described embodiments are selected to best illustrate the principles of the present invention and its practical application, so that other technical personnel in the field can best use the present invention with various modifications suitable for the specific purpose envisioned in various embodiments. The scope of the present invention is intended to be limited by the appended claims.

Claims

1. A semiconductor die, comprising: a first surface, a second surface, and a depth between the first surface and the second surface; a contact pad formed in the first surface of the semiconductor die; a through silicon via formed through the second surface of the semiconductor die and extending through the depth toward the first surface; and an inductive loop formed in the depth of the semiconductor die, the inductive loop comprising: one or more coils made of a helically wound conductive material, a first electrical connector electrically coupling a first end of the inductive loop to the contact pad, and A second electrical connector electrically couples a second end of the inductive loop to the through silicon via.

2. The semiconductor die of claim 1, wherein: The one or more coils are planar coils.

3. The semiconductor die of claim 1 , wherein: The semiconductor die further includes a metallization layer, and wherein the inductive loop is formed in the metallization layer of the semiconductor die.

4. The semiconductor die of claim 1 , wherein: The semiconductor die also includes a metallization layer, and wherein the one or more coils include a plurality of coils formed in different ones of the metallization layers.

5. The semiconductor die of claim 1, wherein: The inductive loop is positioned to the side of the contact pad.

6. The semiconductor die of claim 1, wherein: The inductive loop is positioned beneath the contact pad.

7. The semiconductor die of claim 1, wherein: The inductive loop includes a center-tapped spiral including a plurality of coils.

8. The semiconductor die of claim 7, wherein: Portions of the plurality of coils are positioned at different depths within the semiconductor die.

9. The semiconductor die of claim 1, wherein: The inductive loop is positioned at a depth that is less than or equal to a depth of the contact pad.

10. The semiconductor die of claim 1, wherein: The inductive loop is positioned at a depth greater than or equal to a depth of a base of the through silicon via.

11. The semiconductor die of claim 1, wherein: The inductive loop is positioned at a depth greater than a depth of the contact pad and less than a depth of a base of the TSV.

12. The semiconductor die of claim 1, wherein: The first electrical connector includes one or more of a conductive trace and a hole.

13. The semiconductor die of claim 1, wherein: The second electrical connector includes one or more of a conductive trace and a hole.

14. A semiconductor device, comprising: A plurality of semiconductor dies, each semiconductor die comprising: a contact pad formed in the first surface of the semiconductor die, a through silicon via formed through a second surface of the semiconductor die opposite the first surface, the through silicon via extending through a depth of the semiconductor die toward the first surface, and an inductive loop formed in the depth of the semiconductor die, the inductive loop comprising: one or more coils made of a helically wound conductive material, a first electrical connector electrically coupling a first end of the inductive loop to the contact pad, and a second electrical connector electrically coupling a second end of the inductive loop to the through silicon via; The through silicon via of a first semiconductor die among the plurality of semiconductor dies is physically and electrically coupled to the contact pad of a second semiconductor die positioned directly below the first semiconductor die.

15. The semiconductor device according to claim 14, wherein: The contact pads of each of the semiconductor dies include high frequency signal pads for input / output signal transfer.

16. The semiconductor device according to claim 15, wherein: The inductive loop enables the high frequency signal pad to perform input / output signal transfer at a rate of 12.6 GHz.

17. The semiconductor device according to claim 14, wherein: The plurality of semiconductor dies are stacked directly on top of each other.

18. The semiconductor device of claim 18, further comprising a substrate to which the plurality of stacked semiconductor dies are physically and electrically attached.

19. The semiconductor device according to claim 14, wherein: The one or more coils include a pair of coils forming a pair of inductors connected in series with each other.

20. A semiconductor die, the semiconductor die comprising: contact pads formed in the first surface of the semiconductor die, wherein the contact pads include high frequency signal pads for input / output signal transfer; a through silicon via formed through a second surface of the semiconductor die opposite the first surface, the through silicon via extending through a depth of the semiconductor die toward the first surface, and Means are electrically coupled to the contact pad and the through silicon via, the means for storing current in a magnetic field to distribute capacitance within the semiconductor die.

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