Three-dimensional cross point non-volatile memory

Abstract

A non-volatile memory having a 3D cross point architecture and double cell density is provided in which vertically stacked word lines extend coplanar (i.e., parallel) with the substrate, and bit lines extend perpendicular to the vertically stacked word lines. The vertically stacked word lines are in a patterned stack of dielectric material that includes alternating first layers of dielectric material and recessed second layers of dielectric material. A first dielectric material layer vertically separates each word line within each vertical stack of word lines, and a recessed second dielectric material layer is positioned laterally adjacent to the word lines. The dielectric switch material layer is located between each word line-bit line combination. Some of the bit lines are in the dielectric material stack, and some of the bit lines are in the interlayer dielectric material layer.

Description

Background Art

[0001] The present invention relates to semiconductor technology, and more particularly, to a non-volatile memory having a three-dimensional (3D) cross-point architecture and a method of forming the same.

[0002] Non-volatile memory (NVM) or non-volatile storage is a type of computer memory that retains stored information even after power is removed. In contrast, volatile memory requires a constant power supply in order to retain data. NVM, such as resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM), are gaining renewed attention due to their potential applications in neuromorphic computing with in-memory processing capabilities, which significantly reduces power consumption and eliminates the data bus connection time between the memory and the central processing unit (CPU) based on traditional complementary metal oxide semiconductor (CMOS).

[0003] ReRAM (or sometimes called RRAM) is considered a promising technology for electronic synaptic devices or memristors for neuromorphic computing and high-density and high-speed NVM applications. In neuromorphic computing applications, resistive memory devices such as ReRAM devices can be used as connections (i.e., synapses) between pre-neurons and post-neurons, with the connection weight represented in the form of device resistance.

[0004] Cross-point memory architectures, especially 3D cross-point ReRAM architectures, are particularly attractive. In cross-point memory, memory cells appear at the overlap between word lines and bit lines. Specifically, storage element material, such as conductive filaments in the case of ReRAM, is provided between the word lines and the bit lines. 3D cross-point architectures provide density improvements over non-3D cross-point architectures by stacking memory cells layer by layer. Summary of the invention

[0005] A NVM with a 3D crosspoint architecture and twice the cell density is provided, wherein vertically stacked word lines extend coplanar (i.e., parallel) with a substrate, and bit lines extend perpendicular to the vertically stacked word lines. The vertically stacked word lines are located in a patterned dielectric material stack, the patterned dielectric material stack comprising alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layer vertically separates each word line within each vertical stack of word lines, and the recessed second dielectric material layer is positioned laterally adjacent to the word line. A dielectric switch material layer is located between each word line-bit line combination. Some bit lines are located in the dielectric material stack, and some bit lines are located in the interlayer dielectric material layer.

[0006] In one aspect of the present application, a NVM cell with a 3D crosspoint architecture is provided. In one embodiment, the NVM cell includes a plurality of vertically stacked word lines extending parallel to the topmost horizontal surface of a substrate, wherein each of the plurality of vertically stacked word lines is vertically separated by a first dielectric material layer, and each of the plurality of word lines has a first sidewall contacting a second dielectric material layer and a second sidewall opposite to the first sidewall contacting an interlayer dielectric material layer, wherein the second dielectric material layer has a lateral width less than a lateral width of the first dielectric material layer. At least one first bit line is located in a dielectric material stack including a portion of each first dielectric material layer and each second dielectric material layer, and at least one second bit line is located in the interlayer dielectric material layer. According to the present application, at least one first bit line and at least one second bit line extend perpendicular to the plurality of vertically stacked word lines and are in direct contact with the topmost horizontal surface of the substrate. A dielectric switching material layer is located on sidewalls of both at least one first bit line and at least one second bit line, wherein the dielectric switching material layer surrounding the first bit line separates the first bit line from each of a plurality of vertically stacked word lines, and the dielectric switching material layer surrounding the second bit line separates the second bit line from each of the plurality of vertically stacked word lines.

[0007] In an embodiment of the present application, the second sidewall of each word line is vertically aligned with the outermost sidewall of each first dielectric material layer.

[0008] In an embodiment, the first dielectric material layer is composed of a dielectric material that is compositionally different from the dielectric material providing the second dielectric material layer. In one example, the first dielectric material is composed of silicon dioxide and the second dielectric material is composed of silicon nitride.

[0009] In an embodiment of the present application, a bottommost word line of the plurality of vertically stacked word lines is spaced apart from the substrate by a bottommost first dielectric material layer.

[0010] In an embodiment of the present application, each word line, at least one first bit line, and at least one second bit line are composed of an oxygen-deficient conductive material.

[0011] In an embodiment of the present application, the dielectric switching material layer is composed of dielectric metal oxide.

[0012] In an embodiment of the present application, the substrate includes one or more selector devices.

[0013] In an embodiment of the present application, the at least one first bit line includes a plurality of first bit lines, and the at least one second bit line includes a plurality of second bit lines.

[0014] In an embodiment of the present invention, at least one first bit line and at least one second bit line are arranged in the same row.

[0015] In an embodiment of the present application, at least one first bit line has a topmost surface coplanar with a topmost surface of each of at least one second bit line and the interlayer dielectric material layer.

[0016] In another aspect of the present application, a method for forming an NVM cell having a 3D crosspoint architecture is provided. In one embodiment, the method includes providing at least one patterned dielectric material stack, the at least one patterned dielectric material stack including alternating first and second dielectric material layers located on top of a substrate. Next, each second dielectric material layer of the at least one patterned dielectric material stack is recessed to provide a recessed second dielectric material layer. Then, a word line is formed laterally adjacent to each recessed second dielectric material layer. Then, an interlayer dielectric (ILD) material layer is formed laterally adjacent to at least one patterned dielectric material stack. Next, a first set of openings is formed in each first dielectric material layer and each recessed second dielectric material layer of the at least one patterned dielectric material stack, and a second set of openings is formed in the ILD material layer, wherein the first set of openings and the second set of openings physically expose the substrate. A dielectric switching material layer is then formed that lines the sidewalls of both the first set of openings and the second set of openings, and thereafter a first bit line is formed in the remainder of each of the first set of openings and a second bit line is formed in the remainder of the second set of openings, wherein the first bit line and the second bit line are in direct physical contact with the substrate and are laterally surrounded by the dielectric switching material layer.

[0017] In an embodiment of the present application, each first dielectric material layer has a lateral width greater than a lateral width of the recessed second dielectric material layer.

[0018] In an embodiment of the present application, the recess comprises an isotropic lateral etching, and a gap is formed in the second dielectric material layer laterally adjacent to the recess.

[0019] In an embodiment of the present application, forming the word line includes depositing an oxygen-deficient conductive material, laterally etching the conductive material, and cutting the conductive material formed around an end of each recessed second dielectric material layer of at least one patterned dielectric material stack.

[0020] In an embodiment of the present application, each word line has a first sidewall contacting a sidewall of a laterally adjacent recessed second dielectric material layer, and a second sidewall opposite to the first sidewall and vertically aligned with an outermost sidewall of each first dielectric material layer.

[0021] In an embodiment of the present application, forming a dielectric switching material layer includes depositing a dielectric metal oxide in each of the first and second groups of openings by atomic layer deposition, and removing the dielectric material oxide from the bottom of each of the first and second groups of openings to physically expose the substrate.

[0022] In an embodiment of the present application, the first dielectric material layer is composed of a dielectric material that is compositionally different from a dielectric material providing the second dielectric material layer.

[0023] In an embodiment of the present application, each of the word lines extends parallel to a horizontal surface of the substrate; and the first bit line and the second bit line extend perpendicular to each word line.

[0024] In an embodiment of the present application, forming the first group of openings and the second group of openings includes photolithography and etching.

[0025] In an embodiment of the present application, forming at least one patterned dielectric material stack includes forming a dielectric material stack of alternating blanket layers of a first dielectric material and a second dielectric material, and patterning the dielectric material stack by photolithography and etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a 3D view of an exemplary structure that may be employed according to embodiments of the present application, the exemplary structure comprising a dielectric material stack of alternating blanket layers of a first dielectric material and a second dielectric material overlying a substrate.

[0027] Figure 2 yes Figure 1 A 3D view of an exemplary structure after patterning the dielectric material stack to provide at least one patterned dielectric material stack comprising alternating layers of a first dielectric material and a second dielectric material.

[0028] Figure 3 yes Figure 2 A 3D view of the exemplary structure after recessing each second dielectric material layer of at least one patterned dielectric material stack to provide recessed second dielectric material layers.

[0029] Figure 4 yes Figure 3 3D view of the exemplary structure after forming a word line of the second dielectric material layer laterally adjacent to each recess.

[0030] Figure 5 yes Figure 4 3D view of an exemplary structure after forming an interlayer dielectric (ILD) material layer laterally adjacent to at least one patterned dielectric material stack.

[0031] Figure 6 yes Figure 5 3D view of an exemplary structure after forming a first set of openings in each first dielectric material layer and each recessed second dielectric material layer of at least one patterned dielectric material stack and forming a second set of openings in the ILD material layer, wherein the first set of openings and the second set of openings physically expose the substrate.

[0032] Fig. 7A yes Figure 6 3D view of the exemplary structure after forming a dielectric switching material layer lining the sidewalls of both the first set of openings and the second set of openings.

[0033] Figure 7B yes Fig. 7A A 3D view of an exemplary structure shown in FIG. 1 , showing a dielectric switching material layer formed in a first set of openings and a second set of openings; in this figure, in order to observe the dielectric switching material layer, a portion of each first dielectric material layer and each recessed second dielectric material layer located on the front side of the structure are not shown.

[0034] Fig. 8A yes Fig. 7A A 3D view of an exemplary structure after forming a first bit line in a remaining portion of each of the first set of openings and forming a second bit line in a remaining portion of each of the second set of openings, wherein each of the first and second bit lines is laterally surrounded by one of the dielectric switching material layers and has a bottommost surface in direct contact with a surface of the substrate.

[0035] Figure 8B yes Fig. 8A A 3D view of the exemplary structure shown in FIG. 1 shows a dielectric switching material layer and a bit line formed in each of a first set of openings and a second set of openings; in this figure, a portion of each first dielectric material layer and each recessed second dielectric material layer located in the front side of the structure are not shown in order to better observe the dielectric switching material layer surrounding the first and second bit lines.

[0036] Fig.9A is a top view of an NVM cell with a 3D cross-point architecture according to an embodiment of the present application; the figure includes a tangent line XX passing through a row of ReRAM devices, and a tangent line YY between two adjacent rows of ReRAM devices.

[0037] Fig. 9B is along Fig.9A A cross-sectional view of the cut line XX shown in FIG.

[0038] Fig. 9C is along Fig.9A A cross-sectional view of the cut line YY shown in FIG. DETAILED DESCRIPTION

[0039] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and therefore the drawings are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0040] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0041] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no intervening elements.

[0042] In the traditional 3D crosspoint ReRAM architecture, integration problems and cell density loss are common problems. The present application overcomes the integration problems and cell density loss of the traditional prior art by providing an NVM with a 3D crosspoint architecture, in which the vertically stacked word lines extend coplanar (i.e., parallel) with the substrate, and the bit lines extend perpendicular to the vertically stacked word lines. In other words, the length of the word line extends parallel to the substrate, and the length of the bit line extends perpendicular to the word line. The vertically stacked word lines are located in a patterned dielectric material stack, which includes alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layer vertically separates each word line within each vertical stack of word lines, and the recessed second dielectric material layer is positioned laterally adjacent to the word line. A dielectric switch material layer is located between each word line-bit line combination. Some bit lines are located in the dielectric material stack, and some bit lines are located in the interlayer dielectric material layer.

[0043] First reference Figure 1 , showing an exemplary structure that can be adopted according to an embodiment of the present application. Figure 1The exemplary structure shown includes a dielectric material stack 12 of alternating capping layers of a first dielectric material and a second dielectric material located above a substrate 10, the term "capping layer" refers to a layer that is completely formed above the substrate 10 without undergoing a patterning process. Each capping layer of the first dielectric material in the dielectric material stack 12 can be referred to as a first dielectric material capping layer 14L, and each capping layer of the second dielectric material in the dielectric material stack can be referred to as a second dielectric material capping layer 16L. In the present application, each second dielectric material capping layer 16L is sandwiched between a bottom first dielectric material capping layer and a top first dielectric material capping layer. In the present application, the dielectric material stack includes "n" second dielectric material capping layers 16L and "n+1" first dielectric material capping layers 14L, where "n" is an integer starting from 2. In the accompanying drawings, as an example, the dielectric material stack 12 includes four first dielectric material capping layers 14L and three second dielectric material capping layers 16L.

[0044] The substrate 10 may be a front end process (FEOL) level, a middle process (MOL) level, a lower interconnect level, or any combination thereof; each combination includes the FEOL as the lowest level of the substrate 10. In one example, the substrate 10 is a FEOL level and a MOL level. In another example, the substrate 10 is a FEOL level, a MOL level, and a lower interconnect level. The FEOL level is a level of a semiconductor structure including one or more semiconductor devices formed on or within a semiconductor substrate, such as one or more selector devices, such as transistors and / or diodes. The one or more selector devices typically include an array of selector devices arranged in several rows and columns. The MOL level includes one or more MOL conductive structures (vias and / or lines) embedded in a MOL dielectric material layer. The lower interconnect level includes one or more interconnect structures embedded in an interconnect dielectric material. The FEOL level, the MOL level, and / or the lower interconnect level that can be used to provide the substrate 10 include materials well known to those skilled in the art, and these layers can be formed using techniques well known to those skilled in the art. In order not to obscure the methodology of the present application, materials and processing techniques for providing the FEOL level, the MOL level and / or the lower interconnect level are not described herein.

[0045] The first dielectric material and the second dielectric material employed in the present application are electrically insulating materials, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon boron carbon nitride, or silicon oxycarbide, provided that the first dielectric material is different in composition from the second dielectric material. The compositional difference between the first dielectric material and the second dielectric material is required to provide an etch selectivity between the two different dielectric materials so that the second dielectric material can be selectively etched relative to the first dielectric material. In one example, each first dielectric material capping layer 14L of the dielectric material stack 12 is composed of silicon dioxide, and each second dielectric material capping layer 16L of the dielectric material stack 12 is composed of silicon nitride.

[0046] The dielectric material stack 12 including each first dielectric material capping layer 14L and each second dielectric material capping layer 16L can be formed by, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the first dielectric material capping layer 14L and the second dielectric material capping layer 16L can be formed using the same deposition process. In one example, the first dielectric material capping layer 14L and the second dielectric material capping layer 16L can be formed by CVD. In other embodiments, the first dielectric material capping layer 14L and the second dielectric material capping layer 16L can be formed using different deposition processes. In one example, the first dielectric material capping layer 14L can be formed by CVD, while the second dielectric material capping layer 16L can be formed by ALD.

[0047] Each first dielectric material covering layer 14L and each second dielectric material covering layer 16L may have a thickness from 10 nm to 100 nm; however, other thicknesses for each first dielectric material covering layer 14L and each second dielectric material covering layer 16L are contemplated and may be used as the thickness of the first dielectric material covering layer 14L and the second dielectric material covering layer 16L in the present application. Each first dielectric material covering layer 14L may have the same or different thickness as each other. Likewise, each second dielectric material covering layer 14L may have the same or different thickness as each other. Each first dielectric material covering layer 16L may have the same or different thickness as each second dielectric material covering layer 16.

[0048] Reference now Figure 2 , shows the dielectric material stack 12 after patterning the dielectric material stack 12 including each first dielectric material capping layer 14L and each second dielectric material capping layer 16L to provide at least one patterned dielectric material stack 12S including alternating layers of the first dielectric material and the second dielectric material Figure 1Each patterned blanket layer of the first dielectric material is referred to herein as a first dielectric material layer 14 , and each patterned blanket layer of the second dielectric material is referred to herein as a second dielectric material layer 16 .

[0049] The number of patterned dielectric material stacks 12S formed may vary and is not limited to Figure 2 In the two examples shown in the figure, in an embodiment, a single patterned dielectric material stack 12S can be formed, while in other embodiments, two or more patterned dielectric material stacks 12S can be formed. The shape of each patterned dielectric material stack 12S is generally square or rectangular. Each patterned dielectric material stack 12S can have a length from 50nm to 10000nm, and a lateral width from 90nm to 1000nm; although other lengths and widths are contemplated for each patterned dielectric material stack 12S and can be used in the present application.

[0050] The patterning of at least one patterned dielectric material stack 12S includes photolithography and etching. The photolithography includes depositing at least a photoresist material on the dielectric material stack 12, exposing the deposited photoresist material to a radiation pattern (in this application, to form a Figure 2 The patterned dielectric material stack 12S shown, the radiation pattern is a rectangular or square unit pattern), and the deposited photoresist material exposed by development. In an embodiment, one or more photolithography mask layers, such as a bottom anti-reflective coating (BARC), may be formed between the dielectric material stack 12 and the deposited photoresist material. Figure 2 In the figure, the deposited photoresist material and the optional one or more photolithographic mask layers are not shown because they are removed from the structure after the dielectric material stack 12 is patterned. The etching step for patterning the dielectric material stack 12 includes a wet etching process or a dry etching process. The etching stops at the topmost horizontal surface of the substrate 10, and in one example, the etching includes a fluorine-based plasma etch. The etching of the dielectric material stack 12 is much easier than etching through a material stack including alternating layers of dielectric material and conductive metal-containing material, which is commonly used in the prior art to form NVMs including 3D architectures.

[0051] Reference now Figure 3 , showing after recessing each second dielectric material layer 16 of at least one patterned dielectric material stack 12S to provide a recessed second dielectric material layer 16R Figure 2The lateral width of each recessed second dielectric material layer 16R is smaller than the lateral width of each second dielectric material layer 16 and each first dielectric material layer 14. In one example, the lateral width of each recessed second dielectric material layer 16R is 25 nm to 100 nm.

[0052] The recesses provide gaps 18 positioned laterally adjacent to the second dielectric material layer 16R of each recess, and each gap 18 is located between the bottom first dielectric material layer and the top first dielectric material layer, such as Figure 3 Each gap 18 represents an indentation in at least one patterned dielectric material stack 12S that will subsequently accommodate a word line.

[0053] The recessing step is performed using an isotropic lateral etching process that selectively removes the second dielectric material relative to the first dielectric material. In one example, when the first dielectric material is composed of silicon dioxide and the second dielectric material is composed of silicon nitride, the isotropic lateral etching may include hot phosphoric acid wet etching or fluorine-based plasma etching, which are commercially available and widely used in the industry.

[0054] Reference now Figure 4 , showing the state after forming the word line 20 laterally adjacent to each recessed second dielectric material layer 16R Figure 3 . Each word line 20 has a first sidewall in contact with a sidewall of a laterally adjacent recessed second dielectric material layer 16R, and a second sidewall opposite to the first sidewall, which is vertically aligned with the outermost sidewall of the first dielectric material layer 14. Each word line 20 is composed of an oxygen-deficient conductive material. Examples of these conductive materials that can be used in the present application to provide word lines 20 include, but are not limited to, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), ruthenium nitride (RuN), ruthenium-tantalum alloy (RuTa), RuTaN, cobalt (Co), nickel (Ni), copper (Cu), tungsten (W), tungsten nitride (WN), silver (Ag), platinum (Pt), palladium (Pd), or aluminum (Al).

[0055] Each word line 20 can be formed by first depositing a conductive material using a deposition process such as CVD, PECVD, PVD or ALD. The deposition process fills the entirety of each gap 18 so that the conductive material is flush with the sidewalls of the laterally adjacent recessed second dielectric material layer 16R. After depositing the conductive material, a lateral etching technique is used to remove the portion of the deposited conductive material outside each gap 18, and after the lateral etching, a metal cutting process including photolithography and etching is used to remove the conductive material of each end section of the second dielectric material layer 16R surrounding each recess (the conductive material on the left and right sides of each recessed second dielectric material layer 16R of each patterned dielectric material stack 12S is connected). The metal cutting process ensures that the conductive material remaining in each gap 18 on the left-hand side of each patterned dielectric material stack 12S is not connected to the conductive material remaining in each gap 18 on the right-hand side of each patterned dielectric material stack. The remaining and now separated conductive material in the gap 18 defines the word line 20 of the present application.

[0056] In each patterned dielectric material stack 12S, the word lines 20 are stacked vertically (in columns), and the vertically stacked word lines 20 are vertically separated by a portion of the patterned first dielectric material layer 12. The rows of word lines 20 in at least one patterned dielectric material stack 12S are laterally separated by the recessed second dielectric material layer 16R. The plurality of vertically stacked word lines may be arranged in rows and columns.

[0057] Reference now Figure 5 , showing after forming an interlayer dielectric (ILD) material layer 22 laterally adjacent to at least one patterned dielectric material stack 12S Figure 4 The ILD material layer 22 has a topmost surface that is coplanar with the topmost surface of the topmost first dielectric material layer. In some embodiments, a seam 23 may be formed in the ILD material layer 22 between two laterally adjacent patterned dielectric material stacks 12S. The seam will not be shown in the remaining figures of the present application.

[0058] The ILD material layer 22 is composed of dielectric materials with electrical insulating properties, including but not limited to silicon dioxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric materials, chemical vapor deposition (CVD) low-k dielectric materials, or any combination thereof including multiple layers. The term "low-k" used throughout this application represents a dielectric material having a dielectric constant less than 4.0. Unless otherwise specified, all dielectric constants mentioned herein are measured in a vacuum. Exemplary low-k dielectric materials that can be used include but are not limited to silsesquioxanes, C-doped oxides (i.e., organosilicates) including Si, C, O, and H atoms, thermosetting polyarylene ethers or multiple layers thereof. The term "polyarylene" is used in this application to represent an aryl moiety or an inert substituted aryl moiety connected together by a key, a condensed ring, or an inert linking group such as oxygen, sulfur, sulfone, sulfoxide, carbonyl, etc.

[0059] The ILD material layer 22 may be formed using a deposition process including, for example, CVD, PECVD, ALD, evaporation, or spin coating. After the dielectric material providing the ILD material layer 22 is deposited, a planarization process such as chemical mechanical polishing (CMP) may be performed.

[0060] Reference now Figure 6 , showing the first set of openings 24 formed in the first dielectric material layer 14 and the recessed second dielectric material layer 16R of at least one patterned dielectric material stack 12S and the second set of openings 25 formed in the ILD material layer 22 Figure 5 , wherein the first group of openings 24 and the second group of openings 25 extend downward and physically expose the substrate 10, and it is noted that the first group of openings 24 do not pass through any word line 20 when passing through the first dielectric material layer 14 and the recessed second dielectric material layer 16R. However, the first group of openings 24 exposes the sidewalls of each vertically stacked word line 20 in each patterned dielectric material stack 12S.

[0061] The first group of openings 24 and the second group of openings 25 can be formed by photolithography and etching. With respect to the photolithography step, a hole pattern is formed in the photoresist material, and those hole patterns are transferred to the underlying structure as defined above. With respect to the etching step, one or more etching processes including dry etching and / or chemical wet etching can be used. One or more etching processes for forming the first group of openings 24 and the second group of openings 25 stop on the surface of the substrate 10, and each of the first group of openings 24 and the second group of openings 25 will subsequently accommodate the dielectric switch material layer and the bit line. In some embodiments, the first group of openings 24 and the second group of openings 25 can be formed simultaneously. In other embodiments, the first group of openings 24 and the second group of openings 25 are formed at different times, for example, the first group of openings 24 can be formed first, and then the second group of openings 25 can be formed, or vice versa. When the first group of openings 24 and the second group of openings 25 are formed at different events, the etching for forming the openings 24 can be the same or different from the etching for forming the openings 25. The number of openings 24 may vary (in the present application, at least one, more typically two or more openings 24 are formed), and similarly, the number of openings 25 may vary (in the present application, at least one, more typically two or more openings 25 are formed). The number of openings providing the first group of openings 24 may be the same as or different from the number of openings providing the second group of openings 25, and the first group of openings 24 and the second group of openings 25 may be different as shown in FIG. Figure 6 As shown, they are formed in rows and columns.

[0062] Reference now Fig. 7A , which shows the dielectric switching material layer 26 after forming the dielectric switching material layer 26 lining the sidewalls of each of the first set of openings 24 and the second set of openings 25 Figure 6 An exemplary structure of . Figure 7B Show Fig. 7A , which shows a dielectric switch material layer 26 formed in each of the first group of openings 24 and the second group of openings 25; in this figure, each first dielectric material layer 14 and each recessed second dielectric material layer 16R located on the front side of the structure are not shown in order to better observe the dielectric switch material layer 26. In the present application, each dielectric switch material layer 26 contacts the sidewall of the vertically stacked word line 20.

[0063] Each dielectric switching material layer 26 may be composed of a dielectric metal oxide material having a dielectric constant of 4.0 or greater. At this point in the present application, each dielectric switching material layer 26 is electrically insulating, and during operational use, the dielectric switching material layer 20 may be converted into a conductive filament. After use, the conductive filament returns to its insulating state. Examples of dielectric metal oxides that may be used as dielectric switching material layers 26 include, but are not limited to, hafnium oxide (HfO x ), tantalum oxide (TaO x), titanium oxide (TiO x ), aluminum oxide (AlO x ), silicon dioxide (SiO2), or a combination thereof, wherein x is from 1.5 to 3.5. The dielectric metal oxide providing each dielectric switching material layer 26 is formed by ALD, and after the ALD process, etching can be used to remove the dielectric metal oxide in each of the first set of openings 24 and the second set of openings 25 formed on the surface of the substrate 10. Each dielectric switching material layer 26 within the first set of openings 24 is thus lined within the first set of openings 24, and each dielectric switching material layer 26 within the second set of openings 25 is thus lined within the second set of openings 25. The dielectric switching material layer 26 may have a thickness from 1 nm to 30 nm; however, other thicknesses may also be considered as the thickness of the dielectric switching material layer 26, as long as the dielectric switching material layer 26 does not fill the entire volume of the openings providing the first set of openings 24 and the openings providing the second set of openings 25.

[0064] Reference now Fig. 8A 3D, which shows that after forming the first bit line 28 in the remaining portion of each of the first set of openings 24 and forming the second bit line 29 in the second set of openings 25 Fig. 7A An exemplary structure in which each first bit line 28 and each second bit line 29 are laterally surrounded by one of the dielectric switching material layers 28 and have a bottommost surface in direct contact with a surface of the substrate 10. Figure 8B exhibit Fig. 8A , which shows a dielectric switching material layer 26 and a first bit line 28 formed in each of the first group of openings 24 and a second bit line 29 formed in the second group of openings 25; in this figure, in order to better observe the dielectric switching material layer 26 surrounding the first bit line 28 and the second bit line 29, each first dielectric material layer 14 and each recessed second dielectric material layer 16R located in the front side of the structure are not shown.

[0065] Each first bit line 28 and each second bit line 29 is composed of one of the conductive materials mentioned above for the word line 20. The conductive material providing each first bit line 28 and each second bit line 29 may be the same or different in composition from the conductive material providing the word line 20. The conductive material may be formed using one of the deposition processes mentioned above when forming the word line 20. After depositing the conductive material providing each first bit line 28 and each second bit line 29, a planarization process such as CMP may be used to provide the conductive material. Fig. 8A and 8B , wherein the topmost surface of each first bit line 28 and each second bit line 29 is coplanar with the topmost surface of the ILD material layer 22 and the topmost surface of the first dielectric material layer 14 .

[0066] As shown, each word line 20 extends in a first direction parallel to the horizontal topmost surface of the substrate 10, while each first bit line 28 and each second bit line 29 extend in a second direction different from the first direction and perpendicular to the vertically stacked word lines 20; thereby providing a cross-point memory. As further shown, each first bit line 28 and each second bit line 29 has a bottommost surface in direct physical contact with the substrate 10.

[0067] Reference now Fig.9A , showing a top view of a NVM cell with a 3D crosspoint architecture according to an embodiment of the present application; the figure includes a cut line XX passing through a row of ReRAM devices (see Fig. 9B ) and the tangent line YY between two adjacent rows of ReRAM devices (see Fig. 9C ).exist Fig.9A In the top view shown, a portion of the topmost patterned first material layer 14 is not shown so as to expose the recessed second dielectric material underneath.

[0068] It is worth noting that Figures 8A-8B The NVM cell with a 3D cross-point architecture shown in FIGS. 9A, 9B, and 9C includes a plurality of vertically stacked word lines extending parallel to the topmost horizontal surface of the substrate 10, wherein each word line 20 of the plurality of vertically stacked word lines is vertically separated by the first dielectric material layer 14, and each word line 20 of the plurality of word lines 20 has a first sidewall contacting the second dielectric material layer (i.e., the recessed second dielectric material layer 16R) and a second sidewall opposite to the first sidewall contacting the interlayer dielectric material layer 22, wherein the second dielectric material layer (i.e., the recessed second dielectric material layer 16R) has a lateral width less than the lateral width of the first dielectric material layer 14. At least one first bit line 28 is located in the dielectric material stack including a portion of each first dielectric material layer 14 and each second dielectric material layer (i.e., the recessed second dielectric material layer 16R), and at least one second bit line 29 is located in the interlayer dielectric material layer 22. According to the present application, at least one first bit line 28 and at least one second bit line 29 extend perpendicularly to the plurality of vertically stacked word lines and are in direct contact with the topmost horizontal surface of the substrate 10. A dielectric switching material layer 26 is located on the sidewalls of both the at least one first bit line 28 and the at least one second bit line 29, wherein the dielectric switching material layer 26 surrounding the at least one first bit line 28 separates the at least one first bit line 28 from each word line 20 of the plurality of vertically stacked word lines, and the dielectric switching material layer 26 surrounding the at least one second bit line 29 separates the at least one second bit line 29 from each word line 20 of the plurality of vertically stacked word lines. Figures 8A-8B and Fig.9A , 9BThe NVM cell shown in 9C has double the density compared to a conventional NVM cell with a 3D cross-point architecture.

[0069] Although the present application has been specifically shown and described with reference to the preferred embodiments of the present application, it should be understood by those skilled in the art that the foregoing and other changes may be made in form and detail without departing from the spirit and scope of the present application. Therefore, the present application should not be limited to the exact form and details described and shown, but fall within the scope of the appended claims.

Claims

1. A non-volatile memory (NVM), comprising: a plurality of vertically stacked word lines extending parallel to a topmost horizontal surface of the substrate, wherein each word line of the plurality of vertically stacked word lines is vertically separated by a first dielectric material layer, and each word line of the plurality of vertically stacked word lines has a first sidewall contacting a second dielectric material layer and a second sidewall opposite the first sidewall contacting an interlayer dielectric material layer, wherein the second dielectric material layer has a lateral width that is less than a lateral width of the first dielectric material layer; at least one first bit line located in a dielectric material stack including a portion of each first dielectric material layer and each second dielectric material layer; at least one second bit line located in the interlayer dielectric material layer, wherein the at least one first bit line and the at least one second bit line extend perpendicular to the plurality of vertically stacked word lines and are in direct contact with the topmost horizontal surface of the substrate; as well as a dielectric switching material layer located on sidewalls of both the at least one first bit line and the at least one second bit line, wherein the dielectric switching material layer surrounding the at least one first bit line separates the at least one first bit line from each of the plurality of vertically stacked word lines, and the dielectric switching material layer surrounding the at least one second bit line separates the at least one second bit line from each of the plurality of vertically stacked word lines.

2. The NVM according to claim 1, wherein: The second sidewall of each word line is vertically aligned with the outermost sidewall of each first dielectric material layer.

3. The NVM according to claim 1, wherein: The first dielectric material layer is composed of a dielectric material that is compositionally different from the dielectric material providing the second dielectric material layer.

4. The NVM according to claim 1, wherein: A bottommost word line of the plurality of vertically stacked word lines is spaced apart from the substrate by a bottommost first dielectric material layer.

5. The NVM according to claim 1, wherein: Each word line, the at least one first bit line, and the at least one second bit line are composed of an oxygen-deficient conductive material.

6. The NVM according to claim 1, wherein: The dielectric switching material layer is composed of dielectric metal oxide.

7. The NVM according to claim 1, wherein: The substrate includes one or more selector devices.

8. The NVM according to claim 1, wherein: The at least one first bit line includes a plurality of first bit lines, and the at least one second bit line includes a plurality of second bit lines.

9. The NVM according to claim 1, wherein: The at least one first bit line and the at least one second bit line are arranged in a same row.

10. The NVM according to claim 1, wherein: The at least one first bit line has a topmost surface that is coplanar with a topmost surface of each of the at least one second bit line and the interlayer dielectric material layer.

11. A method for forming a non-volatile memory, the method comprising: providing at least one patterned dielectric material stack comprising alternating first and second dielectric material layers on top of a substrate; recessing each second dielectric material layer of the at least one patterned dielectric material stack to provide a recessed second dielectric material layer; forming a word line of the second dielectric material layer laterally adjacent to each recess; forming an interlayer dielectric (ILD) material layer laterally adjacent to the at least one patterned dielectric material stack; forming a first set of openings in each first dielectric material layer and each recessed second dielectric material layer of the at least one patterned dielectric material stack, and forming a second set of openings in the ILD material layer, wherein the first set of openings and the second set of openings physically expose the substrate; forming a layer of dielectric switching material lining the sidewalls of each of the first set of openings and the second set of openings; as well as A first bit line is formed in a remaining portion of each of the first set of openings and a second bit line is formed in a remaining portion of the second set of openings, wherein the first and second bit lines are in direct physical contact with the substrate and are laterally surrounded by the dielectric switching material layer.

12. The method according to claim 11, wherein: Each of the first dielectric material layers has a lateral width greater than a lateral width of each of the recessed second dielectric material layers.

13. The method according to claim 11, wherein: The recesses include isotropic lateral etching and form gaps of the second dielectric material layer laterally adjacent to each recess.

14. The method according to claim 13, wherein: The forming of the word line comprises: Deposition of oxygen-deficient conductive materials; laterally etching the conductive material; and The conductive material formed around an end portion of each of the recessed second dielectric material layers is cut.

15. The method according to claim 11, wherein: Each word line has a first sidewall in contact with a sidewall of the recessed second dielectric material layer and a second sidewall opposite to the first sidewall and vertically aligned with an outermost sidewall of the first dielectric material layer.

16. The method according to claim 11, wherein: The forming of the dielectric switch material layer comprises: depositing a dielectric metal oxide in each of the first set of openings and the second set of openings by atomic layer deposition; and The dielectric metal oxide is removed from a bottom of each of the first and second groups of openings to physically expose the substrate.

17. The method according to claim 11, wherein: Each of the first dielectric material layers is composed of a dielectric material that is compositionally different from the dielectric material providing each of the second dielectric material layers.

18. The method according to claim 11, wherein: Each of the word lines extends parallel to a horizontal surface of the substrate; and the first bit line and the second bit line extend perpendicular to the word lines.

19. The method according to claim 11, wherein: The forming of the first group of openings and the second group of openings includes photolithography and etching.

20. The method according to claim 11, wherein: The forming of the at least one patterned dielectric material stack comprises: forming a dielectric material stack of alternating layers of a first dielectric material and a second dielectric material; and The dielectric material stack is patterned by photolithography and etching.

Images