Semiconductor device and method for manufacturing semiconductor device

Abstract

And the leakage current is suppressed. The semiconductor device includes: a first positive electrode provided on a portion of an upper surface of a gallium oxide layer of a first conductivity type; a semiconductor layer of a second conductivity type provided so as to cover a portion of the gallium oxide layer and at least a portion of the first positive electrode; and a second positive electrode provided so as to cover the semiconductor layer, a plurality of trenches being provided in a surface layer portion of the gallium oxide layer, the first positive electrode being provided in the surface layer portion of the gallium oxide layer that does not overlap the trenches in plan view, and the semiconductor layer being provided so as to cover the gallium oxide layer inside the trenches.

Description

Technical Field

[0001] The technology disclosed in this application specification relates to semiconductor technology. Background Art

[0002] Power electronics is a technology that quickly and efficiently converts electrical current, such as direct current, alternating current, or frequency. Power electronics (technology) is a technology that combines the recent semiconductor-based electronics and control engineering in addition to conventional electrical engineering. Such power electronics is currently used in all occasions where electricity is used, such as power, industry, transportation, and household use.

[0003] In recent years, the proportion of electric energy in total energy consumption, i.e., the electrification rate, has been rising not only in Japan but also around the world. The background for this is the development of machines that are convenient and energy-efficient in terms of electricity use, and the increase in the utilization rate of electricity. The technology that forms the basis of these is power electronics technology.

[0004] Power electronics technology can also be called: technology that converts input into an electrical state suitable for the machine being used, regardless of the state of the electrical state of the object of conversion (e.g., frequency, current, or voltage). The basic elements of power electronics technology are rectifiers and inverters. Moreover, semiconductors, and semiconductor elements such as diodes or transistors that use semiconductors, are the basis of these.

[0005] In the current field of power electronics, diodes as semiconductor rectifying elements are used in various applications including electric machines, and are used in a wide frequency band.

[0006] In recent years, switching elements that can operate at low loss and high frequency have been developed and put into practical use for high withstand voltage and large capacity applications. In addition, the materials used for semiconductor elements have also been transformed into wide bandgap materials to achieve high withstand voltage of the elements. As representative elements for achieving high withstand voltage, there are Schottky barrier diodes (Schottky barrier diodes, i.e. SBDs) or pn diodes (PNDs), etc., which are widely used for various applications.

[0007] As an element using gallium oxide for a semiconductor layer, a trench MOS type SBD has been developed, for example, as exemplified in Patent Document 1. Generally speaking, when a reverse voltage is applied to an SBD using a semiconductor material having a large dielectric breakdown strength, the leakage current between the anode electrode and the semiconductor material layer increases. In contrast, the trench MOS type SBD exemplified in Patent Document 1 can disperse and relax the electric field applied to the anode electrode end, thereby improving the reverse withstand voltage of the element.

[0008] Next, in a trench-type junction barrier controlled Schottky diode (JBS) as exemplified in Patent Document 2, when a reverse voltage is applied, a depletion layer extends from the p-type semiconductor layer to the n-type semiconductor layer of the convex portion, closing the channel and thereby suppressing leakage current.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Publication No. 2020-170787

[0012] Patent Document 2: Japanese Patent Application Publication No. 2019-036593 Summary of the invention

[0013] It is considered that the MOS type SBD described in Patent Document 1 is inferior in leakage current suppression effect compared to the JBS structure using a p-type semiconductor described in Patent Document 2. On the other hand, in the structure described in Patent Document 2, it is difficult to form a pn junction.

[0014] The technology disclosed in the present specification has been accomplished in view of the above-described problems, and provides a technology for suppressing leakage current.

[0015] The first scheme of the technology disclosed in the present application specification provides a semiconductor device, comprising: a first conductive type gallium oxide layer; a first anode electrode, arranged on a portion of the upper surface of the gallium oxide layer; a second conductive type semiconductor layer, arranged to cover a portion of the gallium oxide layer and at least a portion of the first anode electrode; and a second anode electrode, arranged to cover the semiconductor layer, a plurality of grooves being arranged in the surface portion of the gallium oxide layer, the first anode electrode being arranged on the surface portion of the gallium oxide layer that does not overlap with the grooves when viewed from above, and the semiconductor layer being arranged to cover the gallium oxide layer inside the grooves.

[0016] According to at least the first aspect of the technology disclosed in this specification, leakage current can be suppressed.

[0017] In addition, the objects, features, aspects, and advantages related to the technology disclosed in the present application specification will become more apparent from the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0019] Figure 2It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0020] Figure 3 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0021] Figure 4 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0022] Figure 5 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0023] Figure 6 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0024] Figure 7 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0025] Figure 8 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0026] Fig. 9 This is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

[0027] Fig.10 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0028] Fig.11 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0029] Fig.12 It is a cross-sectional view schematically showing the structure of a semiconductor device according to an embodiment.

[0030] Fig.13 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment.

[0031] Fig.14 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0032] The following embodiments will be described with reference to the attached drawings. In the following embodiments, detailed features and the like are shown for technical description, but these are merely examples and are not all essential features in order to implement the embodiments.

[0033] In addition, the drawings are schematically shown, and for the convenience of explanation, the structure is appropriately omitted or simplified in the drawings. In addition, the size and position of the structures shown in different drawings are not necessarily correctly recorded and can be appropriately changed. In addition, in drawings such as top views that are not cross-sectional views, hatching is sometimes added to facilitate understanding of the contents of the embodiments.

[0034] In the following description, the same components are shown with the same reference numerals, and their names and functions are the same. Therefore, in order to avoid duplication, their detailed description may be omitted.

[0035] In addition, in the description described in the specification of the present application, when a certain component is described as “having”, “including” or “having”, it does not mean that other components are excluded from existence unless otherwise specified.

[0036] In addition, in the description recorded in the specification of this application, even if ordinal numbers such as "1st" or "2nd" are used, these terms are used for convenience in order to make the contents of the implementation method easy to understand, and the contents of the implementation method are not limited to the order that can be obtained by these ordinal numbers.

[0037] In addition, in the description recorded in the specification of this application, even if terms such as "up", "down", "left", "right", "side", "bottom", "front" or "back" are used to imply specific positions or directions, these terms are used for convenience in order to make the contents of the implementation method easy to understand and have nothing to do with the position or direction when the implementation method is actually implemented.

[0038] In addition, in the descriptions recorded in the specification of the present application, when it is described as "the upper surface of..." or "the lower surface of...", etc., in addition to the upper surface itself or the lower surface itself of the target component, it also includes a state where other components are formed on the upper surface or the lower surface of the target component. That is, for example, when it is described as "B provided on the upper surface of A", it does not prevent another component "C" from being interposed between A and B.

[0039] <First Embodiment>

[0040] The following describes an oxide semiconductor device as a semiconductor device of this embodiment and a method for manufacturing the oxide semiconductor device. First, the structure of the oxide semiconductor device of this embodiment is described. In the following description, the oxide semiconductor device may be simply described as a "semiconductor device".

[0041] <Regarding the Structure of Semiconductor Device>

[0042] Hereinafter, the semiconductor device of this embodiment is described by setting the electrode provided on the upper surface side of the substrate as an anode electrode and the electrode provided on the lower surface side of the substrate as a cathode electrode. However, the semiconductor device of this embodiment is not limited to SBD, and may also be other power device elements such as switching elements.

[0043] Figure 1 1 is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to this embodiment. Figure 1 For example, the semiconductor device includes an n-type gallium oxide layer. In the following description, the n-type gallium oxide layer is assumed to include an n-type single crystal gallium oxide substrate 7 and an n-type gallium oxide epitaxial layer 6, but the n-type gallium oxide layer is not limited to such a structural example.

[0044] The n-type single crystal gallium oxide substrate 7 is an n-type oxide semiconductor having an upper surface (first main surface) and a lower surface (second main surface) opposite to the upper surface. The n-type gallium oxide epitaxial layer 6 is an epitaxial layer provided on the upper surface of the n-type single crystal gallium oxide substrate 7 .

[0045] Figure 1 The illustrated semiconductor device has a trench structure 100 in the surface of the n-type gallium oxide epitaxial layer 6 in an active region surrounded by the termination structure in plan view. The semiconductor device also includes an anode electrode 2 as an electrode electrically Schottky-bonded to the n-type gallium oxide epitaxial layer 6.

[0046] The semiconductor device also includes a p-type semiconductor layer 5 provided to cover the inside and outside of the trench structure 100 . The p-type semiconductor layer 5 is a material mainly composed of an element different from gallium oxide, and forms a heterogeneous pn junction with the n-type gallium oxide epitaxial layer 6 .

[0047] and then, Figure 1 The illustrated semiconductor device includes a field plate insulating material layer 3 provided between an n-type gallium oxide epitaxial layer 6 and an anode electrode 1 in a terminal structure provided outside an active region through which current flows in an element such as an SBD. The portion where the field plate insulating material layer 3 and the anode electrode 1 are stacked constitutes a field plate structure, thereby improving the withstand voltage of the semiconductor device when a reverse bias is applied to the semiconductor device.

[0048] Furthermore, on the lower surface of the n-type single-crystalline gallium oxide substrate 7 , a cathode electrode 8 is provided as an electrode electrically ohmically bonded to the lower surface of the n-type single-crystalline gallium oxide substrate 7 .

[0049] Next, the above-mentioned components will be described in further detail.

[0050] The n-type single crystal gallium oxide substrate 7 is made of Ga 2 O 3An n-type oxide semiconductor composed of a single crystal, preferably β-Ga 2 O 3 The n-type single crystal gallium oxide substrate 7 is made of β-Ga 2 O 3 When the single crystal is formed, the crystal structure is stable, and an n-type single crystal gallium oxide substrate 7 having stable physical properties can be obtained.

[0051] The n-type single crystal gallium oxide substrate 7 exhibits n-type conductivity due to oxygen vacancies (deficiencies) in the crystal, and therefore may not contain n-type impurities, but may contain n-type impurities such as silicon (Si) or tin (Sn). That is, the n-type single crystal gallium oxide substrate 7 may be any of a substrate that exhibits n-type conductivity only due to oxygen vacancies, a substrate that exhibits n-type conductivity only due to n-type impurities, and a substrate that exhibits n-type conductivity due to both oxygen vacancies and n-type impurities.

[0052] The n-type carrier concentration (electron carrier concentration) of the n-type single-crystalline gallium oxide substrate 7 containing n-type impurities is the total concentration of oxygen vacancies and n-type impurities. The n-type carrier concentration (electron carrier concentration) of the n-type single-crystalline gallium oxide substrate 7 can be, for example, 1×10 17 cm -3 Above and 1×10 19 cm -3 In order to reduce the contact resistance between the n-type single crystal gallium oxide substrate 7 and the cathode 8, the impurity concentration may be higher than the above numerical range.

[0053] The n-type gallium oxide epitaxial layer 6 is provided on the upper surface of the n-type single crystal gallium oxide substrate 7. The n-type gallium oxide epitaxial layer 6 is made of Ga 2 O 3 An n-type oxide semiconductor composed of a single crystal, preferably β-Ga 2 O 3 The n-type gallium oxide epitaxial layer 6 is made of β-Ga 2 O 3 When the single crystal is formed, the crystal structure is stable, and an n-type gallium oxide epitaxial layer 6 having stable physical properties can be obtained.

[0054] The n-type carrier concentration (electron carrier concentration) of the n-type gallium oxide epitaxial layer 6 is preferably lower than the electron carrier concentration of the n-type single crystal gallium oxide substrate 7, and may be, for example, 1×10 15 cm -3 Above and 1×10 17 cm -3 the following.

[0055] A trench structure 100 is formed on the surface of the n-type gallium oxide epitaxial layer 6. The method for forming the trench structure 100 is not particularly limited. For example, the trench structure 100 may be formed by using BCl 3 Dry etching of gas is formed.

[0056] When forming the trench structure 100, the anode electrode 2 that is Schottky-bonded to the n-type gallium oxide epitaxial layer 6 can be used as an etching mask. For this reason, it is preferable that the surface of the anode electrode 2 does not deteriorate due to etching. As a Schottky electrode, for example, platinum (Pt), nickel (Ni), gold (Au), or palladium (Pd) can be used, but in the case of a material that significantly deteriorates due to etching, the anode electrode 2 can be a stacked structure.

[0057] For example, it is preferable to provide a first layer composed of a metal material suitable for Schottky bonding with the n-type gallium oxide epitaxial layer 6 in contact with the n-type gallium oxide epitaxial layer 6, and to provide a second layer composed of other metal materials with excellent etching resistance on the upper surface of the first layer, thereby forming a stacked structure anode 2.

[0058] The cathode electrode 8 is provided on the lower surface of the n-type single crystal gallium oxide substrate 7. Since the cathode electrode 8 is ohmically bonded to the n-type single crystal gallium oxide substrate 7, it is preferably formed of a metal material having a work function smaller than that of the n-type single crystal gallium oxide substrate 7. In addition, it is preferable to form the cathode electrode 8 with a metal material such that the contact resistance between the n-type single crystal gallium oxide substrate 7 and the cathode electrode 8 is reduced by heat treatment after the cathode electrode 8 is formed on the lower surface of the n-type single crystal gallium oxide substrate 7. As such a metal material, titanium (Ti) can be used, for example.

[0059] In addition, the cathode electrode 8 may also be formed by stacking a plurality of metal materials. For example, in the case where a metal material that is easily oxidized contacts the lower surface of the n-type single crystal gallium oxide substrate 7, a metal material that is not easily oxidized may also be formed on the lower surface of the metal material to form a laminated cathode electrode 8. For example, a first layer made of Ti in contact with the n-type single crystal gallium oxide substrate 7 may be provided, and a second layer made of gold (Au) or silver (Ag) may be provided on the lower surface of the first layer to form a laminated cathode electrode 8.

[0060] In addition, the cathode electrode 8 may be provided on the entire lower surface of the n-type single-crystalline gallium oxide substrate 7 , or may be provided on a portion of the lower surface of the n-type single-crystalline gallium oxide substrate 7 .

[0061] The anode electrode 1 is disposed above the n-type gallium oxide epitaxial layer 6. It is preferable to provide a p-type semiconductor layer 5 between the anode electrode 1 and the n-type gallium oxide epitaxial layer 6, and the anode electrode 1 and the p-type semiconductor layer 5 are ohmically bonded. For this purpose, the anode electrode 1 is preferably composed of a metal material having a work function smaller than that of the p-type semiconductor layer 5. As such a metal material, for example, Au can be used.

[0062] The anode electrode 1 may be a stacked structure like the anode electrode 2 or the cathode electrode 8. For example, a first layer made of a metal material suitable for ohmic bonding with the p-type semiconductor layer 5 may be provided in contact with the p-type semiconductor layer 5, and a second layer made of another metal material may be provided on the upper surface of the first layer, thereby forming an anode electrode 1 of a stacked structure.

[0063] The p-type semiconductor layer 5 is also provided inside the trench structure 100 formed on the surface of the n-type gallium oxide epitaxial layer 6. The p-type semiconductor layer 5 is formed to cover the outside (specifically, the top) of the trench structure 100 via the anode electrode 2.

[0064] The material of the p-type semiconductor layer 5 is not particularly limited, and is preferably a p-type oxide semiconductor material, preferably copper oxide (Cu 2 O), silver oxide (Ag 2 O), nickel oxide (NiO), or tin oxide (SnO), which exhibits p-type conductivity even without adding p-type impurities. 2 In O, the 3d orbital of Cu forms the upper end of the valence band that conducts holes, and holes appear due to Cu vacancies, so p-type conductivity is exhibited. 2 When O is oxidized to CuO, the 3d orbital of Cu does not form the upper end of the valence band, and the p-type conductivity disappears. The p-type semiconductor layer 5 is preferably composed of a p-type oxide semiconductor composed of a metal oxide having such properties, such as Cu 2 A p-type oxide semiconductor generally exhibits p-type conductivity even without adding a p-type impurity.

[0065] When the p-type semiconductor layer 5 is limited to a p-type oxide semiconductor, it is composed of a p-type oxide semiconductor that exhibits p-type conductivity even without adding a p-type impurity, but even in such a case, a p-type impurity may be added. 2 In the case of O, nitrogen (N) can be used as a p-type impurity.

[0066] The p-type carrier concentration (electron carrier concentration) of the p-type semiconductor layer 5 is the concentration of metal atom vacancies of the p-type oxide semiconductor when no p-type impurities are added, and is the total concentration of metal atom vacancies and p-type impurities of the p-type oxide semiconductor when p-type impurities are added. When p-type impurities are added to the p-type semiconductor layer 5, sometimes even if the metal oxide of the p-type oxide semiconductor is oxidized and the p-type conductivity disappears, the p-type oxide semiconductor as a whole exhibits p-type conductivity due to the p-type impurities. However, when the metal oxide of the p-type oxide semiconductor is oxidized and the corresponding p-type conductivity disappears, the p-type conductivity of the p-type oxide semiconductor as a whole decreases, so it is preferable not to oxidize the metal oxide of the p-type oxide semiconductor.

[0067] The field plate insulating material layer 3 is made of, for example, silicon dioxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ) and other materials. These materials have a dielectric breakdown field strength higher than that of Ga that constitutes the n-type gallium oxide epitaxial layer 6. 2 O 3 The thickness of the field plate insulating material layer 3 varies depending on the structure of the device, but may be 1 μm or less, and may be, for example, 200 nm or more and 900 nm or less.

[0068] and then, Figure 1 The illustrated field plate insulating material layer 3 is not a simple one-level structure, but a multi-level field plate structure formed in a stepped shape. Specifically, the field plate insulating material layer 3 is arranged across the upper surfaces of the p-type semiconductor layer 5 and the n-type gallium oxide epitaxial layer 6, but since it is formed across the portion of the top of the trench structure 100 arranged in the p-type semiconductor layer 5 (i.e., the portion arranged on the upper surface of the n-type gallium oxide epitaxial layer 6 across the anode electrode 2), and the portion of the upper surface of the n-type gallium oxide epitaxial layer 6 arranged outside the trench structure 100 of the p-type semiconductor layer 5, and the inside of the trench structure 100, it becomes a multi-level structure. For this reason, the field plate insulating material layer 3 is preferably formed in a slope or step shape. When the field plate insulating material layer 3 is formed in a slope or step shape, the electric field strength at the electric field concentration point of the device can be suppressed, so a high withstand voltage of the device can be expected.

[0069] <About Method of Manufacturing Semiconductor Device>

[0070] Next, refer to Figures 1 to 8 A method for manufacturing an oxide semiconductor device as a semiconductor device of this embodiment will be described. Figures 2 to 8 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the present embodiment.

[0071] First, if Figure 2 As an example, an n-type single crystal gallium oxide substrate 7 is prepared. As the n-type single crystal gallium oxide substrate 7, a β-Ga prepared by a solution growth method can be used. 2 O 3 A substrate cut out of a single crystal bump in a substrate shape.

[0072] Next, if Figure 3 For example, an n-type gallium oxide epitaxial layer 6 is deposited by epitaxial growth on the upper surface of an n-type single crystal gallium oxide substrate 7. The method for forming the n-type gallium oxide epitaxial layer 6 is not particularly limited, and for example, the n-type gallium oxide epitaxial layer 6 can be formed on the upper surface of the n-type single crystal gallium oxide substrate 7 by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or a halide vapor phase epitaxy (HVPE) method.

[0073] Next, if Figure 4 For example, a metal material that becomes a cathode electrode 8 is deposited on the lower surface of an n-type single-crystalline gallium oxide substrate 7 by evaporation or sputtering. For example, a Ti layer is deposited on the lower surface of the n-type single-crystalline gallium oxide substrate 7 with a thickness of 50 nm by electron beam evaporation (EB evaporation), and then an Au layer is deposited on the Ti layer with a thickness of 300 nm by electron beam evaporation, thereby forming a two-layer cathode electrode 8. Thereafter, for example, a heat treatment is performed at 550° C. for 5 minutes in a nitrogen atmosphere or an oxygen atmosphere. As a result, a cathode electrode 8 is formed on the lower surface of the n-type single-crystalline gallium oxide substrate 7 that is ohmically bonded to the n-type single-crystalline gallium oxide substrate 7. In addition, in order to reduce the contact resistance between the n-type single-crystalline gallium oxide substrate 7 and the cathode electrode 8, the lower surface of the n-type single-crystalline gallium oxide substrate 7 may be treated with BCl before the cathode electrode 8 is formed. 3 RIE treatment of gases.

[0074] Next, if Figure 5 For example, in the active region surrounded by the terminal structure in a plan view, the anode electrode 2 is formed on a portion of the upper surface of the n-type gallium oxide epitaxial layer 6. The anode electrode 2 is formed at a position that does not overlap with the trench structure 100 formed in a subsequent process in a plan view. The method for forming the anode electrode 2 is not particularly limited, and for example, a resist pattern mask can be formed by photolithography to form a metal that is Schottky-bonded to the n-type gallium oxide epitaxial layer 6, and then the anode electrode 2 is formed by a lift-off process.

[0075] Next, if Figure 6For example, the anode electrode 2 is used as an etching mask to form the trench structure 100. For example, by using boron trichloride (BCl 3 ) or other dry etching gas to form a trench structure 100 in the surface layer of the n-type gallium oxide epitaxial layer 6. The method for forming the trench structure 100 is not particularly limited, and an existing formation method such as a dry etching method or a wet etching method can be used. In addition, it is best to remove the damaged layer formed in the n-type gallium oxide epitaxial layer 6 due to etching in post-processing.

[0076] Next, if Figure 7 For example, the p-type semiconductor layer 5 is formed to cover the inside of the trench structure 100 and the outside of the trench structure 100 (specifically, the top of the trench structure 100 where the anode electrode 2 is formed and a portion of the upper surface of the n-type gallium oxide epitaxial layer 6 that is exposed without the anode electrode 2). The method for forming the p-type semiconductor layer 5 is not particularly limited, and for example, there is a method of forming the p-type semiconductor layer 5 with desired physical properties using a sputtering method or a pulsed laser deposition method (PLD) method. In addition, when forming a pattern, it can be formed by various techniques such as formation based on lift-off or formation based on etching.

[0077] Next, if Figure 8 For example, in the terminal structure, a field plate insulating material layer 3 is formed on the upper surface of the exposed n-type gallium oxide epitaxial layer 6 and the upper surface of the p-type semiconductor layer 5. The method for forming the field plate insulating material layer 3 is not particularly limited, and for example, it can be formed using a plasma CVD method, a sputtering method, or a spin-on glass (SOG) method.

[0078] Finally, an anode electrode 1 is formed on the upper surface of the p-type semiconductor layer 5 and the upper surface of the field plate insulating material layer 3, thereby completing the Figure 1 The semiconductor device according to this embodiment is illustrated.

[0079] <Second Embodiment>

[0080] In the following description, components identical to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted.

[0081] <About the Structure of Semiconductor Device>

[0082] Fig. 92 is a cross-sectional view schematically showing an example of the structure of the semiconductor device of this embodiment. Note that the method for manufacturing the semiconductor device of this embodiment is the same as the method for manufacturing the semiconductor device of the first embodiment.

[0083] exist Figure 1 In the semiconductor device shown in FIG. 1 , a p-type semiconductor layer 5 is formed so as to bury the interior of the trench structure 100. Fig. 9 In the semiconductor device of the present embodiment shown, a p-type semiconductor layer 5A is formed on the sidewalls and the bottom of the trench structure 100. The p-type semiconductor layer 5A does not bury the interior of the trench structure 100 but is provided on the bottom surface and the side surface of the interior of the trench structure 100. Furthermore, an anode electrode 1 is provided inside the trench structure 100 so as to be surrounded by the p-type semiconductor layer 5A.

[0084] The p-type semiconductor layer sometimes acts as a resistance component of the device, so by having Fig. 9 The p-type semiconductor layer 5A shown can realize a low-resistance semiconductor device.

[0085] <About Method of Manufacturing Semiconductor Device>

[0086] Next, refer to Figures 9 to 11 A method for manufacturing an oxide semiconductor device as a semiconductor device of this embodiment will be described. Fig.10 as well as Fig.11 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the present embodiment.

[0087] First, relatively Figure 6 The construction of the state shown, such as Fig.10 For example, the p-type semiconductor layer 5A is formed to cover the inside of the trench structure 100 and the outside of the trench structure 100 (specifically, the top of the trench structure 100 where the anode electrode 2 is formed and a portion of the upper surface of the n-type gallium oxide epitaxial layer 6 that is exposed without the anode electrode 2). The method for forming the p-type semiconductor layer 5A is not particularly limited, and for example, there is a method of forming the p-type semiconductor layer 5A having desired physical properties using a method such as a sputtering method or a PLD method.

[0088] Next, if Fig.11 For example, in the terminal structure, a field plate insulating material layer 3 is formed on the upper surface of the exposed n-type gallium oxide epitaxial layer 6 and the upper surface of the p-type semiconductor layer 5A. The method for forming the field plate insulating material layer 3 is not particularly limited, and for example, it can be formed using a plasma CVD method, a sputtering method, or a SOG method.

[0089] Finally, the anode electrode 1 is formed on the upper surface of the p-type semiconductor layer 5A and the upper surface of the field plate insulating material layer 3, thereby completing the Fig. 9 The semiconductor device according to this embodiment is illustrated.

[0090] <Third Embodiment>

[0091] In the following description, components identical to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted.

[0092] <About the Structure of Semiconductor Device>

[0093] Fig.12 2 is a cross-sectional view schematically illustrating the structure of the semiconductor device of this embodiment. The method for manufacturing the semiconductor device of this embodiment is substantially the same as the method for manufacturing the semiconductor device of the first embodiment and the second embodiment.

[0094] exist Fig. 9 In the semiconductor device shown in FIG. 1 , a p-type semiconductor layer 5A is also formed on the top of the trench structure 100 in the active region. Fig.12 In the semiconductor device of the present embodiment shown, the p-type change layer 4 is formed on the top of the trench structure 100 in the active region so as to cover the upper surface of the anode electrode 2 .

[0095] The p-type change layer 4 is a layer having lower electrical resistance than the p-type semiconductor layer 5A. When the p-type semiconductor layer 5A is, for example, an oxide semiconductor, it is preferably reduced and metalized (lower electrical resistance). In addition, the p-type semiconductor layer 5B is formed in the portion where the p-type change layer 4 is not formed (except the top of the outside of the trench structure 100, the inside of the trench structure 100, and the side of the anode electrode 2). The electrical resistance of the p-type change layer 4 is lower than the electrical resistance of the p-type semiconductor layer 5A.

[0096] The method for forming the p-type change layer 4 is not particularly limited. For example, the p-type semiconductor layer 5A can be changed into a low resistance layer (i.e., the p-type change layer 4) by plasma treatment. Here, in the plasma treatment, a gas such as helium, argon, hydrogen, nitrogen, or oxygen can be used. Due to these gases, the p-type change layer 4 contains at least one of helium, argon, hydrogen, nitrogen, and oxygen.

[0097] When the p-type change layer 4 is formed on the upper surface of the outer portion of the trench structure 100 in the active region, the resistance between the anode electrode 1 and the anode electrode 2 becomes low. Therefore, the resistance of the semiconductor device itself can be reduced. In addition, the p-type semiconductor layer 5 can be changed into the p-type change layer 4 by plasma treatment using argon gas, so even materials with high etching resistance and difficult to process can be reduced in resistance.

[0098] <About Method of Manufacturing Semiconductor Device>

[0099] Next, refer to Figure 12 to Figure 14 A method for manufacturing an oxide semiconductor device as a semiconductor device of this embodiment will be described. Fig.13 as well as Fig.14 It is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the present embodiment.

[0100] First, relatively Fig.10 The construction of the state shown, such as Fig.13 As an example, plasma irradiation is performed on the top of the trench structure 100 where the anode electrode 2 is formed. As a result, the p-type semiconductor layer 5A formed on the upper surface of the anode electrode 2 is changed to form the p-type change layer 4 .

[0101] Next, if Fig.14 For example, in the termination structure, a field plate insulating material layer 3 is formed on a portion of the upper surface of the p-type change layer 4, the upper surface of the exposed n-type gallium oxide epitaxial layer 6, and the upper surface of the p-type semiconductor layer 5B. The method for forming the field plate insulating material layer 3 is not particularly limited, and for example, it can be formed using a plasma CVD method, a sputtering method, or a SOG method.

[0102] Finally, the anode electrode 1 is formed on the upper surface of the p-type change layer 4, the upper surface of the p-type semiconductor layer 5A, and the upper surface of the field plate insulating material layer 3, thereby completing the Fig.12 The semiconductor device according to this embodiment is illustrated.

[0103] <Effects Produced by the Multiple Embodiments Described Above>

[0104] Next, examples of the effects produced by the above-described multiple embodiments are shown. In addition, in the following description, the effects are recorded based on the specific structures exemplified by the above-described multiple embodiments, but they can also be replaced with other specific structures exemplified in the specification of this application within the scope of producing the same effects. That is, for the convenience of description, sometimes only one of the corresponding specific structures is recorded representatively, but the specific structure recorded representatively can also be replaced with other corresponding specific structures.

[0105] In addition, the replacement may be performed across a plurality of embodiments. That is, each structure illustrated in different embodiments may be combined to produce the same effect.

[0106] According to the above-described embodiment, the semiconductor device includes a first conductive type gallium oxide layer, a first anode electrode, a second conductive type semiconductor layer, and a second anode electrode. Here, the gallium oxide layer corresponds to, for example, the n-type gallium oxide epitaxial layer 6. In addition, the first anode electrode corresponds to, for example, the anode electrode 2. In addition, the semiconductor layer corresponds to, for example, the p-type semiconductor layer 5, the p-type semiconductor layer 5A, the p-type semiconductor layer 5B, etc. In addition, the second anode electrode corresponds to, for example, the anode electrode 1. The anode electrode 2 is provided on a portion of the upper surface of the n-type gallium oxide epitaxial layer 6. The p-type semiconductor layer 5 is provided to cover a portion of the n-type gallium oxide epitaxial layer 6 and at least a portion of the anode electrode 2. The anode electrode 1 is provided to cover the p-type semiconductor layer 5. In addition, a plurality of grooves are provided on the surface of the n-type gallium oxide epitaxial layer 6. Here, the grooves correspond to, for example, the groove structure 100. Moreover, the anode electrode 2 is provided on the surface of the n-type gallium oxide epitaxial layer 6 that does not overlap with the groove structure 100 when viewed from above. Furthermore, the p-type semiconductor layer 5 is provided so as to cover the n-type gallium oxide epitaxial layer 6 inside the trench structure 100 .

[0107] According to such a structure, leakage current can be suppressed. Specifically, by forming the anode electrode 2 at the top of the trench structure 100, a structure is formed in which the Schottky junction formed between the lower surface of the anode electrode 2 and the top of the trench structure 100 is protected by the anode electrode 2. Therefore, in the manufacturing process after forming this structure, the Schottky junction formed between the lower surface of the anode electrode 2 and the top of the trench structure 100 is not damaged. Thus, it is possible to suppress the increase of leakage current due to damage to the Schottky junction.

[0108] In addition, even when other structures exemplified in the specification of the present application are appropriately added to the above-mentioned structure, that is, when other structures in the specification of the present application that are not mentioned as the above-mentioned structure are appropriately added, the same effect can be produced.

[0109] In addition, according to the above-described embodiment, the p-type semiconductor layer 5A (p-type semiconductor layer 5B) is provided on the bottom surface and the side surface of the inside of the trench structure 100. Furthermore, the anode electrode 1 is provided in the inside of the trench structure 100 surrounded by the p-type semiconductor layer 5A (p-type semiconductor layer 5B). According to such a structure, the element resistance can be reduced compared to the case where the inside of the trench structure 100 is entirely buried with the p-type semiconductor layer.

[0110] In addition, according to the above-described embodiment, the p-type semiconductor layer 5 is composed of a metal oxide material. According to such a structure, the p-type semiconductor layer 5 can exhibit p-type conductivity even without adding p-type impurities. In addition, the heterogeneous pn junction between the p-type semiconductor layer 5 and the n-type gallium oxide epitaxial layer 6 is formed by the oxides, and the stability is improved.

[0111] In addition, according to the above-described embodiment, the metal oxide material is copper oxide, silver oxide, nickel oxide or tin oxide. According to such a structure, the p-type semiconductor layer 5 can exhibit p-type conductivity even without adding p-type impurities. In addition, the heterogeneous pn junction between the p-type semiconductor layer 5 and the n-type gallium oxide epitaxial layer 6 is formed by the oxides, and the stability is improved.

[0112] In addition, according to the above-described embodiment, the semiconductor device includes a second conductivity type variable layer provided to cover the upper surface of the anode electrode 2. Here, the variable layer corresponds to, for example, the p-type variable layer 4. The p-type semiconductor layer 5B is provided to cover the side of the anode electrode 2. Moreover, the electrical resistance of the p-type variable layer 4 is lower than the electrical resistance of the p-type semiconductor layer 5B. In addition, with respect to the p-type semiconductor layer 5B and the p-type variable layer 4, a part of the semiconductor layer formed integrally may be changed into the p-type variable layer 4 by plasma irradiation, or they may be formed separately and independently. According to such a structure, the electrical resistance between the anode electrode 2 and the anode electrode 1 can be reduced, so the on-resistance of the device can be reduced.

[0113] In addition, according to the above-described embodiment, the p-type change layer 4 contains at least one of helium, argon, hydrogen, nitrogen, and oxygen. According to such a structure, by forming the p-type change layer 4 from the p-type semiconductor layer by plasma irradiation using at least one of helium, argon, hydrogen, nitrogen, and oxygen, it is possible to reduce the resistance of a material with high etching resistance (and difficult to process).

[0114] According to the above-described embodiment, in the method for manufacturing a semiconductor device, the anode electrode 2 is provided on a portion of the upper surface of the first conductive type n-type gallium oxide epitaxial layer 6. Furthermore, etching is performed on the surface of the n-type gallium oxide epitaxial layer 6 using the anode electrode 2 as a mask to provide a plurality of trench structures 100. Furthermore, the second conductive type p-type semiconductor layer 5 is provided so as to cover a portion of the n-type gallium oxide epitaxial layer 6 including the inside of the trench structure 100 and at least a portion of the anode electrode 2. Furthermore, the anode electrode 1 is provided so as to cover the p-type semiconductor layer 5.

[0115] According to such a structure, leakage current can be suppressed. In addition, the trench structure 100 is formed using the anode electrode 2 as an etching mask, the anode electrode 2 is left as it is, and the p-type semiconductor layer 5 is formed to cover the inside and outside of the trench structure 100, so that the JBS element can be easily manufactured without removing the p-type semiconductor layer 5 (no need to perform flattening and other processing). In addition, since the processing of the p-type semiconductor layer 5 is not required, the damage to the p-type semiconductor layer 5 generated during the processing is also suppressed, which can improve the stability of the Schottky interface.

[0116] Furthermore, the order in which each process is performed can be changed without particular limitation.

[0117] In addition, even when other structures exemplified in the specification of the present application are appropriately added to the above-mentioned structure, that is, when other structures in the specification of the present application that are not mentioned as the above-mentioned structure are appropriately added, the same effect can be produced.

[0118] In addition, according to the above-described embodiment, in the method for manufacturing a semiconductor device, the p-type change layer 4 of the second conductivity type is provided so as to cover the upper surface of the anode electrode 2. Here, the p-type semiconductor layer 5B is provided so as to cover the side surface of the anode electrode 2. In addition, the electrical resistance of the p-type change layer 4 is lower than the electrical resistance of the p-type semiconductor layer 5B. According to such a structure, the electrical resistance between the anode electrode 2 and the anode electrode 1 can be reduced, so the resistance of the device can be reduced.

[0119] In addition, according to the above-described embodiment, the p-type change layer 4 is formed by irradiating the p-type semiconductor layer 5A covering the upper surface of the anode electrode 2 with plasma. According to such a structure, by forming the p-type change layer 4 from the p-type semiconductor layer by plasma irradiation using at least one of helium, argon, hydrogen, nitrogen and oxygen, it is possible to reduce the resistance of a material with high etching resistance (and difficult to process).

[0120] <Regarding Modifications of the Multiple Embodiments Described Above>

[0121] In the multiple embodiments described above, the material, size, shape, relative arrangement relationship or implementation conditions of each component are sometimes described, but these are merely examples in all aspects and are not restrictive.

[0122] Therefore, numerous modifications and equivalents not shown in the examples are conceivable within the scope of the technology disclosed in the present specification, including, for example, the case where at least one component is modified, the case where at least one component is added, or the case where at least one component is omitted, and the case where at least one component in at least one embodiment is extracted and combined with components in other embodiments.

[0123] In at least one embodiment described above, when a material name or the like is described without particular designation, the material includes other additives, for example, an alloy, etc., unless a contradiction occurs.

[0124] Furthermore, when the above-described embodiment states that “one” component is included, “one or more” of the component may be included unless a contradiction occurs.

[0125] Furthermore, each component in the above-described embodiments is a conceptual unit, and within the scope of the technology disclosed in the present application specification, it includes a case where one component is composed of multiple structures, a case where one component corresponds to a part of a certain structure, and further a case where multiple components are arranged in one structure.

[0126] In addition, as long as the respective components in the above-described embodiments exhibit the same function, structures having other structures or shapes are included.

[0127] In addition, the descriptions in the specification of the present application are referenced for all purposes related to the present technology and are not considered to be prior arts.

[0128] (Explanation of symbols)

[0129] 1: anode electrode; 2: anode electrode.

Claims

1. A semiconductor device comprising: A gallium oxide layer of a first conductivity type; a first anode electrode disposed on a portion of the upper surface of the gallium oxide layer; a second conductivity type semiconductor layer provided to cover a portion of the gallium oxide layer and at least a portion of the first anode electrode; and a second anode electrode, arranged to cover the semiconductor layer; A plurality of grooves are provided on the surface of the gallium oxide layer, The first anode electrode is provided on the surface portion of the gallium oxide layer which does not overlap with the groove in a plan view. The semiconductor layer is provided so as to cover the gallium oxide layer inside the trench.

2. The semiconductor device according to claim 1, wherein The semiconductor layer is disposed on the bottom surface and the side surface of the interior of the trench, The second anode electrode is provided in the interior of the trench so as to be surrounded by the semiconductor layer.

3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor layer is made of metal oxide material.

4. The semiconductor device according to claim 3, wherein: The metal oxide material is copper oxide, silver oxide, nickel oxide or tin oxide.

5. The semiconductor device according to any one of claims 1 to 4, wherein: further comprising a second conductivity type variable layer provided to cover the upper surface of the first anode electrode, The semiconductor layer is provided so as to cover the side surface of the first anode electrode. The electrical resistance of the change layer is lower than the electrical resistance of the semiconductor layer.

6. The semiconductor device according to claim 5, wherein: The variable layer contains at least one of helium, argon, hydrogen, nitrogen and oxygen.

7. A method for manufacturing a semiconductor device, A first anode electrode is provided on a portion of the upper surface of the first conductivity type gallium oxide layer. A plurality of grooves are formed in the surface portion of the gallium oxide layer by etching using the first anode electrode as a mask, A second conductivity type semiconductor layer is provided so as to cover a portion of the gallium oxide layer including the interior of the trench and at least a portion of the first anode electrode, A second anode electrode is provided so as to cover the semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: A second conductivity type variable layer is further provided in a manner covering the upper surface of the first anode electrode, The semiconductor layer is provided so as to cover the side surface of the first anode electrode. The electrical resistance of the change layer is lower than the electrical resistance of the semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The change layer is formed by irradiating the semiconductor layer covering the upper surface of the first anode electrode with plasma.

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