Layered structure of super-power photovoltaic TMBS chip

Abstract

The utility model discloses a superpower photovoltaic TMBS chip layered structure, which comprises a lining plate and an epitaxial layer, the epitaxial layer is arranged on the top of the lining plate, a Schottky barrier layer is arranged on the top of the epitaxial layer, the Schottky barrier layer comprises a Schottky contact layer, the Schottky contact layer is arranged on the top of the epitaxial layer, and the Schottky contact layer is arranged on the top of the epitaxial layer. A field plate layer is arranged on the outer edge of the Schottky contact layer and located on the top of the epitaxial layer, and a protective layer is arranged on the top of the epitaxial layer and located on the outer surface of the field plate layer. According to the layered structure of the super-power photovoltaic TMBS chip, the aluminum nitride film layer is deposited on the outer layer of the device, and the passivation layer formed by silicon nitride is passivated, so that the device can conduct and dissipate heat through the aluminum nitride film layer, and can isolate the external environment through the passivation layer to prevent the influence of moisture, pollutants and mechanical damage on the performance of the device.

Description

TECHNICAL FIELD

[0001] The utility model relates to diode technical field, concretely is a layered structure of superpower photovoltaic TMBS chip. BACKGROUND

[0002] TMBS is trench MOS barrier schottky diode, it has the ability to bear high forward surge and low to 0.3V forward voltage drop, thereby can reduce power loss. This characteristic makes it have important application value in photovoltaic and other fields, can improve the efficiency of entire photovoltaic system.

[0003] In photovoltaic system, the reduction of power loss means that more solar energy can be effectively converted into electric energy, improves the power generation efficiency of photovoltaic cell. Meanwhile, due to its ability to bear high forward surge, the chip can also work stably under complex illumination conditions, guaranteeing the reliability of photovoltaic system.

[0004] Although the prior art is convenient to reduce power loss, it still has some shortcomings, the chip lacks a heat dissipation layered mechanism, which leads to the problem that the device is prone to long-term high-temperature working conditions, therefore, a layered structure of superpower photovoltaic TMBS chip is proposed to solve the existing problems. CONTENT OF THE UTILITY MODEL

[0005] In view of the shortcomings of the prior art, the utility model provides a layered structure of superpower photovoltaic TMBS chip, which solves the problem that the chip lacks a heat dissipation layered mechanism, leading to the problem that the device is prone to long-term high-temperature working conditions.

[0006] To achieve the above purpose, the utility model realizes the following technical scheme: a layered structure of superpower photovoltaic TMBS chip, comprising a backing plate and an epitaxial layer, the epitaxial layer is arranged on the top of the backing plate, the top of the epitaxial layer is provided with a schottky barrier layer, the schottky barrier layer comprises a schottky contact layer, the schottky contact layer is arranged on the top of the epitaxial layer, the outer edge of the schottky contact layer and the top of the epitaxial layer are provided with a field plate layer, and the top of the epitaxial layer and the outer surface of the field plate layer are provided with a protective layer.

[0007] Preferably, the backing plate and the epitaxial layer are provided with an aluminum nitride layer on the opposite side, the top metal layer and the bottom metal layer are arranged on the opposite side of the two aluminum nitride layers respectively, and the top metal layer and the bottom metal layer are provided with a graphene layer on the opposite side.

[0008] Preferably, the outer surfaces of the backing plate, the epitaxial layer, the schottky barrier layer and the graphene layer are provided with an aluminum nitride film layer, and the surface of the aluminum nitride film layer is provided with a passivation layer.

[0009] Preferably, the top of the aluminum nitride film layer has an upper pin connection hole that matches the top metal layer.

[0010] Preferably, the upper pin connection hole extends through to the outside of the passivation layer.

[0011] Preferably, the bottom of the aluminum nitride film layer is provided with a lower pin connection hole that is compatible with the bottom metal layer.

[0012] Preferably, the lower pin connection hole extends through to the outside of the passivation layer.

[0013] Beneficial effects

[0014] This invention provides a layered structure for an ultra-high power photovoltaic TMBS chip. Compared with existing technologies, it has the following advantages:

[0015] (1) The layered structure of the ultra-high power photovoltaic TMBS chip, by depositing an aluminum nitride film layer and passivating a passivation layer formed by silicon nitride on the outer layer of the device, enables the device to conduct heat dissipation through the aluminum nitride film layer and isolate the external environment through the passivation layer to prevent the influence of moisture, pollutants and mechanical damage on the device performance.

[0016] (2) The layered structure of the ultra-high power photovoltaic TMBS chip, by setting a field plate layer and a protective layer between the Schottky contact layer and the epitaxial layer, enables the electric field concentration effect to be reduced, edge leakage current to be suppressed, electric field intensity to be dispersed, breakdown risk to be reduced, electric field distribution to be optimized and device reliability to be improved during the use of the device through the cooperation of the field plate layer and the protective layer.

[0017] (3) The layered structure of the ultra-high power photovoltaic TMBS chip, by setting graphene layers on the surfaces of the top metal layer and the bottom metal layer, enables the graphene layers to reduce contact resistance and optimize contact characteristics.

[0018] (4) The layered structure of the ultra-high power photovoltaic TMBS chip, by setting an aluminum nitride layer on the opposite side of the substrate and the epitaxial layer, enables the device to conduct heat dissipation through the aluminum nitride layer, reducing the thermal resistance of the device and improving the reliability under high temperature environment. In addition, the thermal expansion coefficient of the aluminum nitride layer matches the semiconductor material, which can also reduce device failure caused by thermal stress. Attached Figure Description

[0019] Fig. 1 This is a schematic diagram of the external structure of this utility model;

[0020] Fig. 2 This is a top view of the Schottky barrier layer structure of this utility model;

[0021] Fig. 3 This is a top view of the passivation layer structure of this utility model.

[0022] In the diagram: 1. Backing plate; 2. Epitaxial layer; 3. Schottky barrier layer; 31. Schottky contact layer; 32. Field plate layer; 33. Protective layer; 4. Aluminum nitride layer; 5. Top metal layer; 6. Bottom metal layer; 7. Graphene layer; 8. Aluminum nitride film layer; 9. Passivation layer; 10. Upper lead connection hole; 11. Lower lead connection hole. Detailed Implementation

[0023] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.

[0024] Please see Figs. 1-3 This utility model provides a technical solution: a layered structure of an ultra-high power photovoltaic TMBS chip, including a substrate 1 and an epitaxial layer 2. The epitaxial layer 2 is disposed on the top of the substrate 1. As explained in detail: the substrate 1 is made of silicon carbide, and the epitaxial layer 2 is made of N-type doped silicon. By combining the two, the electrical performance of the device can be optimized and the on-resistance can be reduced.

[0025] Furthermore, to facilitate the reduction of electric field concentration effect and suppress edge leakage current, a Schottky barrier layer 3 is disposed on the top of the epitaxial layer 2. The Schottky barrier layer 3 includes a Schottky contact layer 31, which is disposed on the top of the epitaxial layer 2. A field plate layer 32 is disposed on the outer edge of the Schottky contact layer 31 and on the top of the epitaxial layer 2. A protective layer 33 is disposed on the top of the epitaxial layer 2 and on the outer surface of the field plate layer 32. For detailed explanation: the Schottky contact layer 31 is deposited from a platinum low work function metal, the field plate layer 32 is made of silicon dioxide, and the protective layer 33 is a protective ring formed by ion implantation.

[0026] Furthermore, to facilitate heat conduction and optimize contact characteristics, aluminum nitride layers 4 are provided on the opposite sides of the substrate 1 and the epitaxial layer 2. A top metal layer 5 and a bottom metal layer 6 are provided on the opposite sides of the two aluminum nitride layers 4, respectively. A graphene layer 7 is provided on the opposite sides of the top metal layer 5 and the bottom metal layer 6. The graphene layer 7 has high electron mobility, which significantly reduces contact resistance and improves device efficiency.

[0027] Furthermore, to facilitate subsequent pin connection and assembly, an aluminum nitride film layer 8 is jointly provided on the outer surfaces of the substrate 1, epitaxial layer 2, Schottky barrier layer 3, and graphene layer 7. The aluminum nitride film layer 8 is used to optimize heat dissipation. A passivation layer 9 is provided on the surface of the aluminum nitride film layer 8. An upper pin connection hole 10 is opened at the top of the aluminum nitride film layer 8 to match the top metal layer 5, and the upper pin connection hole 10 extends through to the outside of the passivation layer 9. A lower pin connection hole 11 is opened at the bottom of the aluminum nitride film layer 8 to match the bottom metal layer 6, and the lower pin connection hole 11 extends through to the outside of the passivation layer 9. For detailed explanation, the passivation layer 9 is made of silicon nitride and its function is insulation and moisture protection.

[0028] The fabrication steps of the layered structure of this ultra-high power photovoltaic TMBS chip are as follows:

[0029] S1. Select silicon carbide wafer as the material of substrate 1. After cleaning the surface of substrate 1, grow a high-quality epitaxial layer 2 on the surface of substrate 1 by chemical vapor deposition.

[0030] S2. A low work function metal platinum layer is deposited on the surface of the epitaxial layer 2 using physical vapor deposition to form a Schottky contact layer 31. Subsequently, a field plate layer 32 made of silicon dioxide is deposited and introduced at the edge of the Schottky contact layer 31.

[0031] S3. Ion implantation is performed on the top of the epitaxial layer 2 and the periphery of the Schottky contact layer 31 to form a protective layer 33 around the Schottky contact layer 31. Then, aluminum and nitrogen atoms are deposited on the opposite sides of the substrate 1 and the epitaxial layer 2 respectively using a molecular beam source to form an aluminum nitride layer 4.

[0032] S4. On the opposite side of the two aluminum nitride layers 4, a top metal layer 5 and a bottom metal layer 6 are formed by depositing copper for contact with external pins. Then, graphene is deposited on the surface of the top metal layer 5 and the bottom metal layer 6 to form a graphene layer 7. Finally, an aluminum nitride film layer 8 is deposited on the outer surface of the above-mentioned outer surface. A silicon nitride layer is passivated on the outer surface of the aluminum nitride film layer 8 to form a passivation layer 9.

Claims

1. A layered structure of a super-power photovoltaic TMBS chip comprising a substrate (1) and an epitaxial layer (2) disposed on top of the substrate (1), characterized in that: The top of the epitaxial layer (2) is provided with a Schottky barrier layer (3), the Schottky barrier layer (3) comprises a Schottky contact layer (31), the Schottky contact layer (31) is arranged on the top of the epitaxial layer (2), the outer edge of the Schottky contact layer (31) and the top of the epitaxial layer (2) are provided with a field plate layer (32), and the top of the epitaxial layer (2) and the outer surface of the field plate layer (32) are provided with a protective layer (33).

2. A layered structure of a super-power photovoltaic TMBS chip according to claim 1, characterized in that: The back of the backing plate (1) and the epitaxial layer (2) is provided with an aluminum nitride layer (4), the back of the two aluminum nitride layers (4) is respectively provided with a top metal layer (5) and a bottom metal layer (6), and the back of the top metal layer (5) and the bottom metal layer (6) is provided with a graphene layer (7).

3. A layered structure of a super-power photovoltaic TMBS chip according to claim 2, characterized in that: The outer surfaces of the backing plate (1), the epitaxial layer (2), the Schottky barrier layer (3) and the graphene layer (7) are collectively provided with an aluminum nitride film layer (8), and the surface of the aluminum nitride film layer (8) is provided with a passivation layer (9).

4. A layered structure of a super-power photovoltaic TMBS chip according to claim 3, characterized in that: The top of the aluminum nitride film layer (8) is provided with an upper pin connecting hole (10) matched with the top metal layer (5).

5. A layered structure of a super-power photovoltaic TMBS chip according to claim 4, characterized in that: The upper pin connecting hole (10) extends to the outside of the passivation layer (9).

6. A layered structure of a super-power photovoltaic TMBS chip according to claim 3, characterized in that: The bottom of the aluminum nitride film layer (8) is provided with a lower pin connecting hole (11) matched with the bottom metal layer (6).

7. A layered structure of a super-power photovoltaic TMBS chip according to claim 6, characterized in that: The lower pin connecting hole (11) extends to the outside of the passivation layer (9). The bottom of the aluminum nitride film layer (8) is provided with a lower pin connecting hole (11) matched with the bottom metal layer (6).

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